TW379301B - Data processor and data processing method - Google Patents

Abstract

The invention relates to a data processor in a microprocessor or micro computer, in particular, a data processor for executing image processing application programs such as two-dimensioinal discrete cosine transform and two-dimensional discrete inverse cosine transform. The basic structure of high-speed two-dimensional discrete cosine transofrm and two-dimensional discrete inverse cosine transform comprises: a computation circuit with accumulators to linearly transform the corresponding vectors of element 4 and the first register file to store the 4x4 matrix and the second register file for storing the vectors of element 4 for linear transform and the third register file for storing the result of the linear transform at the same time, the computation commands for the vector of the first register file and second register file, with two types of row-column vector operation commands, when the first kind of row-column operations are executed, the reading-out direction of the values from the first register file is defined to be the row direction, when the second kind of row-column operations are executed, the reading-out direction of the values from the first register file is defined to be the column direction.

Description

Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. A7 B7 V. Description of the invention) 1. TECHNICAL FIELD The present invention relates to a data processing device such as a microprocessor or a microcomputer, and more particularly to the implementation of a discrete cosine transform or 2 Appropriate data processing devices for image processing applications such as inverse discrete cosine transform. Background technology When the image data is not processed, there are large amounts of data. When storing image data, large-capacity memory and data When transmitting, it takes a long time to transmit. The following measures are taken here: compress the image data before storing it in the memory, and stretch it before using it, compress the image data before transmitting it, and extend it after receiving. Let's take the example of the M image and the elongation of the image, taking the encoding of the still image according to the J PEG specification as an example. In the J P E G specification, compression is a method of combining two of the following. / (1) 2D discrete cosine transform (DCT) (2) Huffmann coding _ (Huffmann coding) On the other hand, it is extended to combine the following two methods. (3) Huffman decoding * (4) 2 dimensional inverse discrete cosine transform. The above-mentioned two-dimensional discrete cosine transform (1) is performed on a unitary group of two-dimensional blocks of 8 x 8 pixels. Specifically, ′ is a product obtained by multiplying a unitary group of a two-dimensional block of 8 × 8 pixels and a determinant of a base called D C T. Therefore, the conversion result (referred to as the 0 CT coefficient) is also applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) for this paper size —I; ------ dl «(Please read the precautions on the back before (Fill in this page)-Order printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7 _____B7______ 5. Description of the invention (2) Become a group of 8-by-8-pixel 2-dimensional cubes. The transformed DCT coefficients are quantized using a quantization table having a different 値 at each coefficient position (the process of replacing 値 in a certain interval with a representative 値 in the interval). In the two-dimensional discrete cosine transform of image data, generally, the lower right part of the transformed square _ is close to 0 値. In the quantization process, most of these have the characteristics of becoming 0. The above Huffman coding (2) is a process of transforming the quantized 8 × 8 pixel block unitary group into a bitstream. In this case, encoding is performed using more than 値 0 points in an 8 × 8 pixel block. That is, those who have a high probability of appearing in the signal frame are assigned a short bit string encoding to perform a variable length encoding. As a result, the number of bytes of the bit flux after encoding becomes 1/1 0 of the number of bytes of the data before conversion. · The above Huffman decoding (3) is the inverse processing of the Huffman coding (2). That is, the process of restoring the bit flux to a unitary group of 8 × 8 pixel squares. The 2D inverse discrete cosine transform (4) is an inverse transform process of the 2D inverse discrete cosine transform (1). That is, the unitary group of the 8 × 8 pixel block is subjected to the inverse processing of the 2D discrete cosine transform (1), and is restored to the unitary group of the original 8 × 8 pixel block. Specifically, the multiplication of the decoded 8 × 8 pixel square unitary group (DCT coefficients) and the DCT base through Huffman decoding processing to obtain the product makes the image data restored. Furthermore, through the quantization performed in the above-mentioned 2D discrete cosine transform (1), the unitary group of 8 X 8 pixel squares before the 2D discrete cosine transform and 8 X after the above 2D discrete cosine transform (4) The group of 8-pixel squares is not strictly consistent. That is, it is irreversibly compressed and stretched. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

A 7 _________B7_____ V. Description of the invention (3) Long processing. However, in the non-extreme rough quantization, the difference between the existing image and the restored image can hardly be distinguished by the human eye. There is no practical problem. The above explains the image data through image compression. The required number of bytes becomes about 1/1 0, and the storage efficiency or transfer efficiency of the memory device becomes about 10 times the advantage. However, on the other hand, there are disadvantages in that the procedures and time required for the compression / expansion processing of image data are increased. For example, when the image data is stored in a memory device without compressing the image data, the image data can be used immediately after being read out from the memory device. However, when the compressed image data is stored in the device, the image data is read out by the device, and then it is stretched and restored to the original image data. Yin Ben, an employee consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Before the present inventors, the image data was compressed / extended through a general-purpose microprocessor. Every 8 X 8 pixel block is subjected to the Huffman encoding processing (2) and (: 3) and the Huffman decoding processing. Each of the execution commands needs to be about 1,000. (1), ·: (4) Discrete cosine transform and inverse. Discrete cosine transform processes each require a degree of between 100 and 2000. Therefore, in the encoding of (1) and (2) or the decoding of (3) and (4), each 8x8 pixel block requires a number of commands of the order of 2 0 0-3 0 0 0 . Therefore, when the number of commands required for each colored image of 640 x 480 pixels is simply converted, each color is 480 times the above-mentioned processing, and the entire order must be implemented by 1400 times. That is, in previous microprocessors, when encoding or decoding image data, 28.8M-43.2M per image was required (M means millions [MEGA]). This paper standard applies to China. National Standard (CNS) A4 specification (210X 297 mm) ~~ The implementation of the order of the extent that A7 B7 is printed by Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (5) Invention Description (4)). Here, the processing of the "1 command is set on the average when one clock pulse is required" when the microprocessor operates at 100 MHz. It is understood that a processing time of 2 8 8-4 3 2 m seconds is required for each image. At this processing speed, even when a still image is to be continuously displayed, there is a processing speed of 2 to 4 frames per 1 second. Therefore, it is difficult to produce an animation effect with the continuous display of a still image. Here, the size of the screen is reduced. “Special hardware for compression or expansion is prepared ingeniously. Algorithms are introduced to reduce the number of commands.” The mechanical language implementation method that can process two or more commands in one clock pulse is implemented ( superscalar), waiting for the effort is necessary. Also, in the above description, in the processing of (1) or (4), it has been explained that each 8x8 pixel block needs 1000-2000 commands. When there is no simple algorithm with special effort, it is 2000. The degree of command 'When the clever algorithm is worked hard, it means the meaning of 100 command levels. An object of the present invention is to provide a data processing device capable of performing a 'two-dimensional discrete cosine transform or a two-dimensional inverse discrete cosine transform at high speed. The object of the present invention is to provide the basic mechanism of the data processing device necessary for high-speed implementation of the two-dimensional discrete cosine transform or the two-dimensional inverse discrete cosine transform (the minimum required hardware conditions), and the form of the command to effectively use it and the introduction The basic mechanism of control of the order. The above and other objects and new features of the present invention will become clear from the description of the detailed description and the attached drawings. The disclosure of the invention reveals that the paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling out this page)-* Γ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (5) Among the inventions disclosed in the present patent application, a brief description of the main points of the representative is as follows. That is, in the present invention, the basic mechanism for high-speed implementation of the two-dimensional discrete cosine transform or the two-dimensional inverse discrete cosine transform is an arithmetic circuit that prepares a product summator having the number of elements corresponding to the vector line deformation of the number of elements 4 /. In addition, a first register file for storing 4 X 4 rows and a linear transformation, and a second register file for storing a vector of the number 4 of elements to be subjected to the linear transformation, and a third register file for storing the result of the linear transformation are prepared. . In addition, as the operation command of the vector of the first register slot and the vector of the second register file, the first type of row and column operation command and the second type of row and column operation command are prepared. When the first type of row and column operation command is executed, The reading direction of each frame of the first register file is set to the row direction, and when the second type of row and column calculation command is executed, the arithmetic circuit is set to the column direction. Based on this, when there are two register files or when the rank calculation command is one type, it is necessary to correct the data in the register file during the calculation when the two-dimensional discrete cosine transform or the two-dimensional inverse discrete cosine transform is used. The storage person applies the present invention, so that the correction storage of the register file becomes unnecessary, and as a result, the 2D discrete cosine transform or the 2D inverse discrete cosine transform can be performed at high speed. Best Mode for Carrying Out the Invention An embodiment of the present invention will be described below with reference to the drawings. In Fig. 1, a block diagram of a suitable microprocessor to which the present invention is applied is shown. In Figure 1, 1 is the central processing unit (hereinafter referred to as the CPU). This paper size is applicable to the Chinese national standard (CNS M4 specification (210X297 mm)) β {Please read the precautions on the back before filling this page)

A 7 _________B7 V. Description of the invention (6) 2 is a co-processor (hereinafter referred to as FPU) that performs operations such as row-column product or floating decimal operation instead of CPU 1, and 3 is a circuit that accepts peripheral circuits 1 1, 1 2 Insertion request from 13 and exception processing request signal from MMU to be described later to determine the priority. For the above-mentioned CPU 1 output control signal IRQ interpolation control circuit, 4 is the above-mentioned CPU 1 output to the bus 8 a The above address signal conversion manages the memory management unit (MMU) of the imaginary memory, 5 is an address conversion circuit formed by converting a logical address into a physical address, and changing tables. In addition, 6 is a high-speed cache memory that stores frequently used programs or data through the above-mentioned CPU 1, and 7 is to monitor the address signals output from the above-mentioned CPU 1 on the bus, and follow the prescribed replacement algorithm to externally The data in the main memory (hard disk storage device, etc. outside the picture) is transmitted to the cache memory 6 in a predetermined block unit. The cache memory 6 is discarded and becomes unnecessary data, and the cache memory 6 is written The data is copied back or written through to make the memory 'in the master cache memory controller. This cache memory 6 and the external main memory are accessed via the physical address signals transformed by the address conversion table 5 described above. Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) The single-chip microprocessor of this embodiment is used to transmit the logical address signals and data signals output by the CPU 1. The logical address bus 8 a and the data bus 9 a are differently provided with a physical address bus 8 b for transmitting the physical address signal transformed in the upper address conversion table 5, and the upper cache Data bus 9b for transmitting data between the billion body 6 and the external main memory, and at the same time, an external bus interface circuit for setting an interface between the internal bus 8b, 9b and the external bus 10 paper size Applicable to China National Standard (CNS) A4 (2 丨 0 X 297 mm) A 7 ___B7_____ V. Description of the invention (7) ο · In this embodiment, it is different from the logical address side bus 8a , 9a or the physical address side buses 8b, 9b, in addition to the serial communication interface circuit for serial communication 1 1. or the instant pulse circuit with the function of the current time ^ monthly calendar, etc. 12, to the CPU 1 Timer The peripheral address clock circuit 13, etc. are connected to the peripheral circuit bus and a peripheral data bus 8 c 9 c. Furthermore, in FIG. 1, 14 are bus controllers that control the status of the buses 8 b and 9b on the physical address side and peripheral buses 8c and 9c. 15 is the use of a phase locked loop (PLL) ) The circuit generates the CPU 1 inside the chip and the clock pulse generation circuit of the clock pulse signals necessary for the operation of each circuit block. 16 is a watchdog timer for detecting hardware abnormalities. 17 is a peripheral confluence through the external interface circuit 10 described above. I / O port for data input and output between bus 8 c, 9 c and external bus. 18 is to provide user system development support for system errors, interrupt control for stopping program execution at any point. 〇Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Also, the CPU1 and circuit blocks (2 ~, 10 ~ 18, and SPF) shown in Figure 1 and the bus (8a to 8c, 9a to 9c) are formed on a semiconductor wafer 100 such as one of single crystal silicon substrates. In addition, although there is no particular limitation, in this embodiment, when the external main memory is composed of DRAM (Dynamic Random Access Memory), the update controller that performs the update operation is built in the above Inside the external bus interface circuit 10. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -10- Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 __B7_______ 5. Description of the invention (8) In Figure 2, the above CPU 1 Specific constitution examples. In Fig. 2, 20 represents the address of the executed command. '2 1 is the 3 2 bits of the command code obtained from the above-mentioned cache memory 6 or external main memory through the data bus 9 a. The command register 22 is a command decoder that decodes the command code taken into the command register 21 and generates a control signal. The command register 23 is a variety of general-purpose registers that hold the data before or after the operation. REG 1 ~ REG η and address calculation or data addition and subtraction, logical operation. Addition and subtraction device ALU, barrel line converter S FT for bit shifting of data, address output register ADR, data input and output register D A command execution circuit composed of TR and the like. The above-mentioned command execution circuit 2 3 is provided with an arithmetic bus BUS 1, 2, 3, via which the arithmetic bus BUS 1 ′ 2, 3, the above-mentioned registers REG1 to REGn, ADR, adder-subtractor ALU, barrel-shaped commutator SFT You can connect 'gates GT 1 ~ G Tm set between the buses of each register or processor through the above-mentioned command register 2 2 output control. Signals CS1 ~ Cs i are controlled by timing' The data of the corresponding command is Implemented. However, when c PIJ 1 judges that the command fetched into the command register 2 2 is a dedicated command for FPU (coprocessor) 2, the execution of this command is left to F P U 2, which itself is in a standby state or moves to the execution of the next command. In addition, a CPU is provided in the CPU 1 to reflect the status of the internal control state, such as the internal register SR, to avoid the contents of the status register SR when an exception occurs, and to avoid the contents of the register SSR and the program counter 2 0 when an exception occurs. When avoiding the register S PC and storing the indirect addressing mode, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

-11-A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs V. The basic address register GBR of the basic address of the invention description (9), the vector address register VBR that stores the vector address of exception processing or interrupt processing, etc. The control register 2 4 formed by the register is read and written through the output of the command decoder 2 2. The state of each bit is read and written. The content of the command is controlled according to the specified bit state in the control register 2 4. With. A specific configuration example of the FPU 2 is shown in FIG. 3. FPU2 is shown in Fig. 3, which includes: a sum product 9 including a possible row and column product of register sections 9 0 1 and 4 X 4; 10, 911, 912, 913 and four latches corresponding to each product sum The operation section 9 0 0 formed by the lock circuits 920, 921, 922, 9 2 3 and the latch circuit 9 2 4 commonly used in the above-mentioned summator, and the operation control section 9 9 which controls the operation section 9 0 0 according to a command. 0. Although not shown in the figure, the operation control unit 9 900 is composed of the same command register and command decoder as the CPU 1. The command fetched into the command register is determined as its own dedicated command (the first row and column operation command, the second row and column Calculation command, etc.), a control signal for the calculation unit 900 is formed so as to execute corresponding calculation processing. The command register and command decoder of FPU 2 can be configured in common with the command register and command decoder of CP1. An example of the configuration of the above-mentioned summators 910 to 913 is shown in FIG. 4. Each multiplier is formed by a multiplier 9 6 0 and an adder 9 6 1 and a temporary register 9 6 2 to form a 'multiplier 9 6 0. The 16-bit data supplied by the signal line 9 4 0, 9 4 4 is provided. The operation of the product of time. The above-mentioned adder 9 6 1 obtains the sum of the operation result of the multiplier 9 6 0 and the holding data of the temporary register 9 62 2 and stores the result in the temporary register. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297). Li) (Please read the notes on the back before filling in this page)

-12- A 7 _B7________ V. Description of the invention (彳.) 9 6 2 and update its content. Also, it is necessary to make the temporary register 9 62 2 be 0 before the product sum operation. In this embodiment, a signal line 937 and a selection element 963 are provided at the initial stage of supply "0", and the selection element 9 6 3 is set before the calculation is started. It is constituted by giving a control signal of "?" To the initial stage of selection through signal line 9 3 5 and storing _ in temporary register 9 6 2. A specific configuration of the register section 901 is shown in FIG. 5. The register section 901 is composed of four register files 500, 501, 502 '5 0 3 and corresponding to the above ... pin circuit 9 2 0, 9 2 1' 9 2 2 '923, 924 selection elements 550, 551' 552 '553,554 and 16 register files in the above register files 500' 501,502,503. These registers are divided into 4 sub-files "For example, register file 5 0 0 configuration by 4 The secondary files formed by the individual registers are 5 1 0 '5 1 1, 5 1 2, 5 1 3 0 Printed by the Shellfish Consumer Cooperative of the Central Bureau of Quasi-Ministry of Economic Affairs (please read the notes on the back before filling this page). Four registers are arranged in each of the auxiliary files, and a selection element 5 1 6 for defining the auxiliary files is set. Registers 0, 4, 8, 12 are allocated to the auxiliary file 5 1 1 and registers 1, 5, 9, 13 are allocated to the auxiliary file 512. Therefore, 16 registers from 0 to 15 can be identified by register numbers formed by 4-digit binary digits. Also, "9 3 6 is a signal line for giving a write permission control signal to a register file supply" 9 50 is a common signal line for supplying a write data to a register file. Each of the above-mentioned sub-files can be constituted by reading data from two registers and writing data from one register. Therefore, through signal lines 930, 931 and 932, the 4-bit paper size of the designated register is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -13- A7 _; _ B7_____ V. Description of the invention (n ) The upper 2 digits of the register number are entered into the auxiliary file. For example, for the auxiliary file 5 1 0, the data read from the register designated by the selection line number supplied through the signal line 9 3 0 is sent to the selection element 5 5 0, which is supplied in accordance with the signal line 9 3 4 The register data of the selection signal of the register file is selected. In addition, the data supervised by the register corresponding to the selection signal (the upper 2 digits of the register number) supplied through the signal line 9 3 1 is sent to the selection element 5 1 6 and the corresponding signal is supplied through the signal line 9 3 3 The register data of the selection signal (two digits below the register number) is selected. The write data sent through the signal line 9 50 is written to the register corresponding to the selection signal supplied through the signal line 9 3 2 when the signal permission of the signal line 9 3 6 is written. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page), and then explain the 2D discrete cosine transform or 2D inverse discrete cosine through the microprocessor of the present invention 'Before conversion' First, the nature of the matrix product of the conversion method of the present invention which is the basis for effective speedup will be explained. Let 8 × 8 rank M be defined by (Equation 1 — 1) in Figure 6. This rank M is the rank of the inverse discrete cosine transform. 'Replace some ranks or ranks of the discrete cosine transform to obtain this rank.' Below this rank The description of the present invention will be made. 4 × 4 ranks A ′ C are defined by (Expression 1-2) and (Expression 1-3) in FIG. 6. In this way, the rank M can be expressed as shown in Fig. 6 (Equation 1-4). The 8x8 rank X is defined by Fig. 7 (Equation 2-1). Apply this paper size to Chinese National Standard (CNS) A4 specification U10X297 mm) -14- A7 ___B7____ V. Description of the invention (12) Divide the rank X into 4 and divide the ranks of each part X 1, X 2 'X 3 'X4 is defined by (Expression 2-2), (Expression 2-3), (Expression 2-4), and (Expression 2-5) in FIG. In this way, the rank X can be expressed (Equation 2-6). Next, FIG. 8 is a diagram showing a calculation method in a case where the definition of the discrete cosine transform and its 〆 are decomposed into 4x4 partial ranks. (Equation 3— _1) is the definition f of the discrete cosine transform. Decompose the 8 X 8 rows and columns expressed in (Equation 3 — 1) into 4 X 4 partial rows and express them as (Equation 3-2). Substitute the rank M in (Formula 3-1) with the right side of (Formula 1_4), and replace the rank X in (Formula 3_1) with the right side of (Formula 2-6). Then, when this (Expression 3-2) is developed, it becomes (Expression 3-3), (Expression 3-4), (Expression 3-5). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). The four types of items shown in (Equations 3-5) are given respectively (Equations 3-6) ~ (Equations 3 — 9). In this way, the inverse discrete cosine transform can be calculated (Equation 3-1 0). Here / process the above (Equation 3-10) slightly. FIG. 9 is a diagram for explaining the processing. First, the respective elements of the 4 × 4 rows and columns 1, T2, T3, and T4 shown in (Equation 3-10) in FIG. 8 are assigned with the following (Equation 4-1) to (Equation 4-4). In addition, the constant row B of 4x4 is defined by (Equation 4-6), and the product of T and B (4X16 row) is defined by row S, that is, S = TB. Each of the six or four elements in the rank S is given a code that follows (Equation 4-7). In addition, using these numbers, Y is used to define 8x8 ranks as shown in (9) (Equation 4-8). In this way, the paper size defined by (Equation 4-8) applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 15- A7 _____B7____ V. Description of the invention (13) Y and Figure 8 (Equation 3 — 10) Y is the same as defined. For example, the upper left element of the 8X8 rank Y defined by (Expression 3-1 0) in Fig. 8 is added to the 4X4 rank Ti, T2, T3, T4 defined by (Expression 4-1) ~ The respective top left elements are t 10, t 20, t 30, and t 40. On the other hand, the element on the upper left of the 8X8 rank Y as defined in Figure 9 (Equation 4-8), S = TB, is given to the first row (1 1 1) to the right of B (Equation 4-6). 1) The inner product of the initial trip (t 1-10-t20t3 0t40) to the right of T (Eq. 4-5), as follows. . lxt 10 + lxt20 + lxf30 + lxt40 = t 10 + t2 0 + t30 + t40 The same applies to other elements. Therefore, it can be understood that Y defined by (Equation 4-8) in FIG. 9 is the same as Y defined by (Equation 3-10) in FIG. 8. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Register file and order form Next, the structure of the register file and the order formation among the necessary hardware components of the present invention will be explained. In the processor to which the present invention is applicable, a register file composed of 16 registers has at least three groups. Figure 10 shows the case of register files RFLO, RFL1, RFL2, RFL3 with 4 groups. The register numbers assigned to the left side of Fig. 10 are shown in the auxiliary files 510 to 513 of Fig. 5. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ~~ -16- Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (14) The register shown in Figure 5 and Figure 10 Correspondence between the registers of the file. Moreover, in the processor to which the present invention is applied, there are two types of commands for performing a row-column product of a 4 × 4 row and column and a vector of 4 elements. The command is set as shown below. TRV m, n, s, d (the first kind of row and column operation command) TRVT m, n, s, d (the second kind of row and column operation command) For example, the command form is as shown in Figure 11 and stored via the command code The command code field ICF is formed with four fields of which operands represented by m, s, d, η are stored: 0PF1, 0PF2, 0PF3, and 0PF4. Among these operands, m, s, and d are the numbers of the specified register file. Also, η is the number of the register in the designated register file, which is one of multiples of 4 (0, 4, 8, 12). That is, η is formed by a 4-bit code, and the sub file of FIG. 5 is designated by η lower and 2 bits. The upper 2 bits specify the register in the auxiliary file. (In the TRV command, the lower 2 bits are often set. 00). Next, the function of the first row and column operation command TRV will be described first. The function of the TRV command is defined in Figure 12 (Equation 5-1). That is, a group of 16 registers in the register file m is regarded as a 4 × 4 row 'column, and a group of registers η, n + 1., n + 2, and η + 3 in the register file s is considered.値 is regarded as a vector of 4 elements, the ranks are multiplied by the vector, and the result is stored in the register group η, n + 1, n + 2, n + 3 in the register file. That is, the calculated vector consists of 4 auxiliary files in Figure 5 and 1 in this paper. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page). 17- Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the Invention (15) One was taken out, and the calculation results were stored in four auxiliary files. Regarding the register file of FIG. 10, four consecutive register vectors are read out and the results are stored in the corresponding four registers. Therefore, when it is the following command, TRV 0 9 0, 1 > 2 Fig. 12 (Equation 5-2) operation is performed 0 and the following command line 9 RV 0 f 0, 1 9 2 TRV 0 9 4, 1 9 2 TRV 0 > 8, 1, 2 TRV 0 9 12 9 1, 2 Figure 12 (Equation 5-3) is performed > 4 X 4 rows and 4 X on the right Multiplication of 4 rows and columns 9 The result is to obtain 4 X 4 rows and columns 0 on the left. Then 5 describes the function of the second row and column operation command TR -VT. The function of the T R V T command is defined by rcrf Figure 12 (Equation 5-4). The t used in (Equation 5-4) is to form the above-mentioned operand η by a 4-bit code, and shift 2 to the right by 2 bits. 〇 The upper 2 bits of T are 0 0. The second type of rank operation command TRVT m 9 n, s 9 d is: treat 16 registers in the register file m as 4x4 ranks > treat the register group t in the register file S, 4 + t > 8 + t 9 1 2 + t is regarded as a vector of 4 elements, the ranks are multiplied by the vector, and the result is stored in the register group η, n + 1, n + 2, n + 3 in the register file. That is, the calculated vector is stored in four of one of the four sub-files in Figure 5. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the note on the back first) (Fill in this page again)

-18-A7 B7 V. Description of the Invention (16) The device of the device is taken out, and the operation results are separately stored in the registers corresponding to the four auxiliary files. Regarding the register file of FIG. 10, every 4 of the 16 registers is read as an operation vector, and the result is stored in the designated register file of the 4 consecutive registers. Register (register with a mark having a multiple of 4) ○ Therefore, when the following command is executed: 9 TRV 0 0 9 1 9 2 (Equation 5-5) in Figure 12 is performed. And when the following command line is t 9 TRV 0, 0 9 1, 2 TRV 0 9 4 »1 9 2 TRV 0» 8 9 1 2 RV RV 0 f 1 2 9 1 7 2 Figure 1 2 (Equation 5 — 3 The operation of) is performed, multiplying 4 X 4 rows and 4 X 4 rows and columns by j to obtain the result of 4 X 4 rows and columns 0. It should be noted here that (Expression 5-3) and (Expression 5-6), The rank of the right term is given by (Eq. 5-3). The point of transposition with (Eq. 5-6), that is, C Eq. 5-3), is the arrangement of the unitary group in the direction of the line of the previous term and (Eq. 5) _ Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page) 6) The arrangement of the groups in the direction of the previous item is the same, (Equation 5-3) The arrangement of the unitary groups in the direction of the rows and columns is the same as the arrangement of the unitary groups in the direction of the rows of the preceding items (Equation 5-6). This means that the two commands TR U, TRUT, are not used. Will change the register The arrangement method of the archives in the file storage, that is, the register file does not need to be loaded by the memory, can be implemented (Eq. 5 _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297)) Central standard of the Ministry of Economy A7 printed by the Bureau's Consumer Cooperatives ____B7 __ V. The description of the invention (17) 3) and the operation of (Formula 5_6). As a result, the calculation of the image data for the inverse discrete cosine transform according to (Equation 3-10) will be compared with the case where the TRU and TRUT commands are not used. The order number can be greatly reduced. In the inverse discrete cosine transform of Equation 3-10), it is necessary to load the 'stored command' from the main memory register to the one having the following command which is also used by the previous microprocessor. LD 4 b + disp, d, n ST n, b + disp Here, the command represented by LS 4 is separated by the base address b only the address of 値 specified by the displacement 値 disp (in the embodiment, it is The address of one of the main memories), load 4 copies of data into the register group η, n + 1, n + 2, n ++ 3 in the register file d. The command indicated by 'ST is to separate the register η in the register file s from the base address b to only the address specified by the displacement 値 disp (in the embodiment, one of the bits in the main memory) Address) to store the order. Command execution sequence Next, the sequence of the case where the control unit 990 of FIG. 3 executes the first type of row and column operation command TRVm, n, s, and d will be described. In the first step, the control unit 9 0 9 uses the signal line 9 3 0 as a 2-bit binary code, and first sends “0 0” to the auxiliary files 5 1 0 to 5 1 3 of each register file 500 to 503. In response to this, the auxiliary files 5 1 0 to 5 13 respectively send the contents of register 0 to the selection component. The paper size is applicable to the Chinese National Standard (CNS) A4 specification · (210X297 mm) ---------- ^-(Please read the notes on the back before filling out this page) Order-20- Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ____B7_ V. Description of the invention (18) 5 5 0. Send the contents of register 1 to Selection element 5 5 1. Send the content of register 2 to selection element 5 5 2. Send the content of register 3 to selection element 553. Furthermore, the 'control section 990 sends the number m of the designated register file to the signal 9 3 4. In this way, the data specified by m is latched to the latch 920 '921' 922, 923 through the selection elements 550 to 553 '(i.e., the contents of register 0' 1 '2, 3 of the register file m are latched to the latch 920' 921 '922' 923) 0 heart-In addition, the control unit 9 9 0 sends the upper 2 bits of the register number η to the register number η through the signal line 9 3 1 to each register file. In response to this, each register file sends the contents of the register corresponding to the upper 2 bits of n to the selection element 5 1 6. In addition, the control unit 990 sends the lower 2 bits of η to the selection element 5 1 6 through the signal line 9 3 3. In this way, the selected data is sent to the selection element 5 5 4 through the selection element 5 1 6. Further, the control section 9990 sends the number s of the designated register file to the signal line 935. Thus, the data designated by s is latched to the latch 9 2 4 through the selection element 5 5 4. At the same time, the control unit 9 9 0 controls the selection element 9 6 3 through the signal line 9 3 5 which is set to the temporary register 9 6 2 in the initial stage “0”. In the second step, the contents of the latches 920, 921, 922, and 9 2 3 are sent to the corresponding summators 9 1 0, 9 1 1, 912, 913, and the contents of the latch 92 4 are sent. Add the sum of 4 to 910 * 911, 912, 913. And the initial product sum of each product summator 9 1 0 ~ 9 1 3 is being carried out, and the result is applied to Chinese paper standard (CNS) A4 standard (210XW7 mm) by this paper standard --- 1- ------ "" 4-- (Please read the precautions on the back before filling this page) Order-21-A7 ___ B7_ V. Description of the invention 19 Set in temporary register 9 6 2 etc." At the same time Through the signal line 9 30 binary code "〇1" is sent to each register file 5 0 ~ 5 0 3. In response to this, each register file sends the contents of register 4 to selection element 5 50, the contents of register 5 to selection element $ 5 1, and the contents of register 6 to selection element 5 5 2. Register 7 The content is sent to the selection element 5 5 3. Furthermore, the control unit 9 9 0 sends the number m of the designated register file to the signal line 9 3 4 »In this way, the data designated by m passes through the selection elements 5 5 0 to 5 5 3 and is latched to the latches 920, 92 1 , 922, 923. In addition, the control unit 9 9 0 sends a 4-bit register number η increment (+1) of 値 η + 1 to the upper 2 bits to each register file 500 to 5 0 3 through the signal line 9 3 1 Printed by the Central Standards Bureau Shellfish Consumer Cooperative (please read the precautions on the back before filling this page) In response to this, each register file sends the contents of the 2-bit register corresponding to the upper η + 1 to the selection element 5 1 6. Furthermore, the control unit 9 9 0 sends the lower two bits of η + 1 to the selection element 5 1 6 through the signal line '9 3 3. Thus, the selected data is sent to the selection element 5 through the selection element 5 1 6 5 4 »Furthermore, the control unit 9 9 0 sends the number s of the designated register file to the signal line 9 3 4. The data designated in this way is latched to the latch 9 2 4 by the selection element 5 5 4. The operation of the third step is the same as the operation of the second step. The difference is that the register number 4, 5, 6, 7 becomes 8, 9, 9, 0: L 1, and a 4-digit register number. η + 1 becomes η + 2. The operation of the fourth step is the same as the operation of the second step. The difference is that the register number 4,5 '6,7 becomes 12,13'. This paper standard is in accordance with China National Standards (CNS) Α4 specification ( 2 丨 0 × 297 mm) -22- A7 _B7 _ V. Description of the invention (2D) 14 '15' and 4 digit register number π + 1 becomes π + 3 ° The fifth step is to be latched on the product sum Steps for writing 4 of the registers 9 1 0, 9 1 1 '9 1 2, 91 3 back to the register section 9 01. The latched on the product 9 1 0 is sent to the sender 9 0 1 through the signal line 9 2 0 and so on. The control unit 9 0 0 sends the upper 2 bits of the 4-bit register number η to each auxiliary file through the signal line 9 3 2. Furthermore, the writing of the register file corresponding to the operand "d" is permitted through the signal line 9 3 6. In this way, four of the four files are set to the four sub-files of the register file designated by "(1". In the above operation, the operation defined by (Equation 5-1) is performed. Next, regarding Fig. 3 The control unit 9 9 0 implements the following second kind of rank calculation commands TRVTm, n, s, and d. It is explained in the case of the printing and packaging of the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) ) In the first step, the control unit 9990 sends the binary code "〇〇" to each register file through the signal line 930. In response to this, each register file sends the contents of each register 0 to Selecting element 5 5 0, sending the content of register 1 to selecting element 5 5 1. Sending the content of register 2 to selecting element 5 5 2. Sending the content of register 3 to selecting element 5 5 3. And the control unit 9 9 0 sends the number m of the specified register file to the signal line 9 3 4 »In this way, the data specified by m passes through the selection elements 550 to 553 and is latched to the latches 920, 921, 922, and 923. The control unit 990 passes Signal line 931 lowers the 4-bit register number η by 2 Yuan to each register file (in the TRV command, pay attention to the upper 2 bits). In response, each register file sends the contents of the register corresponding to the lower 2 bits to η to the selection component CNS) Α4 specification (210 × 297 mm) -23- Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (21) 5 1 6 0 Furthermore, the control unit 9 9 0 places the register number η above The 2 bits are sent to the selection element 5 1 6 through the signal line 9 3 3. In this way, the selected data is sent to the selection element 5 5 4 through the selection element 5 1 6 »and the control unit 9 9 0 will specify the number of the register file s is sent to the signal line 9 3 5. 〆 In this way, the data designated by s is latched to the latch 924 by the selection element 5 5 4. At the same time, the control unit 990 sets the initial value "0" to the temporary register 9 6 2 Ground. Control the selection element 9 6 3 through the signal line 9 3 5. In the second step, the contents of the latches 920, 921, 922, and 923 are sent to each of the summators 910, 91 1, 912, 9 1 3. The contents of the latch 9 2 4 are sent to the 4 summators 910, 91 1, 912 , 913. Furthermore, the first product sum is performed in each product summator, and the result is set in the temporary register 9 62, etc. At the same time, the binary code "0 Γ" is sent to each register through the signal line 9 3 0 '. In response to this, each register file sends the contents of register 4 to selection element 5 50 0, the contents of register 5 to selection element 5 5 1, and the contents of register 6 to selection element 5 5 2. The content of the register 7 is sent to the selection element 553 », and the control unit 990 sends the number m of the designated register file to the signal line 9 3 4. In this way, the data designated by m passes through the selection elements 5 50 to 5 53 and is latched to the latches 920, 921, 922, 923. In addition, through the signal line 9 31, the lower 2 bits of the register number n + 1 are sent to each register file. In response to this, individual register files will correspond to the register number η + this paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) Order

• Quan · II -24- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 11 A7 B7 V. Description of the invention (22) The contents of the lower 2 bits of the register are sent to the selection element 5 16. Furthermore, the upper 2 bits of the register number n + 1 are sent to the selection element 5 1 6 through the signal line 9 3 3. Further, the selected data is sent to the selection element 554 through the selection element 516. Then, the control unit 990 sends the number s of the designated sound memory file to the signal line 9 3 5. In this way, the data designated by s is latched to the latch 9 2 4 through the selection element 5 5 4. The operation of the third step is the same as the operation of the second step, but the register number is 4, 5 ,. 6 ′ 7 is different in that the register number n + 1 of 8, 9, 10, 11, and 4 bits becomes η + 2. The operation of the fourth step is the same as the operation of the second step, but the register number 4,5 '6,7 becomes 12,1 3,14,1 5 and the 4-bit register number η + 1 becomes η + 3 is different. The fifth step is a step of writing back to the register section 901 the four of the latches 910, 911, 912, 913. Those latched in the product 9 10 and the like are sent to the register portion 9 1 through a signal line 9 '2 0 and the like. The control unit 9 9 0 sends the upper 2 digits of the register number η to each auxiliary file through a signal line 9 3 2. Furthermore, the writing of the register file corresponding to the number d is permitted through the signal line 9 3 6. In this way, four of the four's are set in the four sub-files of the register file of number d. In the above operation, the operation defined by (Equation 5-4) is performed. Data necessary for inverse discrete cosine transform Next, the data necessary for inverse discrete cosine transform are organized. These data are seen by the conversion program. The configuration shown in Figure 13 is stored on the outside. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out (This page)

-25- A7 B7 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 5. In the main memory Μ E Μ of the invention description (23). First of all, it is necessary to change the data of the object (DCT coefficient). This is stored in the memory fields shown in Fig. 13 in the X1T, X2T, X3T, and X4T. The necessary constants (equivalent to the base of DCT) are related to (Equation 1-2), (Equation 1-3), and (Equation 4_6). These are stored in AT, CT, and Β in Fig. 13 respectively. Shown the field of memory. Moreover, the transformation result is stored in the memory area shown by Υ in Fig. 13. Inverse discrete cosine transform The inverse discrete cosine transform can be performed in the order of (Equation 3-6), (Equation 3-7), (Equation 3-9), and (Equation 3-10) in order. When executing (Equation 3-6), load XI T of FIG. 13 into register file 0 with 4 LD4 commands, load AT of FIG. 13 into register file 1 with 4 LD4 commands, and 4 with LD4 command. The T " RVT command will obtain the result corresponding to AX1 t in (Equation 3-6) in register file 2. The 4 TRV commands will obtain the result corresponding to the right of (Equation 3-6) in register file 2. Finally, 16 ST commands can be stored in T in FIG. 13. This can be implemented in the following command series: LD 4 X 1 Τ + 0, 0, 0 LD 4 X 1 Τ + 4, 0, 4 LD 4 X 1 D + 8, 0, 8 LD 4 X 1 Τ + 12, 0, LD 4 (0) AT, 1,0 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) ^ -'β Γ -26 -V. Description of the invention (24) A7 B7 Printed by the Consumer Cooperatives of the Central Ladder Bureau of the Ministry of Economic Affairs LD 4 (4) AT, 1, LD 4 (8) AT i 1 9 LD 4 (1 2) AT y 1 TRVT 0 > 0 > 1 2 TRVT 0 9 4 y 1 > 2 TRVT 0 9 8 y 1 ί 2 TRVT 0 > 1 2 9 1 > TRV 1 9 0 j 2 9 2 TRV 1 4 9 2 y 2 TRV 1 8 »2 y 2 TRV 1 > 1 2 > 2 > ST 2 9 0 T + 0 ST 2 1 9 T + 4 ST 2, 1 5 + 6 0 X 2 T load register file 0 > AX 1 in (Equation 3-6) with 4 TRV commands will match register file 2 to get the most T in Fig. 1 3 and 0 and (Formula series Carry out Therefore, the omission of the command means that the loading of the AT is omitted. 0 Implementation (Eq. 3-8) (2 2 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 8, 12 4 LD4 orders will Figure 13 shows the result of t corresponding to t in register file 2. After obtaining the result on the right side of (Equation 3-6), store the result of 16 ST commands in 3-6). A series of specific examples. Here, you should note •. Formula 3 — 9) Specific instructions for the province -27- (Please read the precautions on the back before filling this page)

-, Printed by tT Lu printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of Invention (25) omitted. However, it should be pointed out that when calculating first (Equation 3-9), the number of loading times of AT or C T can be reduced, which becomes an efficient point. When executing (Equation 3-10), first load the register B of Figure 13 with the 4 LD4 commands. Next, with four LD4 lives, load four rows of data into register file 1 from T in Figure 13 and execute one of the four operations on the right side of the four TRV commands (Equation 3 — 1 0). The result is stored in Y of FIG. 13 with 16 ST commands. After that, it will be the same; repeat this time. The first 1/4 of the command series became as follows. LD4 B + 0, 0, 0 LD4 B + 4, 0, 4 LD4 B + 8, 0, 8 LD4 B + 1 2, 0, 12 LD 4 T + 〇, 〇, 0 LD 4 T + 4, 0, 4 LD 4 T + 8,0, 8 LD4 T + 1 2, 0, 12 TRV 0,0,1,1 TRV 0,4,1,1 TRV 0,8,1,1 TRV 0,12,1, 1 ST 1, 0, Y + 0 ST 1, 0, Y + 4 ST 1, 2, Y + 3 2 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the note on the back first (Fill in this page again)

-28-A7 B7 Printing by the Central Laboratories of the Ministry of Economic Affairs, Masonry Consumer Cooperatives V. Description of Invention (26) 1 ST 1 3 y Y + 3 6 1 1 ST 1 9 4 > Y + 1 1 i • · · «· · Please 1 I first 1 ST 1 y 1 5 9 Y + 3 9 Read the ik back 1 m and the remaining 3/4 command series omitted 0 Note 1 1 Matter 1 1 I The effect of the invention fill in 1 1Γ * Ν 1 Although the above can be the inverse discrete cosine transform, but from the implementation of (Formula 3-6) page n I to (Formula 3-9) is 1 1 2 The command (Formula 3-1 0) 1 I is implemented as 1 0 0 Command \ Total is about 2 0 0 Command 0 1 1 0 0 0 2 0 0 is required in the inverse discrete cosine transform according to the first 1 I method. Commander 1 > Through the application of the present invention, it becomes a 2 0 0 command. Completed the reason to order 1 solution to the inverse discrete cosine transform can Amplitude efficiency 〇1 1 The reason that the number of commands can be greatly reduced is to prepare the TRVTRVT command for the 1st row and column product 1 and to efficiently implement the point that is controlled by the arithmetic circuit of the Λ 1 1 coprocessor. 0 The function of the transposed rank of the TRVT 1 command is also worth noting 100. To perform a simple calculation (Eq. 3 1 1 1), it is necessary to make a transposed rank '1 1 after calculating the formula MX in the brackets. But TRVT The command provides the function of simultaneously processing the production of transposed ranks 1 and the processing of rank and rank products. This will improve the performance even more 1 1 improve 0, and then A t loaded into the register file uses the TRVT command. Order 1 1 and use 2 times It is necessary to pay attention to the point. 0 1 1 In the above embodiment, it is not directly calculated. (Equation 3 — 1) > 1 1 Although (Equation 3-6) (Equation 3-7) > (Equation 3-9) ) (Formula I 1 sheet Paper standard quasi-standards are printed in appropriate cents 7 29 29 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (27) 3-8), (Formula 3-10) are calculated in the order, but It can also be calculated in other orders. In the above description, although the inverse discrete cosine transform is mainly described as an example, the present invention can also be applied to the discrete cosine transform. Figure 14 shows the definition of f-discrete cosine transform and its decomposition into partial ranks. The results will be calculated in sequence from (Equation 6-6) to (Equation 6-10). At this time, the TRV and TRVT commands described in the above embodiments are effective and can be used effectively, which can greatly reduce the number of executed commands. In addition, in the above embodiment, four registers are set and explained, but regarding the present invention, The TRU command and the TRUT command can be used in a coprocessor with a register portion formed of at least three register files 50 0, 50 0 1, 50 2 as shown in FIG. 15 and the arithmetic circuit shown in FIG. 3. Implemented. Furthermore, although the above-mentioned embodiment is described based on the discrete cosine transform and inverse discrete cosine transform of the coprocessor, in the coprocessor of the arithmetic circuit having the structure shown in FIG. You can make floating-point operations. In addition, the microprocessor of the embodiment will be described with reference to the case where the central processing unit (the first processor) 1 is provided with a coprocessor (the second processor) 2 that performs individual row and column operations and floating decimal point operations. However, it can also be a configuration in which the functions of these two processors are realized by one processor. Possibility of industrial utilization In the above description, the inventions made by the inventors are mainly based on the Chinese paper standard (CNS) A4 specification (210X297 public directors) (please read the precautions on the back before filling in) (This page)

T 30 A7 B7 printed by the Consumers 'Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs' Explanation (28) is described as applicable to general-purpose microprocessors, but this invention is not limited to this and can be widely used for image data The compression / extension processor generally performs other data processing devices. Brief Description of the Drawings Fig. 1 is a block diagram showing one embodiment of a suitable microprocessor to which the present invention is applicable. 'Fig. 2 is a block diagram showing a specific embodiment of a central processing unit (CPU) constituting a microprocessor. Fig. 3 is a diagram showing an embodiment of an arithmetic circuit constituting a suitable coprocessor that efficiently executes the TRV command and the TRVT command. Fig. 4 is a diagram showing an embodiment of a product summator in the arithmetic circuit of the coprocessor. Fig. 5 is a diagram showing an example of a register section of a coprocessor. Fig. 6 is a diagram showing the rank and inverse decomposition of the inverse discrete cosine transform. Fig. 7 is a diagram showing the ranks of the inverse discrete cosine transform and their partial ranks. Fig. 8 is a diagram showing the definition of a two-dimensional inverse discrete cosine transform and its decomposition into partial ranks and unfolding definitions. FIG. 9 is a diagram for calculating the order of (Expression 3-10) in FIG. Fig. 10 is a diagram showing a concept of a register file. Figure 1 1 shows the form of the TRV command and TRVT command. The paper size applies the Chinese National Standard (CNS) A4 specification (210X2.97 mm) (Please read the precautions on the back before filling this page)

-31-A7 _ _B7 _______ One 5. Description of the invention (29) Figure. Fig. 12 is a diagram showing the calculation formulas used for the command functions of the TRV command and the TRVT command. FIG. 13 is a layout diagram as seen from a conversion program of data stored in the memory of an inverse discrete cosine transform. Figure 14 shows the definition of the 2D discrete cosine transform and its decomposition into partial ranks and unfolding definitions. Fig. 15 is a diagram showing another example of the configuration of the register section of the coprocessor that can execute the TRV command and the TRVT command. Comparison table of main components 1 Central processing unit 2 Co-processor 3 Interrupt control 4 Memory management unit: 5 Address conversion circuit 6 Command / data mixed in cache memory Printed by the Central Standards Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives 7 Cache memory Body controller 8 a 32-bit logical address bus 8b 32-bit physical address bus 8 c Peripheral address bus 9a, 9b 32-bit data bus 9c 16-bit peripheral data bus 10 External bus Interface This paper size is in accordance with Chinese National Standard (CNS) A4 specifications. (210X1297 mm) -32-A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (3〇) 1 1 Serial communication interface 1 2 Real-time clock pulse 1 3 Timer 1 4 Bus status controller 1 5 Clock pulse generating circuit 1 6 Watch timer 1 7 I / 0 Fill 1 8 User interrupt selector 1 0 0 Semiconductor chip 9 0 1 Register section 9 1 0 9 1 3 Multiplier 9 2 0 9 2 4 Latch circuit 9 6 0 Multiplier 9 6 1 Adder 9 6 2 Temporary Register (Please read the notes on the back before filling this page)

This paper size applies to China National Standard (CNS) A4 (210X2.97 mm) • 33 ·

Claims (1)

A8 B8 C8 D8 、 Appendix 1 of patent application scope No. 86 1 1 6630 Chinese patent application scope amendment The Republic of China 8 March 1988 Correction code and register file Register file 2 If applying for the Central Standards Bureau of the Ministry of Economic Affairs J In the printing of industrial and consumer cooperatives, it is provided with: the line of input vector in the file of NX register in the file / 3 of the operand designation 3. If the application intermediary is formed by the register selected by the specified vector. 4. If the application is to be rented, in which the above-mentioned fourth operation is performed on the row director number? The patent register for material processing is patented with the above ranks and the above column product. The third patent is used in the above device. The first register is the first register. The first register is the result register. The second entry of the fourth entry vector has the characteristics 2 and 4 of the operands. The operand and output specified by the second operand are specified by the operand and output. The operands and outputs are as follows: The vector of the register specified by the first operand specified by the data processing is stored in the command. The register vector in the data place has the rank operation instructions described in item 2 or 3 of the non-patent scope. Including: via the specified input number The first row operation command selected by the register number η in the row, and the first designated command number and designated command in the row direction of the register group passing through. The number of the second element of the register of the device is the same as that of the 0th device, and the number η is the same. The command data is processed into the register group for the vector. This paper size applies _Guo Gu Jia Standard (CNS) A4 specification (210X297 mm) A8 B8 C8 D8, patent application scope Annex 1 No. 86 1 1 6630 Chinese patent application scope amendment March 1988 Correction code and register file 2 in the register file. If the application is printed by the Central Standards Bureau of the Ministry of Economic Affairs, J. Industry Cooperative Cooperative, it is provided with: Perform the line of the input vector in the file NX X Ν register file / 3 operand designation 3. If the application intermediary is formed by the register selected by the specified vector. 4. If the application is to be rented, in which the above-mentioned fourth operation is performed on the row director number? The patent register for material processing is patented with the above ranks and the above column product. The third patent is used in the above device. The first register is the first register. The first register is the result register. The second entry of the fourth entry vector has the characteristics 2 and 4 of the operands. The operand and output specified by the second operand are specified by the operand and output. The operands and outputs are as follows: The vector of the register specified by the first operand specified by the data processing is stored in the command. The register vector in the data place has the rank operation instructions described in item 2 or 3 of the non-patent scope. Including: via the specified input number The first row operation command selected by the register number η in the row, and the first designated command number and designated command in the row direction of the register group passing through. The number of the second element of the register of the device is the same as that of the 0th device, and the number η is the same. The command data is processed into the register group for vectors. Please read the precautions for this book. This paper size applies _Guo Gu Jia Standard (CNS) Α4 specification (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A8 Βδ C8 D8 6. Application for a patent garden 5. A kind of data processing device, characterized by Use at least one of the inverse discrete cosine transforms using the command as described in any of claims 1, 2, 3, or 4. 6. A kind of data processing device ^ 'It is characterized by having a control device that forms a control signal corresponding to the command to be read in, a register file that can implement at least three registers that are formed from a predetermined number of registers, and an operation system. The Λ calculator is an operation-device that executes the individual processing of the plural command of the row and row operation command via the control signal from the control device described above. The above row and row calculation command passes the specified command code and the first and the first for register files. The second and third operands are configured with the fourth operand for the register in the specified register file. 7. The data processing device as described in item 6 of the scope of patent application, wherein the data processing device includes: performing the N × N sequence in the first register file designated by the first operand and the second operand designation In the second register file, the row-by-line product of the input vector of the element number N of the register specified by the fourth operand, and the output vector of the result is stored in the command of the third register file specified by the third operand. form. 8. The data processing device as described in item 7 of the scope of the patent application, wherein the register group selected through the register number η in the above-mentioned fourth operand used by the specified vector has different input and output vectors. Formed by order. 9. The data processing m set described in the 7th item to the 8th item of the scope of the patent application, wherein the above-mentioned row and column operation command includes: a register number n selected through the register 4 in the above-mentioned fourth operand used to specify the input vector The paper size of the register group applies to the Chinese National Standard (CNS) 8-4 specification (210X297 mm) -2- --------- loading-(Please read the precautions on the back first ^ k this page) Order — Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China. A8, B8, C8, D8. ☆. The first rank calculation command for patent application in the direction of the ranks. The second row and column operation command of the direction. 10. The data processing device according to item 7, 8 or 9 of the scope of the patent application, wherein the above-mentioned computing device is provided with 16 from each of them. Register at least 3 register slots formed by the device, and obtain the data of the 4 selected registers in the first register file specified by the first operand and the second register file specified by the second operand The multiplier of the product of the data specified in the register specified by the fourth operand above, and the four adders that obtain the sum of the operation results of these multipliers and the previous addition result, and the operations that hold these adders The result is 4 temporary registers. 1 1. A data processing language, which is characterized by having a control device 'for forming a control signal corresponding to a command to be read in, and a register and an arithmetic unit, and the control signal' through the control device 'can be implemented separately. The first processor section of the command execution signal corresponding to the processing of the above command, and a control device having a control signal for forming a corresponding command to be read, and at least three register files and operations including a predetermined number of registers The second processor unit of the computing device that can execute each of the plurality of commands that executes a plurality of commands for performing a matrix operation of a matrix by a control signal via the control device described above is provided. Both of the first and second processor sections are configured to be implemented through the second processor. 1 2. — A control signal is formed in the reading command of the control device. 'This (please read the note on the back first), this paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm)- 3- A8 B8 _ ^ __ VI. The data processing method for applying patent range control signals to the implementation device to implement the processing of corresponding commands, which is characterized by: No. 1, Table 2 and No. 1 through designated command codes and register files The 3 operand 'and the 4th operand for the register in the designated register file are prepared, and two kinds of NXN ranks in the register file designated by the 1st operand specified above are prepared to occupy the 2nd The row-by-product of the input vector of the element number N of the register specified by the fourth operand in the second register file specified by the operand is to store the result-output vector in the third designated by the third operand. The command of the register file 'is a row and row operation command for the register group selected through the register number η in the above-mentioned fourth operand for the specified input vector. The other side's rank-and-row operation command is that the register group selected via the above-mentioned register number η is in the rank-and-row direction. 1 3 · The data processing method described in item 12 of the scope of the patent application, wherein the other party's determinant operation command is a register selected through the register number η in the fourth operand used by the specified vector The group is different in the input vector and the output vector. (Please read the caution page on the back first)-Binding · Binding-Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs