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TW339465B - The method for planarization metal interdielectric layer - Google Patents

The method for planarization metal interdielectric layer

Info

Publication number
TW339465B
TW339465B TW086108547A TW86108547A TW339465B TW 339465 B TW339465 B TW 339465B TW 086108547 A TW086108547 A TW 086108547A TW 86108547 A TW86108547 A TW 86108547A TW 339465 B TW339465 B TW 339465B
Authority
TW
Taiwan
Prior art keywords
layer
insulating layer
deposit
metal
sog
Prior art date
Application number
TW086108547A
Other languages
Chinese (zh)
Inventor
Jyi-Jinn Luo
Original Assignee
Ind Tech Res Inst
Chi Mei Optoelectronics Corp
Toppoly Optoelectronics Corp
Prime View Int Corp Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst, Chi Mei Optoelectronics Corp, Toppoly Optoelectronics Corp, Prime View Int Corp Ltd filed Critical Ind Tech Res Inst
Priority to TW086108547A priority Critical patent/TW339465B/en
Application granted granted Critical
Publication of TW339465B publication Critical patent/TW339465B/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for planarization metal interdielectric layer, its steps include: a. Provide a semiconductor substrate with semiconductor devices; b. Deposit 1st insulating layer on semiconductor device, and form contact window on 1st insulating layer for electrically contact with device; c. Deposit metal barrier on 1st insulating layer and inside contact window; d. Deposit 1st conductive layer for contacting with device inside contact window; e. Define the pattern of 1st conductive and metal barrier layer, to form 1st metal line as interconnection of device; f. Deposit a 2nd insulating layer on defined 1st conductive layer; g. Spin compound layers that includes at least 4 SOG layers, and bake each layer; h. Proceed curing for SOG compound layers; I. Deposit a 3rd insulating layer on SOG compound layer, then use CMP method to polish partial thickness, for global planarization the whole surface; j. Etch through hole through 3rd insulating layer, SOG compound layer, 2nd insulating layer till 1st metal line; k. Deposit a 4th insulating layer, and use anisotropical etching to proceed etching back, and form sidewall space at sidewall of through hole; l. Deposit a 2nd conductive layer on 3rd insulating layer and inside through hole, then use CMP method to polish partial thickness, for global planarization the whole surface; m. Form next layer metal interconnection after defined pattern of 2nd conductive layer.
TW086108547A 1997-06-19 1997-06-19 The method for planarization metal interdielectric layer TW339465B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086108547A TW339465B (en) 1997-06-19 1997-06-19 The method for planarization metal interdielectric layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086108547A TW339465B (en) 1997-06-19 1997-06-19 The method for planarization metal interdielectric layer

Publications (1)

Publication Number Publication Date
TW339465B true TW339465B (en) 1998-09-01

Family

ID=58263358

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086108547A TW339465B (en) 1997-06-19 1997-06-19 The method for planarization metal interdielectric layer

Country Status (1)

Country Link
TW (1) TW339465B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906422B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
US7915734B2 (en) 2001-12-13 2011-03-29 Megica Corporation Chip structure and process for forming the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7906422B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
US7906849B2 (en) 1998-12-21 2011-03-15 Megica Corporation Chip structure and process for forming the same
US7915157B2 (en) 1998-12-21 2011-03-29 Megica Corporation Chip structure and process for forming the same
US7915734B2 (en) 2001-12-13 2011-03-29 Megica Corporation Chip structure and process for forming the same
US7919867B2 (en) 2001-12-13 2011-04-05 Megica Corporation Chip structure and process for forming the same
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US8008776B2 (en) 2001-12-13 2011-08-30 Megica Corporation Chip structure and process for forming the same
US8546947B2 (en) 2001-12-13 2013-10-01 Megica Corporation Chip structure and process for forming the same

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees