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TW313687B - - Google Patents

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Publication number
TW313687B
TW313687B TW086100651A TW86100651A TW313687B TW 313687 B TW313687 B TW 313687B TW 086100651 A TW086100651 A TW 086100651A TW 86100651 A TW86100651 A TW 86100651A TW 313687 B TW313687 B TW 313687B
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TW
Taiwan
Prior art keywords
chip
foil substrate
wafer
substrate
unit
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Application number
TW086100651A
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English (en)
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Ericsson Telefon Ab L M
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/4245—Mounting of the opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4249—Packages, e.g. shape, construction, internal or external details comprising arrays of active devices and fibres
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/422—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements
    • G02B6/4221—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements involving a visual detection of the position of the elements, e.g. by using a microscope or a camera
    • G02B6/4224—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements involving a visual detection of the position of the elements, e.g. by using a microscope or a camera using visual alignment markings, e.g. index methods
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/426—Details of housings mounting, engaging or coupling of the package to a board, a frame or a panel
    • G02B6/4261—Packages with mounting structures to be pluggable or detachable, e.g. having latches or rails
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G02B6/428—Electrical aspects containing printed circuit boards [PCB]
    • G02B6/4281—Electrical aspects containing printed circuit boards [PCB] the printed circuit boards being flexible
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Led Device Packages (AREA)

Description

五、發明説明 經濟部中央標準局員工消費合作社印製 發明範圍少裝—晶片於一單元上之方法，該晶片至 :有：及關於一裝置供安裝-晶片於-單元 上’：: 光學表面，如安裝晶片於-光小型模組4及/或密封之光電元件如檢光光射 7 = 或雷射二極體(LD)多半與電子元件統合一起 k吊女裝在小型模组上俾易於處理。 以往技藝之敘述 、當__作高速通信時’在光纖及光組件之主動表面 後經常有一水久連接如光發射機或光接收機。此項連接 需要光纖之_與光學组料位上之限定良好或域作非常 準確…。因此，組合件必需與永久安裝之光纖長度密 1在-起，即所謂豬尾巴，如此則—小而永久安裝之光纖 將水久自模組掛起。密封可用金屬或陶質材料密封。此組 件密封法非常費時，昂貴，佔用士宏積，並不能將密封之 组件與光纖連接，及自光纖釋放。 吴國專利 US-A 5,168,537, 5,199,093, 5,230,030, 5’249’245_! 5,309’537 ’ 5,337,391 及 5,420,954 等曾揭示出 已知之方法及裝置，以某種形勢之通信裝置之助以連接光 纖至光發射機，或接收機。其中，個別光纖終端以不同形 式之導引裝置之協助使其直接與光電元件之—主要表面 接。 本發明之略述 本發明擬將一具有至少一光主動表面之晶片裝置簡化， (請先閱讀背面之注意事項再填寫本頁) 裝· -a 線 I I - I - -. -4 - 本纸張尺度適用中國國家標準（CNS ) M規格（2丨OX297公褒） .I I 11 . 313687 A7 五、發明説明（ 及將晶片放置在與—朵.策^ / 伶龙、缸本工 乍模組爲正確之位置以期在光纖 與光王動表面間脾盘甚兀*成 ,A 玫仔取佳之光輪送，晶片係固定在至少有 請{ 先I 閱 卜 讀 J I 面 | 之I 注 j 意 事I 項 · 再 , 填I 寫壁 本’ 頁 一個導體的錫箔上，龙 芏〆有 T ^ , w θ α '、上尚備有校正記號及/或導引裝置 以正確放置叫片於錫箔 白上 並正確的將箔定位，及安宪晶 片於模组上。固定晶片於唸μ、议 久女裝时 ,m ^ u, 、冶上足後，箔及晶片總成可容易 地固足在模组上。利用導引租苗 道 价 引裝置，如在模組上之接觸元件
導引梢，洎及晶片可盘描；έΕΙ 士. T A 母巧J Μ杈组成正確定位，故在接觸元 之光纖之終端將在晶片之#I主 τ 因而提供了光之傳輸。 、接觸 圖説之簡略説明 圖1説明根據以往技藝之光小型模组裝置。 圖2説明本發明之一光小型模組 土伏，、孔表置，具有—晶片 i-7 引梢之小室。 、圖城明一笛基質’其上載有導體及-具有光活動表面 之下方晶片。 圖补説日月箱基質及圖3a中所示之有下方導體之晶片。 線 圖3c説明箔片及有下方導體之圖3a中之晶^。印 ° 經濟部中央標準局員工消費合作社印製 圖“說日月一光小型模组，包括本發明之：裝羯上之晶片. 及其下面之導體。 圖4b爲説明一光小型模组包括本發明之安裝落上之晶片 及其下面之導體。 ' 00 圖型模组’包括導引㈣及安裝錫错 上之晶片，該圖等顯示小型模組之頂视及側视圖。 較佳具體實例之敘述 -5- 本紙張尺度適用中國國家標率（CNS ) A4规格（2淑加公釐） 313687 A7 B7 五、發明説明（3 經濟部中央標準局員工消費合作社印裝 圖1説明一已知模組，或所謂光小型模组之製造，其 光電組件15 ’該圖已顯示—在基質上之模组裳置H 板或相似裝置。具有數條相互鄰近之—種光學多 色帶纖維備有-模組連接器，其具有導引梢子，在、乘^ 與模组連接時，此導引梢之功能爲將連接器準確地 與模组成正確之關係，、經由此導？1梢，連接器可準確= 而與模组之前側之導引洞穴丨丨匹配。參考號17指出電導體 之路徑，其自光電組件向下直伸至模组之背部。模組 ，中尚包括一線凹隙19，组件15即可安裝其中，與模 前侧其餘部分成沉下之關係。當將在光連接器上^導引= 插入模組之導引洞&時，此裝置可使在光组件之外連接表 面與光連接器之對應表面得到一控制之距離，通常爲光纖 電境之光纖之終端表面^此舉可使由於在安裝光連接器上 之壓力引起之連接表面之損害可以避免。模组之前側包括 以校正十字形式之記號21，其功能爲可使光組件放置在模 组之前側與接收導引梢之洞穴"成正確方向。 圖2説明一模组/光小型模组1〇，其根據本發明所製造 ’並具有铁收晶片之凹隙部分14及導引梢17以供光纖連接 器之用。 &圖3a-c説明一模组/小型模组電連接裝置，其包括一軟 搭基質9，由聚合物，如聚亞醯胺，金屬搭4，最好爲銅箱 在柔性II之一側或二側。銅落係印刷在電路上以供晶片i 及電路板1 1間之電連接。晶片可利用倒裝片之技術安裝在 基質9上，故晶片之活動表面7則面向羯基質。簿基質有一 -6- f請先閱讀背面之注意事碩再填寫本頁j •裝_ -許 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（4 ) 開口 5與晶片之活動表面相對。可利用黏膠3以改進倒裝片 與泊基吳疋膠合，黏膠3可爲一種透明膠。膠加上之後部 f或完全將馆之開口填滿。當可經由辖基質獲得足夠良好 可I3之輸送時，則不需開口。薄而透明的橡膠薄膜6可以 加在辖基質之後側與活動表面相對應之位置。供接收模组 10上之梢17之具有洞穴8之箔基質被置於此等梢上，而晶 片貝)容納於模組中之凹隙14内。晶#及馆基質可用膠^: 在模組上，見圖4。#連接—連接器時，料橡膠薄膜6可 防止連接器與组件間空氣隙之形成。例如，當倒裝晶片緩 衝器2有一 5 0-7 5 μ m之高度’箔基質4厚度爲1〇"瓜，聚 合體箱9(厚度爲25#m，薄膜6厚度爲2〇"m，連接器纖 維與晶片表面之距離爲100_ 13〇"m，此一距離被視爲足 夠短之距離。 有一種方式可達成晶片與軟箔上之電路板間之電連接， 其不同之處由軟箔之一側決定，而導體4即在軟箔4上。如 .導體係在晶片之同一側，如圖31?所示。當安裝在電路板η 上，並與電路板18上導件以銲接或導電膠13連接時，箔基 質被向前f，如圖4 a所示，而不在模组之下方。如導體不 在裝晶片一側之相反側，見圖3c。導體則向模组下方彎曲 ，見圖4b ,並與安裝電路板之導體以銲接或導電膠〖3連接 。在後者（情況，在箔基質之一侧之晶片與另侧之箔基質 上之導體經由洞穴1 6連接。 當晶片被放在模組上，或箔基質安裝在模組上時，晶片 之活動表面可置於模组中與導引梢之相關位置。在前者之 _ -7-_ 本紙張尺度適财麵家縣（CNS ) A4規格（210X297公釐） ~—：---- — -h― I -----ί I 裝 I---II-討 ί― ------ (請先閱讀背面之注意事項再填寫本頁) 313687 A7 —___B7_ 五、發明説明（5 ) 情況下，可使用一個能夠將晶片放置在與洞穴8相關之位 置之士I機械並有相當兩之約爲5 # m之準確度。 亦可使用一 ”目視”系统，其可稱爲晶片之外緣，或稱晶 片上攜帶之校正記號，再將此等記號或邊緣正確地置於箔 基質之洞穴上。如此洞穴之直徑與導引梢17直徑相同，晶 片將正確地被置於導引梢，而箔基質/晶片總成亦固定在 導引梢上。在後者之情況下，見圖5，凹隙i 4之二邊緣i 9 ’ 2 0與導引梢1 7已有足夠準確之關係。箔基質/晶片總成 於是與導引梢匹配，而晶體之外緣在膠合箔基質/晶片總 成前已抵住良好限定之邊緣19，20。後者之情況需要在结 基貝8中之洞穴較導引梢之直控大。不用模組凹隙中之邊 緣，在固定箔與晶片之前，先固定—限定形狀之金屬箔或 塑膠箔。此箔亦可能有邊緣，此邊緣與該洞穴限定良好， 與上述之模组凹隙之邊緣相似，提供了限定良好之箔基質 /晶片總成之定位。 ---^---i— —1 ^ I 裝------1ί—----W 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 -8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）

Claims (1)

  1. 申請專利範圍 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 :種”具有至少一光活動表面於一單元上之晶片之方 固定：：裝一晶片於—光小型模组上，其特徵爲將曰“ 上，即膠合於基質上，該基質至少有一導 之’、/、曰9片成電接觸，並與面向或背向箔基質之晶片 /動表面接觸；提供、m校正記號及/或導引装 片细士確地將洎基質放置在單元上；及固定箔基質/晶 片總成於單元上。 範圍第α之方法，其特徵爲提供洞穴於 貝上’其與單疋上之導引梢或單元上安裝之接觸袭 匹配以將箔基質正確地置於單元上。 =據申叫專利範圍第丨項之方法，其特徵爲提供箔基質 開口，孩開口在晶片已固定在箔基質上時其位於晶 片之活動表面之反面。 種知晶片疋位之裝置，該晶片至少有一光活動表面 命 _ Wg _ ”早凡成正確之關係，如安裝一晶片於一光小型模组 上，其特徵爲晶片（1)固定在箔基質（9)上，其上至少含 個導to ( 4 ) ’在箔基質上備有校正記號及/或導引裝 料-(8 )以-正確地將晶片定位於箔基質上，並正確地將箔基 質固定於該單元上。 根據申请專利範圍第4項之裝置，其特徵爲該箔基質包 括洞穴（8)與單元或安裝在接觸裝置之導引梢（17)匹配。 ‘根據申凊專利範圍第4項之裝置，其特徵爲箔基質包括 —開口（5)，該開口在已將晶片固定在箔基質上時，其位 於晶片之活動表面（7)之反面。 2 9 本氏張尺度適用巾_國家襟準（CNS ) ( 21GX297公瘦） (请先聞面，νι注意事項再本) 裝— fflf — fnvf _ ¾ 線 3ίθ687
    申請專利範圍 7_根據申請專利範圍第4項之裝置，其特徵爲單元 限又良好之凹隙（14)，纟安裝晶片於單元上_限定t〜 (1)之位置。 日g片 8.—種光小型模組，包括一具有至少一光活動表面之晶片 ，其特徵爲晶片（1 )安裝在具有一導體（4 )之箔基質（9 ); 名$基質/晶片總成係安裝在模組（1 〇)上、；及在箔基質 上之導體與晶片連接，或能與在電路板（11)上之一導體 連接。 In· ml _ n^i n (請先閱讀背面之注意事項再填寫本頁) ΤΓ 線 經濟部中央榡準局員工消費合作社印製 -10- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
TW086100651A 1995-11-29 1997-01-22 TW313687B (zh)

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AU7716496A (en) 1997-06-19
CN1100345C (zh) 2003-01-29
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WO1997020344A1 (en) 1997-06-05
US6242274B1 (en) 2001-06-05
KR19990067640A (ko) 1999-08-25
KR100426039B1 (ko) 2004-06-18
EP0864173A1 (en) 1998-09-16
JP3856475B2 (ja) 2006-12-13
SE508763C2 (sv) 1998-11-02
SE9504271D0 (sv) 1995-11-29
SE9504271L (sv) 1997-05-30
CA2238754C (en) 2008-01-15
CN1203698A (zh) 1998-12-30

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