^ C 5 ό41 A7 ____ B7 ~· - ——— … ~ _ - — - — 五、發明説明（1) 發明範圍 本發明通常相關於一極性偵測器。本發明特別有用，但 非必須限制於偵測電腦監視器中連續的同步脈波之極性。 發明背景 電腦監視器中垂直及水平同步脈波決定出時序，其可確 定在監視器上的顯示可正確的重生。要做到這樣，電腦監 視器中的電路必須偵測出垂直及水平同步脈波的極性。 一偵測同步脈波極性的傳統類比方法是使用電阻-電容 (R/C)積分電路其在一預先決定的時間期間内平均同步脈波 。同步脈波的極性便由平均的大小來決定。然而，因爲需 要相當大數値的電阻與電容，將電阻與電容配置在半導體 晶片上是有困難的。因此，這限制了將這類的極性偵測器 整合到一數位電腦監視器控制晶片的能力。一偵測同步脈 波極性的傳統數位方法是用計數器與比較器。然而，雖然 這類數位極性偵測器可以整合到一數位電腦監視器控制晶 片’相當大數量的元件造成電流消耗的增加，晶片體積與 動作的速度，可能無法滿足控制晶片的某些應用。 發明概要 經濟部中夬標準局員工消費合作杜印製 --II ·- I'----- ------訂 * (請先閲讀背面之注意事項再填寫本頁) 本發明之一目的是克服或減輕至少一種先前技藝之極性 偵測器的問題。 根據本發明之一觀點提供有—極性偵測器包含：—儲存 裝置選擇性的取樣及儲存連續的最少兩脈波；及一連接到 像存裝S輸出的數位比較器裝置以比較取樣來提供一輸出 信號’其中，被使用來，輸出信號的改變乃根據它的極性 -4- 本紙張尺度中關家標準（CNS ) A4規格（21Qx 2974董） A7 ----_______ _ B7 五、發明説^ ( 2) ~~~~~ --— ，則取樣便會有相同的極性，而其中當取樣的極性不 的話’則輸出信號維持不變。 最好，#存裝置可以有時鐘輸入來達成儲存。 適當的，儲存裝置可以包含兩個雙穩態。 數位比較器可以包含-輸出信號的儲;裝置來儲存輸出 信號。此輸出信號儲存裝置可以連接到儲存裝置的時鐘輸 入，藉接收時鐘信號達成輸出信號的餘存。 最好’數位比較器包含一遲輯電路連接來接收一儲存的 輸出信號隨之與取樣比較。 根據本發明之另-觀點，提供有—方法來㈣連績脈波 的極性，這方法的步驟包含： 汪）選擇性的取樣並儲存脈波的取樣；及 b)比較此取樣來提供一指示出取樣是否極性相同的輸出 信號。 最好，選擇性的取樣及儲存的步驟⑻可以由時鐘信號達 成。 適當的，比較的步驟(b)還包含在最少一個時鐘信號週期 之輸出信號的儲存步驟。 最妤，比較步驟(b)還包含取樣與輸出信號的比較步驟。 圖式的簡要說明 圖1説明一根據本發明之較佳具體實例的極性偵測器。 圖2到圖8説明根據本發明之較佳具體實例之圖1中極性 偵測器的時序波形a 圖9説明根據本發明之較佳具體實例之圖1中極性偵測器 -5- 本紙張尺度適用中國國家襟準（CNS ) Α4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁} 裝· -丁 -、τ 經濟部中央標準局員工消費合作社印装 ¾濟都中夬檩率局員X消費合作'社印製 Λ7 ---------- Β7 _ 五、發明説明（3) 動作的詳細流程圖。 發明的詳細説明 在接下來的説明中，參考到一脈波或取樣的邏輯〇及運 輯狀態有一負極性，參考到一脈波或取樣的遲輯1及運輯i 狀態有一正極性。 圖1説明一極性偵測器10〇，其包含一儲存裝置1〇2及數 位比較器103。儲存裝置1〇2包含雙穩態ι〇5及1〇7，而數位 比較器103包含一邏輯電路1〇8及雙穩態1〇9。雙穩態ι〇5連 接到一時鐘信號產生器Π4及一連續的脈波120 »雙穩態 105的輸出連接到雙穩態1〇7及邏輯電路1〇8的互斥〇R閘ι31 的一個輸入《雙穩態107連接以接收時鐘信號產生器1M。 雙穩態107的一輸出連接到互斥OR閘131的另一輸入及一 AND閘132的一輸入。互斥OR閘的一輸出連接到閘U2 的輸入，其爲一反相輸入，及一 AND閘133的一輸入。and 閘132與133的輸出同時接到一 OR閘134的輸入，其一輸出 連接到雙穩態109。雙穩態1〇9的一輸出連接到AND閘133的 另一個輸入。時鐘信號產生器提供一時鐘信號115到雙穩 態105 ’ 107及1〇9的時鐘信號輸入。在極性偵測器1〇〇中加 以辨認的不同信號包含；雙穩態1〇5的輸出信號121 ;雙穩 態107的輸出信號122 ;互斥OR閘131的輸出信號123 ; 〇R 閘134的輸出信號124 ;及雙穩態109的輸出信號125。 時鐘信號115輸入到雙穩態105及107以達成取樣，並儲存 取樣，連續的脈波120。取樣被雙穩態1〇5及1〇7儲存，並 經由輸出信號121及122提供到邏輯電路108。邏輯電路108 -6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局負工消費合作社印製 A7 _B7五、發明説明（4) 包含一互斥OR閘131連接來接收雙穩態1〇5的輸出信號121 及連接來接收雙穩態107的輸出信號122，並提供輸出信號 123。互斥OR閘131比較由雙穩態150及107所儲存的取樣， 提供的輸出信號123在儲存取樣極性不同時有一遲輯1，提 供的輸出信號123在错存取樣的極性相同時有一邏輯〇。輸 出信號123提供到一對的AND閘132及133，它們的輸出傳送 到OR閘134並提供輸出信號124到雙穩態109的輸入。當取 樣的極性不同時AND閘133被致能，而當取樣的極性相同 時AND閘134被致能。當一個邏輯1送到有兩個輸入的 閘的兩個輸入中的一個時，這個AND閘是被致能的。這意 味著此被致能的AND閘產生一輸出，其有著與提供到此 AND閘之另一輸入的相同遲輯，也就是閘的另—輸入 上的邏輯通過閘到達AND閘的輸出。雙穩態1〇9接收時鐘 信號115及輸出信號124，並對應的產生一輸出信號125。 雙穩態109儲存此輸出信號125最少此時鐘信號115的一個 時鐘週期的期間以上。AND閘133也連接來接收輸出信號 125，而當取樣的極性不同且時鐘信號115的—時鐘脈波發 生時’輸出信號125或遲輯1或邏輯〇通過此閘133， OR閘134 ’並接著經輸出信號124，到達雙穩態1〇9。這使 得輸出信號125維持在其原來的邏輯狀態，在時鐘脈波發 生之則，也就是輸出信號維持不變。另外，閘連 接來接收輸出信號Π2及輸出信號123。此AND閘132反相輸 出信號123，如此’當所儲存的取樣極性相同的話則and 閘132被反相的輸出信號123所致能。因此，當所儲存的取 -7- 本B尺度賴中關家縣（CNS ) A4規格（-21Qx297^厂---- i..裝 訂 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 樣相同且時鐘信號115的一時鐘脈波發生時，此輸出信號 122指示出所儲存取樣的極性，或邏輯1或邏輯〇，連接經 由AND閉132 ’ OR閘134 ’並經由輸出信號124到達雙穩態 109。這使得輸出信號ι25有儲存取樣的極性。雙穩態ι〇5 ’ 107及109是邊緣觸發的j)型正反器，然而，任何功能上 類似型的雙穩態，例如已知的在本技藝中均可使用。邏輯 電路108可以包含其他與所敘述的不同的邏輯閘，然而， 可以理解的’不同組合的邏輯閘可用來實現與邏輯電路 108相同的邏輯功能。 0 1 η Q2n Fn+1 0 0 0 0 1 Fn 1 0 Fn 1 1 1 表1 上面的表1説明由極性偵測器100完成的邏輯功能，其中 Q1及Q2分別是雙穩態105及1〇7的輸出，表示取樣的極性， 而F是輸出信號丨25。標記„與n+1指示出時鐘脈波順序。例 如看表1的第一列，當時鐘脈波η發生時，Qi和φ是—邏 輯〇 ’指示取樣的極性是負的。所以，輸出信號F是邏輯〇 ’指示當一接下來的時鐘脈波11+1發生時，連續脈波的極 性是負的。從表1的第二與第三列，當輸入Q1與Q2不相同 ’當一個是邏輯〇而另一個是邏輯1，輸出信號F不變。這 指示出連續脈波極性的不一致改變已被偵測出來的而所以 -8- 本紙張尺度適用中國國家標隼（CNS ) A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 A 7 B7 五、發明説明（6 ) ’輸出信號F維持不變。從第四列，當qi和Q2是逯輯1， 則輸出信號是1。從表1，本發明的極性偵測器1〇〇最好取 樣連續的脈波’藉以提供一輸出信號來指示連續脈波的極 性。 圖2到圖8説明極性偵測器10〇的不同信號的時序圖，其 可參考來更詳細地了解極性偵測器100的動作。在開始的 時候，極性偵測器100啓始而且連續的脈波120提供到極性 偵測器100。當時鐘脈波301的升起邊緣發生時，它使得雙 穩態105取樣脈波201，有一遲輯〇狀態的連續脈波12〇。因 此，輸出信號121有一邏輯〇狀態401，而輸出信號122， 123 ’ 124及125分別有一不確定狀態5〇1，601，701及801。 注意一不確定狀態無法由極性偵測器丨⑻的邏輯電路分辨 出來是邏輯1或邏輯0 *時鐘脈波302的發生使得輸出信號 121維持在邏輯0狀態401，並使得輸出122，123及124分別 改變爲遲輯〇狀態502，602及702。因此，當時鐘脈波3〇2 發生時’提供到雙穩態109的輸出信號124是一不確定狀態 ，雙穩態的輸出信號125維持在不確定狀態8〇ι ^當時鐘脈 波303發生時，雙穩態1〇5取樣有遲輯丨狀態的脈波2〇2，在 連續脈波120，而輸出信號121改變爲邏輯丨狀態4〇2。同時 ，雙穩態107的輸出信號122維持在遲輯0狀態5〇2 ;互斥 OR閘131接收有邏輯1狀態402的輸出信號12ι，及有邏輯〇 狀態502的輸出信號122使得輸出信號123改變成邏輯1狀態 603 ;及輸出信號125成爲邏輯0狀態8〇2。在時鐘脈波3〇3 發生之後，極性偵測器100的起始動作結束，而極性偵測 -9 - 本紙張尺度適用中國國冬標準（CNS ) A4規格（210X 297公釐） | 扯衣-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 ^05941 A7 B7 i、發明説明（7) 器的動作則如囷2到圖8的時序躅所説明的進行β 圖9説明一流程圖詳述極性偵測器1〇〇的動作。同時也參 考圖1 ’極性偵測器1〇〇藉取得並儲存305連續脈波12〇的取 樣而動作。這由雙穩態105在它接收來自時鐘產生器114的 時鐘脈波時完成。下一步是決定315取樣的極性。在較佳 的具體實例中，取樣的極性決定自取樣所代表的邏輯水平 ，如上面所定義的》當取樣的極性是正的，一進—步的決 定320則根據取樣的極性是否相同於前一個取樣的極性。 當取樣的極性並不相同，則極性偵測器1〇〇的輸出信號 沒有改變。當取樣的極性相同，則進·步的決定325則根 據取樣的正極性是否相同於極性/f貞測器1〇〇的輪出信號125 的極性。當極性偵測器100的輸出信號125的極性不同於取 樣的極性，則輸出信號125的極性改變330成儲存取樣的極 性。然而，當輸出信號125的極性相同於取樣的極性，則 輸出信號不改變，且極性偵測器100回過來取得下一個取 樣。一個與以上類似的動作發生在極性偵測器100取得— 負極性取樣的時候。 根據本發明一極性偵測器提供使用數位電路來偵測一連 續脈波的極性。這用雙穩態來取樣，並儲存取樣，一連續 的脈波來達到。接著，使用邏輯電路來比較取樣的極性， 在進一步比較取樣的極性與輸出信號的極性，一決定係根 據輸出信號是否指示出取樣的極性，且輸出信號的極性便 可改變來指示取樣的極性。因此，輸出信號可以很妤的指 示出連續脈波的極性。另外，因爲本發明可以很容易的用 -10 - 本紙張尺度適用中國國家標隼（CNS ) A4規格（210x 297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印製 A7 B7__五、發明説明（8) 數位電路實現，它可以很好的整合在單半導體晶片上的控 制器來使用在電腦監視器中，藉之提供一單一包裝的解決 方法。這可以更容易的由電腦監視器的廠商來設計在它們 的產品中。再者，單一包裝允許較簡易組裝結果是成本的 節省，及零件數目的降低改善了電腦監視器的可靠性。 如此，根據本發明的極性债測器檢測出電腦監視器中水 平及垂直同步脈波的極性，而不需要電阻與電容，不需要 複雜安排的計數器與比較器，並整合到一單晶片中的電腦 監視控制器，而沒有控制器晶片複雜性，功能性及成本的 負面效應。 n·' nn 11 1^1 ^n· n^i ^^^1 I - HI m I ^^^1、一3^. . * (請先閱讀背面之注意事項再填寫本莧) -11 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）^ C 5 ό41 A7 ____ B7 ~ ·-———… ~ _-—-— V. Description of the invention (1) Scope of the invention The present invention is generally related to a polarity detector. The present invention is particularly useful, but is not necessarily limited to detecting the polarity of continuous synchronized pulses in computer monitors. Background of the Invention In computer monitors, the vertical and horizontal synchronous pulse waves determine the timing, which can ensure that the display on the monitor can be reproduced correctly. To do this, the circuit in the computer monitor must detect the polarity of the vertical and horizontal sync pulses. A traditional analog method for detecting the polarity of a synchronization pulse is to use a resistance-capacitance (R / C) integration circuit that averages the synchronization pulse over a predetermined period of time. The polarity of the sync pulse is determined by the average size. However, since a relatively large number of resistors and capacitors are required, it is difficult to arrange the resistors and capacitors on the semiconductor chip. Therefore, this limits the ability to integrate this type of polarity detector into a digital computer monitor control chip. A traditional digital method for detecting the polarity of a synchronized pulse is to use a counter and a comparator. However, although this type of digital polarity detector can be integrated into a digital computer monitor to control a large number of components, resulting in increased current consumption, the size and speed of the chip may not be sufficient for some applications of the control chip. Summary of the Invention DuPont Printing by Employees 'Consumer Cooperation of the Central Bureau of Standards and Economics of the Ministry of Economic Affairs --II ·-I' ----- ------ Order * (Please read the precautions on the back before filling this page) One purpose is to overcome or alleviate the problem of at least one prior art polarity detector. According to one aspect of the present invention, there is provided-a polarity detector including:-a storage device selectively sampling and storing at least two consecutive pulses; and a digital comparator device connected to the image storage S output to provide comparison samples One output signal ', which is used, the change of the output signal is based on its polarity -4- this paper standard Guanjia Standard (CNS) A4 specification (21Qx 2974 Dong) A7 ----_______ _ B7 V. Invention Say ^ (2) ~~~~~ ---, then the sampling will have the same polarity, and if the polarity of the sampling is not, the output signal will remain unchanged. Preferably, the #storage device can have a clock input to achieve storage. Suitably, the storage device may contain two bistable states. The digital comparator can include a storage for the output signal; a device to store the output signal. The output signal storage device can be connected to the clock input of the storage device to achieve the surplus of the output signal by receiving the clock signal. Preferably, the digital comparator includes a late circuit connection to receive a stored output signal which is then compared with the sample. According to another aspect of the present invention, there is provided a method to continuously evaluate the polarity of the pulse wave. The steps of this method include: Wang) selective sampling and storing the sampling of the pulse wave; and b) comparing this sampling to provide an indication Check whether the output signals with the same polarity are sampled. Preferably, the selective sampling and storage step ⑻ can be achieved by a clock signal. Suitably, step (b) of the comparison also includes the step of storing the output signal in at least one clock signal period. Most notably, the comparison step (b) also includes a comparison step of sampling and output signals. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a polarity detector according to a preferred embodiment of the present invention. 2 to 8 illustrate the timing waveform a of the polarity detector in FIG. 1 according to a preferred embodiment of the present invention. FIG. 9 illustrates the polarity detector in FIG. 1 according to a preferred embodiment of the present invention. The standard is applicable to China National Standard (CNS) Α4 specification (2 丨 0X297mm) (please read the notes on the back before filling in this page) 装 ·-丁-、 τ Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Duzhong Yao purse bureau member X Consumer Cooperation 'printed Λ7 ---------- Β7 _ V. Description of the invention (3) Detailed flow chart of the operation. The detailed description of the invention is in the following description, Reference to a pulse wave or sampling logic 0 and operation state has a negative polarity, reference to a pulse wave or sampling delay 1 and operation state i has a positive polarity. FIG. 1 illustrates a polarity detector 10〇, which A storage device 102 and a digital comparator 103 are included. The storage device 102 includes bistable IO05 and 107, and the digital comparator 103 includes a logic circuit 108 and bistable 1009. Bistable ι〇5 is connected to a clock signal generator Π4 and a continuous pulse wave 120 »The output of bistable 105 An input of the mutually exclusive OR gate 31 of the bistable 107 and the logic circuit 108 is connected to the bistable 107 to receive the clock signal generator 1M. An output of the bistable 107 is connected to the mutually exclusive OR Another input of gate 131 and an input of an AND gate 132. An output of the mutually exclusive OR gate is connected to the input of gate U2, which is an inverting input, and an input of an AND gate 133. and gates 132 and 133 The output of is connected to the input of an OR gate 134, and one output is connected to the bistable 109. An output of the bistable 109 is connected to the other input of the AND gate 133. The clock signal generator provides a clock signal 115 Clock signals input to bistable 105 '107 and 109. Different signals recognized in polarity detector 100 include: output signal 121 of bistable state 105; output signal of bistable 107 122; the output signal 123 of the mutually exclusive OR gate 131; the output signal 124 of the OR gate 134; and the output signal 125 of the bistable 109. The clock signal 115 is input to the bistable 105 and 107 to achieve sampling and store the sample, Continuous pulse wave 120. The samples are stored in bistable states 105 and 107, and output signal 121 and 122 is provided to the logic circuit 108. The logic circuit 108 -6-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling in this page). A7 _B7 printed by the Bureau ’s Consumer Cooperatives 5. Description of the invention (4) It includes a mutually exclusive OR gate 131 connected to receive the output signal 121 of the bistable 105 and connected to receive the output signal 122 of the bistable 107, and Provide an output signal 123. The mutually exclusive OR gate 131 compares the samples stored by the bistable 150 and 107. The output signal 123 provided has a late 1 when the stored sample polarity is different, and the output signal 123 provided has a logic when the polarity of the wrong access sample is the same 〇. The output signal 123 is provided to a pair of AND gates 132 and 133, and their outputs are transmitted to the OR gate 134 and provide an input of the output signal 124 to the bistable 109. The AND gate 133 is enabled when the sampling polarities are different, and the AND gate 134 is enabled when the sampling polarities are the same. When a logic 1 is sent to one of the two inputs of a gate with two inputs, the AND gate is enabled. This means that the enabled AND gate produces an output that has the same delay as the other input provided to the AND gate, that is, the logic on the other input of the gate passes through the gate to reach the output of the AND gate. The bistable 109 receives the clock signal 115 and the output signal 124, and correspondingly generates an output signal 125. Bistable state 109 stores the output signal 125 for at least one clock period of the clock signal 115. The AND gate 133 is also connected to receive the output signal 125, and when the sampling polarity is different and the clock pulse of the clock signal 115 occurs, the 'output signal 125 or delay 1 or logic 0 passes through this gate 133, OR gate 134' and then Via the output signal 124, the bistable state 109 is reached. This keeps the output signal 125 in its original logic state, which occurs when the clock pulse occurs, that is, the output signal remains unchanged. In addition, the gate is connected to receive the output signal Π2 and the output signal 123. The AND gate 132 inverts the output signal 123, so that when the stored samples have the same polarity, the AND gate 132 is enabled by the inverted output signal 123. Therefore, when the stored -7 is taken, this B scale is based on Zhongguanjia County (CNS) A4 specifications (-21Qx297 ^ factory ---- i .. binding (please read the precautions on the back before filling in this page) Economy Printed by the Ministry of Standards and Staff's Consumer Cooperatives of the Ministry of Standards A7 B7 5. Invention description (5) When a clock pulse of the clock signal 115 is the same, the output signal 122 indicates the polarity of the stored sample, or logic 1 or logic 0, The connection goes through the AND gate 132 'OR gate 134' and reaches the bistable 109 via the output signal 124. This allows the output signal ι25 to have the polarity of the stored sample. The bistable ι〇5 '107 and 109 are edge-triggered positive type j) positive Inverters, however, any functionally similar type of bistable, such as known in the art can be used. The logic circuit 108 may include other logic gates different from those described, however, it can be understood that different combinations of logic gates can be used to implement the same logic function as the logic circuit 108. 0 1 η Q2n Fn + 1 0 0 0 0 1 Fn 1 0 Fn 1 1 1 Table 1 The above Table 1 illustrates the logic functions performed by the polarity detector 100, where Q1 and Q2 are bistable 105 and 1 respectively. The output of 7 indicates the polarity of the sample, and F is the output signal 丨 25. The marks „and n + 1 indicate the clock pulse sequence. For example, looking at the first column of Table 1, when the clock pulse η occurs, Qi and φ are —logic 0 ′ indicating that the polarity of the sampling is negative. Therefore, the output signal F is logic 0 'indicates that when a next clock pulse 11 + 1 occurs, the polarity of the continuous pulse is negative. From the second and third columns of Table 1, when the input Q1 and Q2 are not the same, when one It is logic 0 and the other is logic 1, the output signal F is unchanged. This indicates that the inconsistent change of the polarity of the continuous pulse has been detected and so -8- This paper scale is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this page) Binding. Order A 7 B7 5. Description of the invention (6) 'The output signal F remains unchanged. From the fourth column, when qi and Q2 If it is set 1, the output signal is 1. From Table 1, the polarity detector 100 of the present invention preferably samples continuous pulses to provide an output signal to indicate the polarity of the continuous pulses. Figure 2 to Figure 8 illustrates the timing diagram of different signals of the polarity detector 10, which can be referred to for more details The action of the sex detector 100. At the beginning, the polarity detector 100 starts and a continuous pulse 120 is provided to the polarity detector 100. When the rising edge of the clock pulse 301 occurs, it makes the bistable State 105 samples pulse 201, and there is a continuous pulse 12 in the late 0 state. Therefore, the output signal 121 has a logic 0 state 401, and the output signals 122, 123 '124, and 125 have an indeterminate state 50 1, 601, respectively. , 701 and 801. Note that an indeterminate state cannot be distinguished by the logic circuit of the polarity detector 丨 ⑻ is a logic 1 or a logic 0 * The occurrence of the clock pulse 302 keeps the output signal 121 at the logic 0 state 401 and makes the output 122, 123, and 124 change to the late state 502, 602, and 702. Therefore, when the clock pulse 30 2 occurs, the output signal 124 provided to the bistable state 109 is an indeterminate state, bistable The output signal 125 is maintained in an indeterminate state 80. When the clock pulse 303 occurs, the bistable state 105 samples the pulse 2O2 with the delayed state. During the continuous pulse 120, the output signal 121 changes. Is logic 丨 state 40. At the same time, bistable The output signal 122 of the state 107 is maintained at the late 0 state 502; the mutually exclusive OR gate 131 receives the output signal 121 of the logic 1 state 402, and the output signal 122 of the logic 0 state 502 causes the output signal 123 to change to a logic 1 State 603; and the output signal 125 becomes a logic 0 state 8〇2. After the clock pulse 303 occurs, the initial action of the polarity detector 100 ends, and the polarity detection -9-This paper scale applies to China National Winter Standard (CNS) A4 specification (210X 297mm) | Zipper-(please read the precautions on the back and then fill out this page) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy ^ 05941 A7 B7 i. Description of invention ( 7) The operation of the detector is performed as explained in the timing sequence from FIG. 2 to FIG. 8. β FIG. 9 illustrates a flowchart detailing the operation of the polarity detector 100. At the same time, refer also to FIG. 1 'Polarity detector 100 is operated by acquiring and storing 305 the sampling of continuous pulse wave 12〇. This is done by the bistable 105 when it receives the clock pulse from the clock generator 114. The next step is to determine the polarity of the 315 samples. In a preferred embodiment, the polarity of the sampling determines the logical level represented by the sampling. As defined above, when the polarity of the sampling is positive, a further decision 320 is based on whether the sampling polarity is the same as the previous one. Sampling polarity. When the sampling polarities are not the same, the output signal of the polarity detector 100 does not change. When the polarities of the samples are the same, the further decision 325 is based on whether the positive polarity of the samples is the same as the polarity of the round-out signal 125 of the polarity / f detector 100. When the polarity of the output signal 125 of the polarity detector 100 is different from the sampling polarity, the polarity of the output signal 125 changes 330 to the stored sampling polarity. However, when the polarity of the output signal 125 is the same as the sampling polarity, the output signal does not change, and the polarity detector 100 goes back to take the next sample. An action similar to the above occurs when the polarity detector 100 acquires-negative polarity sampling. According to the invention, a polarity detector provides the use of digital circuits to detect the polarity of a continuous pulse. This is sampled with bistable, and the sample is stored, and a continuous pulse wave is achieved. Next, a logic circuit is used to compare the polarity of the samples. In further comparing the polarity of the samples with the polarity of the output signal, a decision is made based on whether the output signal indicates the polarity of the sample, and the polarity of the output signal can be changed to indicate the polarity of the sample. Therefore, the output signal can indicate the polarity of the continuous pulse wave. In addition, because the present invention can be easily used -10-This paper scale is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210x 297 mm) (please read the precautions on the back before filling this page) • Packing and ordering economy Printed by the Ministry of Standards and Staff Consumer Cooperative of the Ministry of Economic Affairs Printed by the Ministry of Economic Affairs of the Central Standards Bureau of the Employees and Consumer Cooperatives In computer monitors, it provides a single package solution. This can be more easily designed by computer monitor manufacturers in their products. Furthermore, a single package allows simpler assembly, resulting in cost savings, and a reduction in the number of parts improves the reliability of the computer monitor. In this way, the polarity detector according to the present invention detects the polarity of the horizontal and vertical synchronous pulse waves in the computer monitor, without the need for resistance and capacitance, without requiring a complicated arrangement of counters and comparators, and is integrated into The computer monitors the controller without the negative effects of controller chip complexity, functionality and cost. n · 'nn 11 1 ^ 1 ^ n · n ^ i ^^^ 1 I-HI m I ^^^ 1, a 3 ^.. * (Please read the precautions on the back before filling in this amaranth) -11- The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)