A7 B7 五、發明説明（） 本發明傜一種鰭狀《層電容單層複晶矽形成内電極板 製法，主要為一種形成璺層電容内層電極板之製法，僅需 一次複晶矽沈積步驟卽可形成鰭片型式之内層電極板，而 具製造簡便、快速及低成本之優點。 按現今可隨意讀寫之記億體（RAM)邸區分為靜態 記億體（SRAM)及動態記億體（DRAM),靜態記 億體雖有高速特性，然由於體積大及價格高之因素下，故 而常適用於需高速存取之使用場合，而現今對於較慢速之 使用場合時，即使用動態記億體，藉由此動態記億體之容 置高、省電及價格較為低廉之特性，為現今做為電腦主記 億體所使用之元件，然此種動態記億體雖有前述諸多優點 ,然其最大的缺點為需不斷地定時對之充電 （REFRESH), 以維持記億内容，故而記億體之電荷儲存能力卽異常地重 要，是以，現今動態記憶體製程中均有形成疊層電容器 (STACKED CAPACITOR)之製法，以在内部位置形成叠層電容 ,藉其可適當儲存電荷之特性，逹到延長雒持記億内容之 時間，據以提昇其實用性。 惟受到晶片面積之限制，僅製成單純片狀型式之疊層 電容，顯無法符合較高電容量之效果，故有鑒於此，卽有 所諝蓮用類似如散熱片之鰭片狀多層電極板構成該等叠層 電容，以藉由該多層型式，達到加大電極板之表面積，以 改善電容董過低之問題，然以現有製成該等鰭片型式之習 見製法上，概為以氣化層及複晶矽層依次做交錯式多層沈 -3- 本纸張尺度適用中國國家標準（CNS ) A4洗格（210X 297公釐） I II 裝 I訂 線 (請先閱讀背面之注意事項再填寫本頁) ^ ^ VI υ Ο Α7 _ Β7 五、發明説明（） 積作業，再以蝕刻方式去除介於複晶矽層間之氣化雇，以 使該各複晶矽形成前述鰭Μ狀電極板型式，然以前逑該等 必須依次形成氣化層及沈積複晶矽等多；1構造下，卽受限 於兩種材料必須在不同之操作室内進行，故有箸必須多次 往返於各操作室間，顯然造成製程一貫作業上的不便及麻 煩，亦使其製程較為耗時而造成製程週期延長，另對於該 等間隔之多層複晶矽構造，其相互間之並聯連接方式，傜 透過各複晶矽之側壁相互結合，亦致使製程尤為困難，是 以，前述傳統鰭片狀電容之多層氣化層及多層複晶矽 交錯β合製程繁瑣及複晶矽相互連接亦靥困難之情況下， 顯無法符合高效率及低製造成本之要求，卽有予以改善之 必要。 本發明人鑑於習用之缺點乃經悉心地試驗與研究並一 本鍥而不捨之發明精神，終創作出一種鰭狀叠層電容單層 複晶矽形成内電極板製法，主要為以類似如氣化層及氮化 矽等不同隔離材料予以交錯重叠形成多層構造，、經選擇性 蝕刻去除其一隔離材料，以形成一鰭片狀凹孔，再於該鰭 Η狀凹孔内僅需進行一次沈積複晶矽之步驟，即可完全镇 滿該凹孔而形成鰭片狀複晶矽構造，後缠僅需蝕刻去除其 餘之隔離材料，即形成一電容内層電極板，而以前述多層 隔離材料之交錯重叠作業僅為使用不同氣體卽可完成，且 後缠複晶矽沈積作業亦僅需一次即可達成，故其整體製程 卽相當簡便而迅速，為一製程較為簡便之鰭狀疊層電容内 -4- 本紙張尺度適用中國國家標隼（CNS ) Α4规格（210Χ297公釐） 裝 訂 I線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中夬樣隼局員I.消費合作fi-s-裂 A7 B7 五、發明説明（） 電極板製法者。 為使 貴審査委員能進一步瞭解本發明之製法，特擞 及其他目的，玆 附以圖式詳細說明如后： (一）·圖式部份： 第一圖：傜本發明之實施例㈠剖面構造圖》 第二圖：係本發明之實施例㈠製程示意圖。 第三圖：係本發明之實施例㈡剖面構造圖β 第四圖：傜本創作之實施例㈡製程示意圖。 依據本發明以單層複晶矽沈積作業形成》垴電容内電 極板之製法，可形成如第一圖或第三圖兩種不同型式之叠 層電容，亦即本發明之内電極板可製成如第一圖該第二複 晶矽β (Ρ 2)之各鰭片呈朝外之型式或是如第三圖該第 三複晶矽層（Ρ3)之各鳍片呈朝内之形態者，在第一鼸 中，即以該第二複矽晶層（Ρ 2)形成叠層電容之内層電 極板，而外圍覆蓋有一極薄之介質電層（20)及一形成 為《屬電容外層電極板之第三複晶矽層（Ρ3)組成一電 容構造，以該第二、三複晶矽層（Ρ2) (Ρ3)間該多 庙對應型態，達到高電容董之效果，而在第一、三圖下方 之其他位在矽層（SUB)上之源洩極（Ν + )區、第一 複晶矽閘極（P1)及場區（FOX)則為動態記億體之 習見構造，且非本發明之特激所在，故不予贅述，而對於 第三圖之構造中，除了該電容之電極板型式略有差異外， 兩側之第三複晶矽層（P3)係藉由位在下方之第二複晶 -5 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------裝— (請先閱讀背面之注意事項再填寫本頁) 訂 線 經濟部中央樣隼局員工消費合作杜中裂 A7 B7 i、發明説明（） 矽層（P2)予以相互連接而形成叠層電容之内®電極板 ,而包覆在第三複晶矽餍（P3)外側亦依序為介電質層 (20)及做為外層電極板之第四複晶矽層（P4)，故 由第二、三、四複晶矽jg(P2) ( P 3 ) (P4)構成 ~電容構造。 而本發明製法待色為在該前述第一圖之第二複晶矽層 (P 2)及第三圖之第三複晶砂層（P3)所構成之電容 内層電極板，僅由一次沈積作業完成，較傳統箱多層複晶 矽依序沈積簡便而具較佳之製程效率，該兩種實施例之製 法方面，即可配合參看第二、四圖所示，首先參看第二A 圖所示，卽在矽層（SUB)上方先行沈積一氮化矽層（ S i N)及位在上方標示為1至6之六層透過不同氣體予 以沈積形成之隔離材料，此六層材料之奇數及偶數層分別 以氣化矽及氮化矽層交叉重叠而成（或可採類似之材料， 如氣化矽與多矽氣化層（silicon rich之SiOz )、氮氣化矽 (SiOxNy)與氮化矽（Si3 N4 )等），由於各値沈積層僅以不 同氣體環境下進行，而無需進出不同操作室之煩繁步驟， 具製造方便性，而在前述各隔離層沈積完成後，即於上方 兩側覆蓋光阻（PR)，並對該各層中央未覆蓋光阻位置 進行乾式蝕刻形成凹陷槽，然後再進行一次對各奇數之氣 化厢1、3、5層之選擇性濕式蝕刻作業，以使該對應於 中央凹陷槽兩側之各奇數層蝕刻一適當深度（横向長度） ，其次，於去除光阻（P R )後，即可進行第二複晶矽層 -6- 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 裝 訂 線 (請先閲讀背面之注意事項再填寫本頁} 2〇:n〇e Β7 五、發明説明（ ) 1 1 ( P 2 ) 光 罩 / 沈 積 作 業 即 如 第 二 B 圖 所 示 t 該 沈 積 之 1 1 第 二 複 晶 矽 層 ( P 2 ) 卽 如 圖 面 之 斜 線 區 域 所 示 t m 適 當 1 1 地 延 伸 進 人 至 前 述 被 部 份 蝕 刻 去 除 之 奇 數 層 凹 孔 内 9 而 呈 y—n 請 先 1 1 現 —- 對 稱 於 左 N 右 位 置 之 鳍 片 之 爪 狀 型 式 9 至 此 該 等 第 閲 讀 1 背 1 二 複 晶 矽 層 ( P 2 ) 卽 形 成 為 叠 層 電 容 之 内 m 電 極 板 9 且 面 之 1 注 此 等 步 驟 中 » 邸 僅 需 一 次 沈 積 作 業 m 完 成 該 複 晶 矽 内 層 電 意 事 1 | 極 板 構 造 > 確 具 作 業 迅 速 之 優 點 9 後 绩 即 蝕 刻 去 除 該 第 二 再 填 1 複 晶 矽 層 ( P 2 ) 以 外 之 各 氣 化 層 及 氮 化 矽 層 構 造 ( 如 第 寫 本 % 1 二 C 圖 ) ( 以 稀 釋 之 氫 氟 酸 溶 液 進 行 蝕 刻 ) > 繼 而 再 以 沈 1 I 積 一 包 覆 在 第 二 複 晶 矽 層 ( P 2 ) 各 個 外 表 面 之 介 電 質 層 1 1 I ( 可 為 氮 化 矽 ) 及 沈 積 如 第 二 D 圖 所 示 tt* 兀 全 覆 蓋 及 延 伸 在 1 1 各 鰭 片 内 部 位 置 之 第 三 複 晶 矽 層 ( P 3 ) 即 完 成 鳍 片 狀 訂 I 叠 層 電 容 Ο 1 I 而 對 應 於 第 三 圖 該 等 型 式 之 叠 層 電 容 之 製 法 S 其 不 同 1 1 於 前 述 製 程 為 如 第 四 A 圖 所 示 9 在 沈 積 下 方 之 氮 化 矽 層 ( 1 1 S i N ) 後 9 更 在 該 氮 化 矽 層 ( S i N ) 中 段 蝕 刻 出 開 P 線 | 而 沈 積 一 如 斜 線 所 示 之 供 做 電 容 極 板 連 接 之 第 二 複 晶 矽 層 1 | ( P 2 ) 材 料 9 而 在 第 二 複 晶 矽 層 ( P 2 ) 上 方 卽 為 柑 同 1 1 於 前 述 沈 積 多 層 交 錯 之 氣 化 層 及 氛 化 矽 層 等 隔 離 材 料 並 1 1 令 光 阻 ( P R ) 轉 變 為 覆 蓋 在 中 央 部 位 上 f 於 後 缅 之 乾 V 1 1 濕 式 蝕 刻 步 驟 i 邸 蝕 刻 去 除 位 在 光 阻 ( P R ) 外 側 部 位 > 1 1 | 並 令 各 屬 隔 離 材 料 中 之 氣 化 IS 向 中 央 形 成 適 當 深 度 之 凹 孔 1 1 I 而 在 進 行 第 複 晶 矽 屬 ( P 7- 3 ) 沈 積 作 業 •sis· 兀 成 後 t 即 形 1 1 1 1 1 本紙張尺度適用中國國家標芈（CNS ) Α4規格（210Χ 297公釐） A7 7 Β 五、發明説明（） 成為如第四B圖之以該第三複晶矽（P3)包覆外圍且填 滿内部凹孔之型式，更進行該第三複晶矽（P 3)之反蝕 刻步驟（蝕刻形成側壁雇（SPACER)之步驟），使位在最上 方之第三複晶矽材料連同位在中央之各層隔離材料一併去 除，卽形成為如第四C圖構成一朝内對稱鰭片構造之内層 電極板，後缠概以相同於前述形成電容介電質層及形成電 容外層電極板之步驟，依序進行沈積介電質層（40)及 沈積第四複晶矽層（P4)即形成如第四D圖所構成之曼 層電容構造者，而此例中，由於該形成内層電極板之第三 複晶矽層（P3)為以形成側壁層之反蝕刻步驟完成，可 免除該層光罩作業，另可藉由第三複晶矽形成之側壁構造 亦適當提高電容表面積，可獲致略高之電容容量。 以下即表列傳統疊層電容與本發明各項數據如下： 傳統叠層電容 本發明 每電容量 5 〜1 0 f F 2 0 〜5 0 f F 每CELL面積 2 〜4 m 2 0 · 4〜1必m 2 (電容量> = 20fF) 崩潰電壓 大於7伏待 大於7伏特 本紙伕尺度適用中國國家榡準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) .装. ,ιτ B7 i、發明説明（） 漏電流 小於lfA/#m2 小於lfA/；um2 良 率 依産品而不同 與傳統方法相近 由上逑數據可知，本發明製出之叠層電容可在約相同 的崩潰電壓、漏電流及良率之情況下，每位元（CELL )之電容佔用面積更僅約為傳統之四分之一。 是以，由前述本發明之鰭片型II層電容之製法步驟中 ,即免除傳統製程中該内層電極板需以多屬氣化層及複晶 矽層交叠之製程實施極為不便之缺點，而透過不同材料之 隔離®做多層沈積後，經選擇性蝕刻使部份隔離雇形成一 鳍狀凹孔，使其僅需一次複晶矽沈積步驟即可填滿該鰭狀 凹孔而形成該等内雇電極板，顯較習見製程更為迅速及符 合高效率之特性，為一形成叠層電容之新穎且具進步性之 製法，應符專利申請要件，爰依法提出申請。 -9- 本紙張尺度適用中國國家橾率（CNS ) Α4说格（210Χ297公釐） I — 訂 線 (請先閲讀背面之注意事項再填寫本頁)A7 B7 5. Description of the invention () This invention is a fin-shaped "layer capacitor single-layer polycrystalline silicon forming inner electrode plate manufacturing method, which is mainly a method for forming an inner electrode plate of a layer capacitor, requiring only one step of polycrystalline silicon deposition. The inner electrode plate of the fin type can be formed, which has the advantages of simple manufacture, fast and low cost. According to the RAM that can be read and written at present, it is divided into static RAM (SRAM) and dynamic RAM (DRAM). Although the static RAM has high-speed characteristics, it is due to the large size and high price. Therefore, it is often suitable for use occasions that require high-speed access. Nowadays, for slower-speed use occasions, dynamic memory units are used. With this, the capacity of the dynamic memory units is high, power saving, and the price is relatively low. The characteristics are the components used today as the computer's main memory, although this kind of dynamic memory has many advantages, but its biggest disadvantage is that it needs to be constantly charged (REFRESH) to maintain the memory. 100 million content, so the charge storage capacity of the 100 million body is extremely important. Therefore, in today's dynamic memory system, a method of forming a stacked capacitor (STACKED CAPACITOR) is used to form a stacked capacitor at an internal position. The characteristics of proper storage of electric charges can extend the time for Luo to hold 100 million contents, so as to enhance its practicality. However, due to the limitation of the chip area, only a simple chip type of multilayer capacitor is made, which is obviously unable to meet the effect of higher capacitance. Therefore, in view of this, some of them use fin-like multilayer electrodes similar to heat sinks. The multilayer capacitors are formed by the plates, so that the surface area of the electrode plates can be increased by the multi-layer type to improve the problem of too low capacitance. However, the conventional manufacturing methods for making these fin types are generally based on The gasification layer and the polycrystalline silicon layer are sequentially interleaved multi-layer Shen-3- The paper size is applicable to the Chinese National Standard (CNS) A4 wash grid (210X 297mm) I II Binding I binding line (please read the note on the back first Please fill in this page again) ^ ^ VI υ Ο Α7 _ Β7 V. Description of the invention () Productive operation, then remove the gasification between the polycrystalline silicon layer by etching, so that each polycrystalline silicon forms the aforementioned fin M The shape of the electrode plate, but in the past, these must be formed in order to form a vaporized layer and deposited polycrystalline silicon, etc .; 1. Under the structure, the two materials must be carried out in different operating rooms, so the grate must be back and forth multiple times In each operation room, it obviously caused the process one The inconvenience and trouble in the implementation of the operation also make the process more time-consuming and cause the process cycle to be extended. In addition, for the multi-layer polycrystalline silicon structures at these intervals, the parallel connection mode between them is through the side walls of each polycrystalline silicon. The combination also makes the process particularly difficult. Therefore, the above-mentioned traditional fin-shaped capacitor's multi-layer vaporization layer and multi-layer polycrystalline silicon interlaced β-bonding process is complicated and the interconnection of polycrystalline silicon is also difficult. And the requirement of low manufacturing cost, it is necessary to improve it. In view of the shortcomings of the practice, the inventors have carefully experimented and studied and combined with the persistent spirit of the invention, and finally created a method for forming an internal electrode plate of a single-layer polycrystalline silicon fin-shaped laminated capacitor, mainly by a similar Different isolation materials such as silicon nitride and silicon nitride are alternately overlapped to form a multi-layer structure, and one of the isolation materials is removed by selective etching to form a fin-shaped concave hole, and then only one deposition and restoration is required in the fin-shaped concave hole In the step of crystalline silicon, the concave hole can be completely filled to form a fin-like polycrystalline silicon structure. After the entanglement, only the remaining isolation material needs to be etched to form a capacitor inner electrode plate, and the interleaved multi-layer isolation material is formed. The overlapping operation can only be completed by using different gases, and the post-wrapping polycrystalline silicon deposition operation can be achieved only once, so the overall process is very simple and fast. It is a relatively simple process in the fin-shaped multilayer capacitor- 4- This paper scale is applicable to China National Standard Falcon (CNS) Α4 specification (210Χ297mm) Binding I line (please read the precautions on the back before filling this page) Ministry of Economics Falcon Falcon I. Consumption members cooperate fi-s- A7 B7 five-lobed, the invention described () method of the electrode plate were prepared. In order to enable your reviewing committee to further understand the manufacturing method, special features and other purposes of the present invention, the drawings are attached to explain in detail as follows: (1) · Drawing part: The first picture: the embodiment of the present invention (i) section Construction drawing "Second drawing: It is a schematic diagram of the manufacturing process of the embodiment of the present invention. The third picture: is the embodiment of the present invention (II) cross-sectional structure diagram β The fourth picture: the embodiment of the original writing (II) process schematic diagram. According to the present invention, a method of forming a monolayer polycrystalline silicon deposition operation to form an NAO capacitor internal electrode plate can form two different types of stacked capacitors as shown in the first picture or the third picture, that is, the internal electrode plate of the present invention can be manufactured As shown in the first figure, the fins of the second polycrystalline silicon β (Ρ 2) are outward-facing or as shown in the third figure, the fins of the third polycrystalline silicon layer (Ρ3) are inward-facing In addition, in the first Na, the second complex silicon crystal layer (P 2) is used to form the inner electrode plate of the stacked capacitor, and the periphery is covered with an extremely thin dielectric layer (20) and a The third polycrystalline silicon layer (Ρ3) of the outer electrode plate constitutes a capacitor structure. With the corresponding pattern of the multiple temples between the second and triple polycrystalline silicon layers (Ρ2) (Ρ3), the effect of high capacitance Dong is achieved, and The other source and drain (N +) regions, the first polycrystalline silicon gate (P1) and the field region (FOX) located on the silicon layer (SUB) below the first and third figures are dynamic memory The conventional structure is not the special feature of the present invention, so it will not be described in detail. For the structure of the third figure, except for the slight difference in the electrode plate type of the capacitor, the two The third polycrystalline silicon layer (P3) is based on the second polycrystalline-5 located below-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) --------- -Installation — (Please read the precautions on the back and then fill out this page) The Ministry of Economic Affairs, Central Sample Falcon Bureau employee consumption cooperation Du Zhong crack A7 B7 i, invention description () Silicon layers (P2) are connected to each other to form a stack The inner electrode plate of the capacitor, and the outer side of the third polycrystalline silicon coating (P3) is also sequentially a dielectric layer (20) and the fourth polycrystalline silicon layer (P4) as the outer electrode plate, so It consists of second, third, and fourth polycrystalline silicon jg (P2) (P 3) (P4) ~ capacitor structure. The method of the present invention is to prepare a capacitor inner electrode plate composed of the second polycrystalline silicon layer (P 2) in the first figure and the third polycrystalline sand layer (P3) in the third figure, and only one deposition operation is performed. Finished, it is easier and more efficient to process sequentially than traditional box multi-layer polycrystalline silicon deposition. For the manufacturing methods of these two embodiments, please refer to the second and fourth figures, first refer to the second figure A, Then, first deposit a silicon nitride layer (S i N) on top of the silicon layer (SUB) and the six layers marked with 1 to 6 above are separated by different gases to form the isolation material, the six layers of materials are odd and even The layers are formed by cross-overlapping vaporized silicon and silicon nitride layers (or similar materials can be used, such as vaporized silicon and multi-silicon vaporized layers (silicon rich SiOz), nitrogenated silicon (SiOxNy) and silicon nitride (Si3 N4), etc.), because each deposition layer is only carried out under different gas environments, without the cumbersome steps of entering and leaving different operation rooms, it is convenient to manufacture, and after the deposition of each isolation layer described above, it is at the top two The side is covered with photoresist (PR), and the center of each layer is not covered with light Dry etching at the location to form a recessed groove, and then perform a selective wet etching operation on each of the odd-numbered gasification chambers 1, 3, and 5 layers, so that the odd-numbered layers corresponding to both sides of the central recessed groove are etched appropriately Depth (horizontal length), secondly, after removing the photoresist (PR), you can proceed to the second polycrystalline silicon layer -6- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) binding line (Please read the precautions on the back before filling this page) 2〇: n〇e Β7 5. Description of the invention () 1 1 (P 2) The photomask / deposition operation is as shown in the second B figure t of the deposition 1 1 The second polycrystalline silicon layer (P 2) is tm as shown in the oblique line area of the figure. It is appropriate to extend 1 1 into the odd-numbered concave holes that were partially etched and removed by the aforementioned 9. 1 Now —- the claw-like pattern of the fins symmetrical to the left N and right 9 so far this first reading 1 back 1 double polycrystalline silicon layer (P 2) is formed as a stack Within the capacitor m electrode plate 9 and the surface of 1 Note these steps »Di only needs one deposition operation m to complete the polysilicon inner layer electrical intention 1 | plate structure > indeed has the advantages of rapid operation 9 success Etch to remove the structure of each vaporized layer and silicon nitride layer other than the second refill 1 polycrystalline silicon layer (P 2) (as shown in the first book% 1 2C) (etched with diluted hydrofluoric acid solution) > Then, the surface of the second polycrystalline silicon layer (P 2) is covered with a sink 1 I to accumulate a dielectric layer 1 1 I (which can be silicon nitride) and sink as shown in the second Dtt * The third polycrystalline silicon layer (P 3) that completely covers and extends inside the fins of 1 1 completes the fin-shaped order I stack capacitance Ο 1 I and corresponds to the stack of these types in the third figure The method of making capacitor S is different 1 1 The foregoing process is as shown in the fourth A. 9 After the silicon nitride layer (1 1 S i N) under the deposit 9 is etched in the middle of the silicon nitride layer (S i N) to open the P line | The second polycrystalline silicon layer 1 (P 2) material 9 for connecting the capacitor plates as shown by the oblique line is above the second polycrystalline silicon layer (P 2) as the same as 1 1 interleaved in the previously deposited multilayer Isolation materials such as the vaporized layer and the oxidized silicon layer and 1 1 make the photoresist (PR) be covered on the central part f to be dried after the Myanmar V 1 1 Wet etching step i Di etching to remove the photoresist ( PR) outer part> 1 1 | and make the gasification IS in each isolation material to form a concave hole 1 1 I of appropriate depth toward the center while performing the first polycrystalline silicon (P 7-3) deposition operation • sis · After being formed, the shape is ready 1 1 1 1 1 This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ 297 mm) A7 7 Β V. Description of invention () Become the type of the fourth polysilicon (P3) covering the periphery and filling the internal concave holes as shown in the fourth B picture, and further performing the reverse etching step of the third polysilicon (P3) (etching to form the side wall) (SPACER) step, the third polycrystalline silicon material at the top and the isolation materials at the center are removed together to form an inner electrode forming an inwardly symmetric fin structure as shown in the fourth C diagram After the board is wrapped, the dielectric layer (40) and the deposited fourth polycrystalline silicon layer (P4) are formed in the same order as the previous steps of forming the capacitor dielectric layer and the capacitor outer electrode plate. The man-layer capacitor structure constructed by the four-D pattern, and in this case, since the third polycrystalline silicon layer (P3) forming the inner electrode plate is completed by the reverse etching step of forming the side wall layer, this layer of mask can be eliminated Operation, the side wall structure formed by the third polycrystalline silicon can also appropriately increase the surface area of the capacitor, and a slightly higher capacitance can be obtained. The following is a list of traditional stacked capacitors and the data of the present invention: The traditional stacked capacitors of the present invention each capacitance 5 ~ 1 0 f F 2 0 ~ 5 0 f F per cell area 2 ~ 4 m 2 0 · 4 ~ 1m2 (capacity > = 20fF) The breakdown voltage is greater than 7 volts and greater than 7 volts. The paper size of this paper is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling in this Page). Installed. Ιτ B7 i. Description of the invention () Leakage current is less than lfA / # m2 is less than lfA /; um2 The yield rate is different according to the product. It is similar to the traditional method. From the above data, we can see that the multilayer capacitor made by the present invention Under the condition of about the same breakdown voltage, leakage current and yield, the occupied area of the capacitor per bit (CELL) is only about one-quarter of the conventional one. Therefore, in the above-mentioned manufacturing method of the fin-type II layer capacitor of the present invention, that is, it avoids the disadvantages of the traditional process that the inner electrode plate needs to be implemented by the process of overlapping the vaporized layer and the polycrystalline silicon layer, which is extremely inconvenient. After multi-layer deposition through isolation of different materials, part of the isolation is selectively etched to form a fin-shaped concave hole, so that only one polycrystalline silicon deposition step is needed to fill the fin-shaped concave hole to form the fin-shaped concave hole The internal electrode plate is much faster and more efficient than the conventional process. It is a novel and progressive method for forming multilayer capacitors. It should comply with the patent application requirements and file an application according to law. -9- This paper scale is applicable to China's National Standard Rate (CNS) Α4 said grid (210Χ297mm) I — line booking (please read the precautions on the back before filling this page)