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Application filed by Programmable MicroelectronicsfiledCriticalProgrammable Microelectronics
Priority to TW85101617ApriorityCriticalpatent/TW289165B/en
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A triple split gate PMOS flash memory cell comprises the mainstructures of: (1) well region with implanted one P+ source, one P+ drain and one channel between source and drain; (2) one first insulator grown on well region; (3) one floating gate grown on first insulator; (4) one second insulator grown on floating gate; (5) one control gate grown on second insulator; (6) one third insulator grown on control gate; (7) one select gate grown on third insulator; in which the select gate also includes one select gate extension portion which crosses above P+ source to prevent device from being over programming function, and control gate controls device programming and erasing operation.
Non-voltile memory device, non-volatile memory cell and method of adjusting the threshold value of the non-volatile memory cell and each of plural transistors