TW277119B - Standard DRAM emulator using specialty DRAM - Google Patents

Abstract

A memory module populated with specialty DRAMs which can be used either for a new system designed to take advantage of all the aspects of the specialty DRAMs, or an older system expecting standard DRAM modules is provided. A mode input to the module, which can be a switch on the module, indicates whether it is in a specialty or standard system. When the mode indicates a standard system, signal timing is modified to make the module respond like a standard DRAM module. In particular, in one embodiment, EDO DRAM is used on the memory module and a switch allows it to operate in either EDO mode, or in FPM mode. In FPM mode, a manager circuit controls the OE input of the EDO DRAM to disable the output signal on a CAS transition so that the data output timing matches that expected by a computer system designed for standard FPM DRAM. A parity manager circuit to simulate a parity bit is also provided, with a version of the circuit adapted for synchronous DRAM. Also provided is a voltage converter for converting a system power supply to a different power supply voltage used by the DRAM, either 3.3 volts or some other voltage.