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TW241395B - Fabrication method for multi-level mask ROM - Google Patents

Fabrication method for multi-level mask ROM

Info

Publication number
TW241395B
TW241395B TW83108225A TW83108225A TW241395B TW 241395 B TW241395 B TW 241395B TW 83108225 A TW83108225 A TW 83108225A TW 83108225 A TW83108225 A TW 83108225A TW 241395 B TW241395 B TW 241395B
Authority
TW
Taiwan
Prior art keywords
gate oxide
substrate
transistor channel
forming multiple
extending along
Prior art date
Application number
TW83108225A
Other languages
Chinese (zh)
Inventor
Guann-Cherng Su
Shing-Ren Hsu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW83108225A priority Critical patent/TW241395B/en
Application granted granted Critical
Publication of TW241395B publication Critical patent/TW241395B/en

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Abstract

A multi-level mask ROM which is applicable to one substrate includes: 1. formed multiple heavily doped source/drain on the substrate, and forming multiple bit lines by extending along the first direction; 2. forming multiple gate oxide on the substrate and extending along the second direction which is perpendicular to the first one, and forming transistor channel on the substrate between every two neighbor bit lines under the gate oxide; in which the gate oxide thickness is selected from one series sequences; 3. forming multiple gate electrodes on the gate oxide, and forming multiple bit lines by extending along the second direction; in which the transistor channel, the source/drain connected with the transistor channel, the gate oxide on the transistor channel and the gate transistor forms one memory cell together, by the thickness change of the gate oxide and changing threshold potential to form multi-level storage memory cell.
TW83108225A 1994-09-06 1994-09-06 Fabrication method for multi-level mask ROM TW241395B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW83108225A TW241395B (en) 1994-09-06 1994-09-06 Fabrication method for multi-level mask ROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW83108225A TW241395B (en) 1994-09-06 1994-09-06 Fabrication method for multi-level mask ROM

Publications (1)

Publication Number Publication Date
TW241395B true TW241395B (en) 1995-02-21

Family

ID=51400927

Family Applications (1)

Application Number Title Priority Date Filing Date
TW83108225A TW241395B (en) 1994-09-06 1994-09-06 Fabrication method for multi-level mask ROM

Country Status (1)

Country Link
TW (1) TW241395B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617646A1 (en) * 1996-05-02 1997-11-13 Siemens Ag Memory cell arrangement and method for its production

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617646A1 (en) * 1996-05-02 1997-11-13 Siemens Ag Memory cell arrangement and method for its production
DE19617646C2 (en) * 1996-05-02 1998-07-09 Siemens Ag Memory cell arrangement and a method for the production thereof

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MK4A Expiration of patent term of an invention patent