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TW224543B - Flash memory - Google Patents

Flash memory

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Publication number
TW224543B
TW224543B TW83101499A TW83101499A TW224543B TW 224543 B TW224543 B TW 224543B TW 83101499 A TW83101499 A TW 83101499A TW 83101499 A TW83101499 A TW 83101499A TW 224543 B TW224543 B TW 224543B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric layer
etching
floating gate
polysilicon
Prior art date
Application number
TW83101499A
Other languages
Chinese (zh)
Inventor
Yeun-Ding Horng
Huei-Hwang Chern
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW83101499A priority Critical patent/TW224543B/en
Application granted granted Critical
Publication of TW224543B publication Critical patent/TW224543B/en

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  • Non-Volatile Memory (AREA)

Abstract

One type of manufacturing method for flash memory with split-gateconsists of: 1. providing one silicon substrate with field oxide layer and component area; 2. sequentially forming the tunnel oxide layer, the first polysiliconlayer, the first dielectric layer with ONO structure, the secondpolysilicon layer and one Nitride layer; 3. putting photo-resistance and overlaying the area which is to be formedas floating gate, then sequentially etching the exposed Nitride layer,the second polysilicon layer, the dielectric layer with ONO structureand the first polysilicon layer to form floating gate, then removingthe photo-resistance; 4. forming the second dielectric layer with ONO structure with anisotropicetching to etchback in order to form spacer dielectric layer with ONOstructure on the remaining spacer of the first polysilicon layer, thefirst dielectric layer with ONO structure, the second polysiliconlayer and Nitride layer; 5. etching the exposed tunnel oxide layer out of the floating gate area; 6. forma gate oxide layer; 7. etching the remaining Nitride layer; 8. depositing the third polysilicon layer and molding to word line controlgate; 9. providing appropriate metallurgy to connect the integrated circuit offlash memory needed by component forming.
TW83101499A 1994-02-22 1994-02-22 Flash memory TW224543B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW83101499A TW224543B (en) 1994-02-22 1994-02-22 Flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW83101499A TW224543B (en) 1994-02-22 1994-02-22 Flash memory

Publications (1)

Publication Number Publication Date
TW224543B true TW224543B (en) 1994-06-01

Family

ID=51348265

Family Applications (1)

Application Number Title Priority Date Filing Date
TW83101499A TW224543B (en) 1994-02-22 1994-02-22 Flash memory

Country Status (1)

Country Link
TW (1) TW224543B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796139A (en) * 1995-02-23 1998-08-18 Sanyo Electric Co., Ltd. Semiconductor device
US6214749B1 (en) * 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214749B1 (en) * 1994-09-14 2001-04-10 Sanyo Electric Co., Ltd. Process for producing semiconductor devices
US5796139A (en) * 1995-02-23 1998-08-18 Sanyo Electric Co., Ltd. Semiconductor device
US5989960A (en) * 1995-02-23 1999-11-23 Sanyo Electric Co., Ltd. Semiconductor device and method for fabricating the same

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