TW202539462A - Solar cell and method of manufacturing the same - Google Patents

Abstract

Disclosed is a method of manufacturing a solar cell comprising a step of forming a first semiconductor layer on one surface of the substrate, wherein the step of forming the first semiconductor layer includes a step of forming an amorphous semiconductor layer and a step of repeatedly performing a cycle including a step of crystallizing at least a part of the amorphous semiconductor layer, wherein the step of forming of the amorphous semiconductor layer includes a step of supplying a silicon-containing gas and a first gas, and the step of crystallizing at least the part of the amorphous semiconductor layer includes a step of forming a plasma including a second gas.

Description

Solar cells and their manufacturing methods

This invention relates to a method for forming a solar cell and a method for manufacturing the same.

A solar cell is a device that uses the properties of semiconductors to convert light energy into electrical energy.

A solar cell has a PN junction structure that allows P (positive) semiconductors and N (negative) semiconductors to connect. When sunlight shines on a solar cell with a PN junction structure, holes and electrons are generated in the semiconductors due to the energy of the incident sunlight. In this case, due to the electric field generated in the PN junction, the holes (+) move towards the P-type semiconductor and the electrons (-) move towards the N-type semiconductor, thereby generating electricity.

These solar cells can generally be divided into substrate solar cells and thin-film solar cells.

Substrate-type solar cells are manufactured by using semiconductor materials such as silicon as substrates, and thin-film solar cells are manufactured by forming semiconductors on substrates such as glass in the form of thin films.

Substrate-type solar cells have the advantage of slightly higher efficiency compared to thin-film solar cells, and thin-film solar cells have the advantage of lower manufacturing costs compared to substrate-type solar cells.

Various attempts have been made to achieve high-efficiency solar cells even with thin thicknesses when crystalline semiconductor layers are formed on amorphous semiconductor layers of solar cells.

The present invention is designed to overcome the shortcomings of the aforementioned solar cells and aims to provide a solar cell and a method for manufacturing the same, by repeatedly depositing an amorphous semiconductor layer and plasma treating a portion thereof to crystallize the amorphous semiconductor layer, thereby achieving high efficiency even at a thin thickness.

According to one aspect of the present invention, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, comprising a step of forming a first semiconductor layer on a surface of a substrate, wherein the step of forming the first semiconductor layer includes a step of forming an amorphous semiconductor layer and a step of repeating a cycle comprising a step of crystallizing at least a portion of the amorphous semiconductor layer, wherein the step of forming the amorphous semiconductor layer includes a step of supplying a silicon-containing gas and a first gas, and the step of crystallizing at least a portion of the amorphous semiconductor layer includes a step of forming a plasma comprising a second gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the second gas comprises a gas containing one or more of hydrogen, helium and argon.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, wherein the step of forming an amorphous semiconductor layer further includes a step of forming a plasma containing a first gas, wherein the power used to form the plasma containing the first gas is lower than the power used to form the plasma containing a second gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the first gas comprises a hydrogen-containing gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the step of forming an amorphous semiconductor layer further includes the step of supplying a P-type dopant or an N-type dopant.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, which includes a step of forming a buffer layer before the step of forming the first semiconductor layer, wherein the step of forming the buffer layer includes a step of supplying a silicon-containing gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the step of forming a buffer layer, after the step of supplying silicon-containing gas, further includes a step of forming a plasma containing a fourth gas, wherein the fourth gas comprises a gas combining one or more of hydrogen-containing gas, helium, and argon.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the power used to form a plasma containing a second gas is greater than the power used to form a plasma containing a fourth gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the step of forming a buffer layer further includes a step of forming a plasma containing a third gas, wherein the third gas contains a hydrogen-containing gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the power used to form a plasma containing a fourth gas is lower than the power used to form a plasma containing a third gas.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, which includes, prior to the step of forming a first semiconductor layer, a step of forming a physical semiconductor layer on a surface of a substrate, wherein the substrate is made of a semiconductor substrate.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, wherein the crystallinity on one surface of the first semiconductor layer is different from the crystallinity on the other surface of the first semiconductor layer.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, wherein the crystallization rate on one surface of the first semiconductor layer is higher than the crystallization rate on the other surface of the first semiconductor layer, and one surface of the first semiconductor layer is closer to the substrate than the other surface of the first semiconductor layer.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, which further includes the steps of supplying a first gas from a first gas supply unit to a cavity through a first gas supply pipeline; and the steps of supplying silicon-containing gas from a second gas supply unit to the cavity through a second gas supply pipeline, wherein the first gas supply unit and the second gas supply unit simultaneously supply the first gas and the silicon-containing gas to the cavity.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein a first gas supply line and a second gas supply line each supply gas to the cavity.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein the step of forming an amorphous semiconductor layer further includes the step of forming a plasma containing a first gas, wherein the plasma containing the first gas is formed after the first gas and the silicon-containing gas are supplied.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing solar cells, wherein when the formation of plasma containing the first gas is terminated, the supply of silicon-containing gas is terminated while the supply of the first gas is maintained.

Furthermore, the above and other objectives can be achieved by providing a method for manufacturing a solar cell, wherein, after the formation of a plasma containing a first gas is terminated, a plasma containing a second gas is formed when the step of supplying silicon-containing gas is terminated and the step of supplying the first gas is maintained.

Furthermore, the above and other objectives can be achieved by providing a solar cell, comprising a substrate; and a first semiconductor layer provided on the substrate, wherein the first semiconductor layer is a solar cell formed by a method for manufacturing a solar cell.

Furthermore, the above and other objectives can be achieved by providing a solar cell, and further includes a first buffer layer disposed between the substrate and the first semiconductor layer, wherein the first buffer layer has a thickness of more than 2 Å and less than 5 Å.

The advantages, features, and methods of implementing the present invention will be illustrated by the following embodiments described with reference to the relevant figures. However, the present invention may be implemented in different forms and should not be limited to the embodiments described herein. These embodiments are provided rather than intended to enable a thorough and complete understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is defined only by the scope of the claims.

The shapes, dimensions, proportions, angles, and quantities disclosed in the drawings used to describe embodiments of the invention are merely examples, and therefore the invention is not limited to the details shown. Similar reference numerals throughout represent similar elements. In the following description, detailed descriptions of relevant prior art will be omitted when it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

When using the terms "comprises," "has," and "includes" as described in this manual, an additional component may be added unless "only" is used. Unless otherwise stated, singular forms may contain plural forms.

Although the error is not described in detail when explaining the component, the component should be interpreted as containing such error.

When describing positional relationships, for example, when describing the positional order between two parts using terms such as "above," "on top," "below," "below," and "beside," the situation where they do not touch can be included unless terms such as "directly" or "rightly" are used.

When it is mentioned that the first element is "above" the second element, it does not mean that the first element is substantially above the second element in the drawing. The upper and lower parts of the related object can change depending on the orientation of the object. Therefore, in the drawing or in actual configuration, the case where the first element is "above" the second element includes both the case where the first element is "below" the second element and the case where the first element is "above" the second element.

When describing temporal relationships, for example, when describing the sequence of time using terms such as "after," "following," "next," and "before," discontinuous situations may be included unless terms such as "immediately after" or "directly" are used.

It will be understood that while terms such as "first," "second," etc., can be used to describe various components, these components should not be limited to these terms. These terms are only used to distinguish components. For example, a first component can be named a second component, and similarly, a second component can be named a first component.

It will be understood that the term "at least one" includes all combinations relating to any one of them. For example, "at least one of the first element, the second element, and the third element" may include combinations of two or more first elements, second elements, and third elements, as well as all elements selected from each of the first element, the second element, and the third element.

The features of the various embodiments of the present invention may be partially or wholly coupled or combined with each other, and may interact with each other and be technically driven in various ways. The embodiments of the present invention may be implemented independently of each other, or may be implemented in a commonly related manner.

In a diagram, even if the same or similar elements are drawn in different diagrams, they can still be labeled with the same number.

In the embodiments of the present invention, the source electrode and the drain electrode are distinguished from each other for ease of explanation. However, the source electrode and the drain electrode can be used interchangeably. Therefore, the source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode in any embodiment of the present invention can be the drain electrode in another embodiment of the present invention, and the drain electrode in any embodiment of the present invention can be the source electrode in another embodiment of the present invention.

In one or more embodiments of the present invention, for ease of explanation, the source region is separated from the source electrode, and the drain region is separated from the drain electrode. However, the embodiments of the present invention are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

Figure 1 is a side cross-sectional schematic diagram of a solar cell according to an embodiment of the present invention.

As shown in Figure 1, a solar cell according to an embodiment of the present invention may include a substrate 110, a buffer layer 120, and a first semiconductor layer 130.

The substrate 110 may be formed from a semiconductor wafer, such as a silicon wafer, and specifically, from an N-type silicon wafer or a P-type silicon wafer. As another example, the substrate 110 may be formed from glass or plastic, and in this case, an N-type semiconductor layer or a P-type semiconductor layer may be deposited and used on the substrate 110. Hereinafter, for ease of explanation, the case where the substrate 110 is a semiconductor wafer will be described primarily.

Although not shown, the uneven structure may be formed on at least one of the upper or lower surfaces of the substrate 110. When the uneven structure is formed on the upper and lower surfaces of the substrate 110, the uneven structure may also be formed on the surfaces of the first semiconductor layer 130 and the buffer layer 120.

A buffer layer 120 is formed on the substrate 110. The buffer layer 120 is formed on the substrate 110 to prevent damage to the substrate 110 during the fabrication process of forming the first semiconductor layer 130 on the buffer layer 120.

The buffer layer 120 may comprise an amorphous semiconductor layer. For example, the buffer layer 120 may be formed by depositing an amorphous silicon (Si) layer, or the buffer layer 120 may be formed by depositing an amorphous silicon (Si) thin film layer and performing a plasma treatment on the amorphous silicon (Si) thin film layer in a cycle. In this case, the plasma treatment can be defined as forming a plasma using either hydrogen or a gas containing an inert gas. The method of forming the buffer layer 120 will be described in more detail with reference to Figures 3 and 4.

The first semiconductor layer 130 is formed as a thin film on the upper surface of the substrate 110 formed from a semiconductor wafer. Specifically, the first semiconductor layer 130 is formed as a thin film on the substrate 110 and the buffer layer 120. The first semiconductor layer 130 can form a PN junction together with the substrate 110, and therefore, when the substrate 110 is formed from an N-type silicon wafer, the first semiconductor layer 130 can be formed from a P-type semiconductor layer. In particular, the first semiconductor layer 130 can be formed from P-type silicon doped with a group 3 element such as boron (B). However, the present invention is not limited thereto, and when the substrate 110 is formed from a P-type silicon wafer, the first semiconductor layer 130 can be formed from an N-type semiconductor layer. In this case, the first semiconductor layer 130 can be formed from N-type silicon doped with group 5 elements such as phosphorus (P).

Typically, because the deflection capability of holes is lower than that of electrons, it is preferable to form a P-type semiconductor layer near the light-receiving surface to maximize the collection efficiency of incident light for holes. Therefore, the first semiconductor layer 130 near the light-receiving surface is preferably formed of a P-type semiconductor layer.

According to one embodiment of the present invention, the first semiconductor layer 130 may comprise an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the first semiconductor layer 130 may be formed by depositing an amorphous silicon (Si) thin film layer and plasma treating the amorphous silicon (Si) thin film layer, and then repeating this step in a cycle. By forming the first semiconductor layer 130 described above, multiple crystalline silicon (Si) layers can be formed, thereby ensuring high electrical conductivity. The method for forming the first semiconductor layer 130 will now be described in more detail with reference to Figures 3 and 4.

According to one embodiment of the present invention, the first semiconductor layer 130 may include a surface (e.g., a lower surface) adjacent to the substrate 110 and another surface (e.g., an upper surface) opposite to one surface of the first semiconductor layer 130, and the crystallinity of one surface of the first semiconductor layer 130 may be different from the crystallinity of the other surface of the first semiconductor layer 130. In this case, the crystallinity can be defined as the proportion of crystalline silicon (Si) formed on any virtual surface formed parallel between one surface and the other surface of the first semiconductor layer 130.

Specifically, the crystallinity on one surface of the first semiconductor layer 130 adjacent to the substrate 110 can be formed to be lower than the crystallinity on the other surface of the first semiconductor layer 130, and the crystallinity of the first semiconductor layer 130 can gradually increase from one surface of the first semiconductor layer 130 to the other surface of the first semiconductor layer 130.

Figure 2 is a side cross-sectional view of a solar cell according to another embodiment of the present invention.

As shown in Figure 2, a solar cell according to another embodiment of the present invention includes a substrate 110, a first buffer layer 120a, a second buffer layer 120b, a first semiconductor layer 130a, a second semiconductor layer 130b, a third semiconductor layer 140a, a fourth semiconductor layer 140b, a first transparent conductive layer 200a, a second transparent conductive layer 200b, a first electrode 300a, and a second electrode 300b.

The substrate 110 may be formed from a semiconductor wafer, such as a silicon wafer, and specifically, from an N-type silicon wafer or a P-type silicon wafer. As another example, the substrate 110 may be formed from glass or plastic, and in this case, an N-type semiconductor layer or a P-type semiconductor layer may be deposited and used on the substrate 110. Hereinafter, for ease of explanation, the case where the substrate 110 is a semiconductor wafer will be described primarily.

Although not shown, the uneven structure may be formed on at least one of the upper or lower surfaces of the substrate 110. When the uneven structure is formed on the upper and lower surfaces of the substrate 110, the uneven structure may also be formed on the surfaces of the first buffer layer 120a, the second buffer layer 120b, the first semiconductor layer 130a, the second semiconductor layer 130b, the third semiconductor layer 140a, the fourth semiconductor layer 140b, the first transparent conductive layer 200a, and the second transparent conductive layer 200b.

In another embodiment of the invention illustrated in FIG2, a third semiconductor layer 140a is formed on the upper surface of the substrate 110, and then a first buffer layer 120a and a first semiconductor layer 130a are formed on the third semiconductor layer 140a to prevent defects from occurring on the upper surface of the substrate 110.

The third semiconductor layer 140a may be formed from an intrinsic semiconductor layer, or the third semiconductor layer 140a may be a semiconductor layer with a lower doping concentration than the first semiconductor layer 130a.

For example, the third semiconductor layer 140a can be formed from an intrinsic semiconductor layer.

Because the third semiconductor layer 140a is formed from the intrinsic semiconductor layer, defects may not occur on the upper surface of the substrate 110 during the process of forming the first semiconductor layer 130a on the substrate 110.

In another example, the third semiconductor layer 140a may be a semiconductor layer with a relatively low doping concentration compared to the first semiconductor layer 130a.

The dopants doped into the third semiconductor layer 140a can be of the same type as the dopants doped into the first semiconductor layer 130a, such as the same P-type.

Because the third semiconductor layer 140a is formed between the substrate 110 and the first semiconductor layer 130a, defects can be prevented from occurring on the upper surface of the substrate 110.

In this case, it is preferable to adjust the doping concentration of the low-doped third semiconductor layer 140a so that no defects occur on the surface of the substrate 110.

When the impurity concentration of the third semiconductor layer 140a is relatively lower than that of the first semiconductor layer 130a, the first semiconductor layer 130a and the third semiconductor layer 140a can be fabricated in a continuous process in one cavity. Therefore, no separate deposition equipment or process is required, and the solar cell of the present invention has excellent manufacturability.

A first buffer layer 120a is formed on the substrate 110. Specifically, the first buffer layer 120a is formed on the third semiconductor layer 140a. The first buffer layer 120a is formed on the third semiconductor layer 140a to prevent the third semiconductor layer 140a from being damaged during the process of forming the first semiconductor layer 130a on the first buffer layer 120a. More specifically, the first buffer layer 120a can prevent the third semiconductor layer 140a from partially crystallizing during the process of forming the first semiconductor layer 130a.

The first buffer layer 120a may comprise an amorphous semiconductor layer. For example, the first buffer layer 120a may be formed by depositing an amorphous silicon (Si) layer, or the first buffer layer 120a may be formed by depositing an amorphous silicon (Si) thin film layer and plasma treating the amorphous silicon (Si) thin film layer, and then repeating this step in a cycle.

The first buffer layer 120a may be formed with a thickness of 2 Å or more and 20 Å or less. Preferably, the first buffer layer 120a may be formed with a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer 120a may be formed with a thickness of 2 Å or more and 5 Å or less. When the first buffer layer 120a is formed with a thickness of less than 2 Å, the substrate 110 and the third semiconductor layer 140a may be damaged during the plasma processing of the first semiconductor layer 130a.

A first semiconductor layer 130a is formed in the form of a thin film on the upper surface of a substrate 110 formed from a semiconductor wafer. Specifically, the first semiconductor layer 130a is formed in the form of a thin film on the substrate 110 and the first buffer layer 120a. The first semiconductor layer 130a can form a PN junction together with the substrate 110, and therefore, when the substrate 110 is formed from an N-type silicon wafer, the first semiconductor layer 130a can be formed from a P-type semiconductor layer. In particular, the first semiconductor layer 130a can be formed from P-type silicon doped with a group 3 element such as boron (B).

Typically, because the deflection capability of holes is lower than that of electrons, it is preferable to form a P-type semiconductor layer near the light-receiving surface to maximize the collection efficiency of incident light for holes. Therefore, the first semiconductor layer 130a near the light-receiving surface is preferably formed of a P-type semiconductor layer.

According to one embodiment of the present invention, the first semiconductor layer 130a may comprise an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the first semiconductor layer 130a may be formed by depositing an amorphous silicon (Si) thin film layer and performing plasma treatment on the amorphous silicon (Si) thin film layer, and then repeating this step in a cycle. By forming the first semiconductor layer 130a in this manner, multiple crystalline silicon (Si) layers can be formed, thereby ensuring high electrical conductivity. The method for forming the first semiconductor layer 130a will now be described in more detail with reference to Figures 3 and 4.

According to one embodiment of the present invention, the first semiconductor layer 130a may include a surface (e.g., a lower surface) adjacent to a third semiconductor layer 140a formed from the intrinsic semiconductor layer and another surface (e.g., an upper surface) opposite to a surface of the first semiconductor layer 130a, and the crystallinity of one surface of the first semiconductor layer 130a may be different from the crystallinity of the other surface of the first semiconductor layer 130a. In this case, the crystallinity can be defined as the proportion of crystalline silicon (Si) formed on any virtual surface formed parallel between one surface and the other surface of the first semiconductor layer 130a.

Specifically, the crystallinity on one surface of the first semiconductor layer 130a adjacent to the third semiconductor layer 140a formed by the intrinsic semiconductor layer can be formed to be lower than the crystallinity on the other surface of the first semiconductor layer 130a, and the crystallinity of the first semiconductor layer 130a can gradually increase from one surface of the first semiconductor layer 130a to the other surface of the first semiconductor layer 130a.

A first transparent conductive layer 200a is provided on the upper surface of the first semiconductor layer 130a.

A first transparent conductive layer 200a is formed in the form of a thin film on the upper surface of the first semiconductor layer 130a. The first transparent conductive layer 200a collects carriers generated in the substrate 110, such as holes, and moves the collected carriers to the first electrode 300a.

The first transparent conductive layer 200a may be formed from a transparent conductive material such as indium tin oxide (ITO), ZnOH, ZnO:B, ZnO:Al, SnO ₂ , SnO ₂ :F, etc., and ITO may be selected from the above materials.

The first transparent conductive layer 200a can be formed by sputtering or chemical vapor deposition (CVD) processes.

A first electrode 300a is formed on a first transparent conductive layer 200a to form the front surface of a solar cell. Therefore, the first electrode 300a is patterned into a predetermined shape so that sunlight can be transmitted into the solar cell.

The first electrode 300a can be made of any metal selected from the group consisting of Ag, Cu, Al, Mo and W. At the same time, the first electrode 300a is not limited to this and can be formed into more than one multilayer structure.

In another embodiment of the invention illustrated in FIG2, a fourth semiconductor layer 140b is formed on the lower surface of the substrate 110, and then a second semiconductor layer 130b is formed on the second buffer layer 120b and the fourth semiconductor layer 140b to prevent defects from occurring on the lower surface of the substrate 110. Meanwhile, although FIG2 illustrates a configuration with both a third semiconductor layer 140a and a fourth semiconductor layer 140b formed, only one of the third semiconductor layer 140a and the fourth semiconductor layer 140b may be formed.

Each of the plurality of fourth semiconductor layers 140b may be formed from an intrinsic semiconductor layer, or each of the plurality of fourth semiconductor layers 140b may be a semiconductor layer having a lower doping concentration than the second semiconductor layer 130b.

For example, the fourth semiconductor layer 140b can be formed from an intrinsic semiconductor layer.

Because the fourth semiconductor layer 140b is formed from an intrinsic semiconductor layer, defects may not occur on the lower surface of the substrate 110 during the process of forming the second semiconductor layer 130b on the substrate 110.

In another example, the fourth semiconductor layer 140b may be a semiconductor layer with a relatively low doping concentration compared to the second semiconductor layer 130b.

The dopants doped into the fourth semiconductor layer 140b and the dopants doped into the second semiconductor layer 130b can be of the same type, such as the same N-type.

Because the fourth semiconductor layer 140b is formed between the substrate 110 and the second semiconductor layer 130b, defects can be prevented from occurring on the lower surface of the substrate 110.

In this case, it is preferable to adjust the doping concentration of the low-doped fourth semiconductor layer 140b so that no defects occur on the surface of the substrate 110.

When the impurity concentration of the fourth semiconductor layer 140b is relatively lower than that of the second semiconductor layer 130b, the second semiconductor layer 130b and the fourth semiconductor layer 140b can be fabricated in a continuous process within a single cavity. Therefore, no separate deposition equipment or process is required, and the solar cell of the present invention has excellent manufacturability.

A second buffer layer 120b is formed on the substrate 110. Specifically, the second buffer layer 120b is formed on the fourth semiconductor layer 140b. The second buffer layer 120b is formed on the fourth semiconductor layer 140b to prevent the fourth semiconductor layer 140b from being damaged during the fabrication process of forming the second semiconductor layer 130b on the second buffer layer 120b. More specifically, the second buffer layer 120b can prevent the fourth semiconductor layer 140b from partially crystallizing during the fabrication process of forming the second semiconductor layer 130b.

The second buffer layer 120b may comprise an amorphous semiconductor layer. For example, the second buffer layer 120b may be formed by depositing an amorphous silicon (Si) layer, or the second buffer layer 120b may be formed by depositing an amorphous silicon (Si) thin film layer and plasma treating the amorphous silicon (Si) thin film layer, and then repeating this step in a cycle. The method for forming the second buffer layer 120b will be described in more detail with reference to Figures 3 and 4.

The second buffer layer 120b may be formed with a thickness of 2 Å or more and 20 Å or less. Preferably, the second buffer layer 120b may be formed with a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer 120a may be formed with a thickness of 2 Å or more and 5 Å or less. When the second buffer layer 120b is formed with a thickness of less than 2 Å, the substrate 110 and the fourth semiconductor layer 140a may be damaged during the plasma processing of the second semiconductor layer 130b.

The second semiconductor layer 130b is formed in the form of a thin film on the lower surface of the substrate 110 on which the semiconductor wafer is formed. The second semiconductor layer 130b is formed with a polarity different from that of the first semiconductor layer 130a, and when the first semiconductor layer 130a is formed by a P-type semiconductor layer doped with a group 3 element such as boron (B), the second semiconductor layer 130b is formed by an N-type semiconductor layer doped with a group 5 element such as phosphorus (P). In particular, the second semiconductor layer 130b may be formed of N-type amorphous silicon.

According to one embodiment of the present invention, the second semiconductor layer 130b may comprise an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the second semiconductor layer 130b may be formed by depositing an amorphous silicon (Si) thin film layer and performing plasma treatment on the amorphous silicon (Si) thin film layer, and then repeating this step in a cycle. By forming the above-described second semiconductor layer 130b, multiple crystalline silicon (Si) layers can be formed, thereby ensuring high electrical conductivity. The method for forming the second semiconductor layer 130b will now be described in more detail with reference to Figures 3 and 4.

According to one embodiment of the present invention, the second semiconductor layer 130b may include a surface (e.g., an upper surface) adjacent to a fourth semiconductor layer 140b formed from the intrinsic semiconductor layer and another surface (e.g., a lower surface) opposite to one surface of the second semiconductor layer 130b, and the crystallinity of one surface of the second semiconductor layer 130b may be different from the crystallinity of the other surface of the second semiconductor layer 130b. In this case, the crystallinity can be defined as the proportion of crystalline silicon (Si) formed on any virtual surface formed parallel between one surface and the other surface of the second semiconductor layer 130b.

Specifically, the crystallinity on one surface of the second semiconductor layer 130b adjacent to the fourth semiconductor layer 140b formed by the intrinsic semiconductor layer can be formed to be lower than the crystallinity on the other surface of the second semiconductor layer 130b, and the crystallinity of the second semiconductor layer 130b can gradually increase from one surface of the second semiconductor layer 130b to the other surface of the second semiconductor layer 130b.

The second transparent conductive layer 200b is formed in the form of a thin film on the lower surface of the second semiconductor layer 130b. The second transparent conductive layer 200b collects carriers, such as electrons, generated in the substrate 110 and moves the collected carriers to the second electrode 300b.

The second transparent conductive layer 200b can be formed from transparent conductive materials such as indium tin oxide (ITO), ZnOH, ZnO:B, ZnO:Al, SnO ₂ , SnO ₂ :F, etc., and ITO can be selected from the above materials.

The second transparent conductive layer 200b can be formed by sputtering or chemical vapor deposition (CVD) processes.

The second electrode 300b is formed on the lower surface of the second transparent conductive layer 200b. Since the second electrode 300b is formed on the rear surface of the solar cell, the second electrode 300b can be formed on the entire lower surface of the second transparent conductive layer 200b. However, in order to allow reflected sunlight to pass through the rear surface of the solar cell, a pattern can be formed as shown in the figure.

The second electrode 300b is patterned on the lower surface of the second transparent conductive layer 200b. The second electrode 300b can be made of any metal selected from the group consisting of Ag, Cu, Al, Mo and W. At the same time, the second electrode 300b is not limited to this and can be formed into more than one multilayer structure.

Figure 3 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention. In this case, the embodiment of Figure 3 relates to a method for manufacturing the first buffer layer (or second buffer layer) and the first semiconductor layer (or second semiconductor layer) of Figure 2.

As shown in Figure 3, a method for manufacturing a solar cell according to an embodiment of the present invention may include the steps of forming a buffer layer and forming a first semiconductor layer (or a second semiconductor layer).

The steps for forming the buffer layer may include a first deposition process S11 and a second plasma treatment process S12.

First, a first deposition process S11 can be performed. In this case, the first deposition process S11 may include a step S111 of supplying silicon (Si) gas and a step S112 of forming a first plasma containing the first gas.

After the first deposition process S11, a semiconductor layer containing amorphous silicon (Si) can be formed on the substrate (see 110 in Figures 1 and 2).

First, the first deposition process S11 can be used to perform the steps of supplying silicon (Si) gas (S111) and forming a first plasma containing the first gas (S112). For example, when the first deposition process S11 is performed using plasma-enhanced chemical vapor deposition (PECVD), the steps of supplying silicon (Si) gas (S111) and forming a first plasma containing the first gas (S112) can be performed simultaneously. However, the invention is not limited thereto.

According to one embodiment of the present invention, the silicon (Si) gas may contain silane ( _SiH4 ), and the first gas may contain hydrogen ( _H2 ), but is not limited thereto.

Next, a second plasma processing step S12 can be performed. The second plasma processing step S12 may include a step of forming a second plasma containing a second gas. In this case, the second gas may contain either a hydrogen-containing gas ( _H₂ ) or an inert gas, or a combination of the above gases. For example, when the second gas contains an inert gas, the second gas may be helium (He) or argon (Ar), but is not limited thereto.

By performing the second plasma treatment process S12, a partially crystallized seed layer can be formed on the upper surface of the buffer layer (refer to 120 in Figure 1, 120a in Figure 2, and 120b in Figure 2), for example, adjacent to the surface of the first semiconductor layer (refer to 130 in Figure 1 and 130a in Figure 2) or the second semiconductor layer (refer to 130b in Figure 2). By forming the seed layer, the crystal can grow at high speed during the process of forming the first semiconductor layer (or the second semiconductor layer).

In the step of forming a second plasma containing a second gas in the second plasma processing step S12, the power used to form the second plasma may be lower than the power used to form the first plasma in the step S112 of forming a first plasma containing a first gas. For example, a power of 2.0 kW or less may be applied to form the second plasma, but this is not a limitation.

By repeating the first deposition process S11 and the second plasma treatment process S12 in a single cycle, a buffer layer (refer to 120a and 120b in Figure 1 or 120b in Figure 2) can be formed. In this case, by performing a cycle including the first deposition process S11 and the second plasma treatment process S12 multiple times, the thickness of the buffer layer (refer to 120a and 120b in Figure 1 and 120b in Figure 2) can be formed, for example, to a thickness of 2 Å or more and 20 Å or less. Preferably, the buffer layer (refer to 120a and 120b in Figure 1 and 120b in Figure 2) can be formed to a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (refer to 120a and 120b in Figure 1 and 120b in Figure 2) can be formed to have a thickness of more than 2 Å and less than 5 Å.

The step of forming the first semiconductor layer (or the second semiconductor layer) can be performed after the step of forming the buffer layer. Therefore, the step of forming the first semiconductor layer (or the second semiconductor layer) can be performed on the buffer layer 120 (see 120a or 120b in FIG. 1 or FIG. 2) formed by performing the step of forming the buffer layer.

The step of forming the first semiconductor layer (or the second semiconductor layer) may include a second deposition process S21 and a fourth plasma treatment process S22.

First, a second deposition process S21 can be performed. In this case, the second deposition process S21 may include a step S211 of supplying silicon (Si) gas and a step S212 of forming a third plasma containing a third gas.

After the second deposition process S21, a semiconductor layer containing amorphous silicon (Si) can be formed on the buffer layer 120 (see 120a in Figure 1 and 120b in Figure 2).

First, the second deposition process S21 can be used to perform the steps S211 of supplying silicon (Si) gas and S212 of forming a third plasma containing a third gas. For example, when the second deposition process S21 is performed using plasma-enhanced chemical vapor deposition (PECVD), the steps S211 of supplying silicon (Si) gas and S212 of forming a third plasma containing a third gas can be performed simultaneously. However, the invention is not limited thereto.

According to one embodiment of the present invention, the silicon (Si) gas may contain silane ( _SiH4 ), and the third gas may contain hydrogen ( _H2 ), but is not limited thereto.

In step S212, which forms a third plasma containing a third gas, the power used to form the third plasma can be the same as the power used to form the first plasma in step S112, which forms a first plasma containing a first gas. In this case, the amorphous semiconductor layer or buffer layer of the first semiconductor layer (or the second semiconductor layer) can be formed in the same cavity through the same process.

Next, a fourth plasma processing step S22 can be performed. The fourth plasma processing step S22 may include a step of forming a fourth plasma containing a fourth gas. In this case, the fourth gas may contain either a hydrogen-containing gas ( _H₂ ) or an inert gas, or a combination of the above gases. For example, when the fourth gas contains an inert gas, the fourth gas may be helium (He) or argon (Ar), but is not limited to these.

In the step of forming the fourth plasma containing the fourth gas in the fourth plasma processing step S22, the power used to form the fourth plasma may be lower than the power used to form the third plasma in step S212, which contains the third gas. For example, a power of 7.0 kW or more may be applied to form the third plasma, but this is not a limitation.

By repeating the second deposition process S21 and the fourth plasma treatment process S22 in one cycle, a first semiconductor layer 130 (refer to 130 in FIG. 1 or 130a in FIG. 2) or a second semiconductor layer (refer to 130b in FIG. 2) can be formed. According to an embodiment of the present invention, by continuously performing one cycle of each of the second deposition process S21 and the fourth plasma treatment process S22, a first semiconductor layer (refer to 130a in FIG. 2) or a second semiconductor layer (refer to 130b in FIG. 2) with high crystallinity even with a thin thickness can be formed.

Furthermore, according to one embodiment of the present invention, the power intensity used to form the fourth plasma in the step of forming the fourth plasma containing the fourth gas in the fourth plasma processing process S22 may be higher than the power intensity used to form the second plasma in the step of forming the second plasma containing the second gas in the second plasma processing process S12.

By forming it in this way, damage to the substrate (refer to 110 in Figures 1 and 2), the third semiconductor layer (refer to 140a in Figure 2), or the fourth semiconductor layer (refer to 140b in Figure 2) from the second plasma formed in the second plasma processing step S12 of the buffer layer formation step can be prevented. Furthermore, in the step of forming the first semiconductor layer, a portion of the amorphous semiconductor layer formed in the second deposition process S21 crystallizes, thereby improving conductivity and realizing a high-efficiency solar cell. Moreover, a high-efficiency solar cell can still be realized even when using a relatively small amount of gas.

Figure 4 is a flowchart of a method for manufacturing a solar cell according to another embodiment of the present invention. The embodiment of Figure 4 relates to a method for manufacturing the first buffer layer (or second buffer layer) and the first semiconductor layer (or second semiconductor layer) of Figure 2. Meanwhile, except for the method of forming the first buffer layer (or second buffer layer), the embodiment of Figure 4 is the same as the embodiment of Figure 3, and therefore, the different configurations will be mainly described below.

As shown in Figure 4, a method for manufacturing a solar cell according to an embodiment of the present invention may include the steps of forming a buffer layer and forming a first semiconductor layer (or a second semiconductor layer).

The step of forming the buffer layer may include a third deposition process S31. In this case, unlike the embodiment in Figure 3, the embodiment in Figure 4 may not require a separate plasma treatment process. In this case, according to the embodiment in Figure 4, no additional process is performed, thereby shortening the process time.

First, a third deposition process S31 can be performed. In this case, the third deposition process S31 may include a step S311 of supplying silicon (Si) gas and a step S312 of forming a first plasma containing the first gas.

After the third deposition process S31, a semiconductor layer containing amorphous silicon (Si) can be formed on the substrate (see 110 in Figures 1 and 2).

First, the steps of supplying silicon (Si) gas (S311) and forming a first plasma containing the first gas (S312) can be performed using the third deposition process (S31). For example, when the third deposition process (S31) is performed using plasma-enhanced chemical vapor deposition (PECVD), the steps of supplying silicon (Si) gas (S311) and forming a first plasma containing the first gas (S312) can be performed simultaneously. However, the invention is not limited thereto.

According to one embodiment of the present invention, the silicon (Si) gas may contain silane ( _SiH4 ), and the first gas may contain hydrogen ( _H2 ), but is not limited thereto.

By repeating the third deposition process S31, a buffer layer (refer to 120 in Figure 1 or 120a and 120b in Figure 2) can be formed. In this case, by performing one cycle including the third deposition process S31 multiple times, the thickness of the buffer layer (refer to 120 in Figure 1 or 120a and 120b in Figure 2) can be formed, for example, to a thickness of 2 Å or more and 20 Å or less. Preferably, the buffer layer (refer to 120 in Figure 1 or 120a and 120b in Figure 2) can be formed to a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (refer to 120 in Figure 1 or 120a and 120b in Figure 2) can be formed to a thickness of 2 Å or more and 5 Å or less.

Figure 5 is a graph illustrating the time-varying supply of silicon (Si) gas, hydrogen ( _H2 ) gas, and plasma power for forming a first semiconductor layer (or a second semiconductor layer) in a method for manufacturing a solar cell according to an embodiment of the present invention.

As shown in Figure 5, for example, in the second deposition process (see S21 in Figure 3 or Figure 4) used to form the first semiconductor layer (or the second semiconductor layer), when the deposition process is performed, silicon (Si) gas and hydrogen ( _H2 ) gas can be supplied first, and then the plasma power supply used for the deposition process can be driven to form the third plasma (see S21 in Figure 3 or Figure 4).

For example, in the second plasma processing step (see S22 in Figure 3 or Figure 4) used to form the first semiconductor layer (or the second semiconductor layer), the supply of silicon (Si) gas can be stopped during the plasma processing, but the supply of hydrogen ( _H2 ) gas can be maintained. In this case, the plasma power supply can be left undriven to stop the formation of the third plasma.

Next, the plasma power supply can be driven again to form a fourth plasma (see S22 in Figure 3 or Figure 4). In this case, the power of the plasma power supply used to form the third plasma may be different from the power of the plasma power supply used to form the fourth plasma.

Figure 6 is a cross-sectional view of a substrate processing apparatus for manufacturing solar cells according to an embodiment of the present invention.

As shown in Figure 6, a substrate processing apparatus for manufacturing solar cells according to an embodiment of the present invention includes a cavity 40, a substrate support device 50, a gas supply device 600, and a power supply device 400. The substrate support device 50 is installed inside the cavity 40 to support the substrate S provided inside the cavity 40. The gas supply device 600 is installed inside the cavity 40 to supply gas to the substrate support device 50. The power supply device 400 is connected to the gas supply device 600 to supply power for plasma generation to the cavity 40. Furthermore, a substrate processing apparatus according to another embodiment may further include a control device (not shown). The control device (not shown) controls the power supply device 400.

The cavity 40 provides a predetermined reaction space and keeps it airtight. The cavity 40 may include a body 44 having a predetermined reaction space comprising a flat portion that is substantially circular or rectangular and sidewall portions extending upward from the flat portion, and a cover 42 positioned on the body 44 in a generally circular or rectangular shape to keep the reaction space airtight. However, the cavity 40 is not limited thereto and can be manufactured in various shapes corresponding to the shape of the substrate S.

A discharge port (not shown) may be formed in a predetermined area on the lower surface of the cavity 40, and a discharge pipe (not shown) connected to the discharge port may be provided outside the cavity 40. Furthermore, the discharge pipe may be connected to a discharge device (not shown). For example, a vacuum pump such as a turbomolecular pump may be used as a discharge device. Thus, for example, the interior of the cavity 40 may be evacuated to a predetermined pressure below 0.1 mTorr under a predetermined reduced-pressure atmosphere by the discharge device. The discharge pipe may be installed not only on the lower surface of the cavity 40, but also on the side surface of the cavity 40 below the substrate support device 50, as will be described later. Furthermore, multiple discharge pipes and corresponding discharge devices may be installed to reduce discharge time.

Meanwhile, the substrate S provided to the cavity 40 can be mounted on the substrate support device 50 for substrate processing, such as thin film deposition. For example, the substrate support device 50 can be provided with electrostatic chucks or the like to attract and hold the substrate S by electrostatic force to set and support the substrate S, or it can support the substrate S by vacuum adsorption or mechanical force.

The substrate support device 50 may have a shape corresponding to the shape of the substrate S, such as circular or quadrilateral. The substrate support device 50 may include a substrate support member 52 on which the substrate S is disposed, and a lifting member 54 disposed below the substrate support member 52 to move the substrate support member 52 up and down. Here, the substrate support member 52 may be made larger than the substrate S, and the lifting member 54 may be provided to support at least one area of the substrate support member 52, such as its center, and when the substrate S is disposed on the substrate support member 52, the substrate support member 52 may be moved to approach the gas supply device 600. Furthermore, a heater (not shown) may be installed inside the substrate support member 52. The heater heats the substrate support 52 and the substrate S disposed on the substrate support 52 so that the thin film is uniformly deposited on the substrate S.

A gas supply device may be installed on the cover 42 of the cavity 40. The gas supply device may be installed to penetrate the cover 42 of the cavity 40 and may include a first gas supply unit 410 and a second gas supply unit 420 to supply the first gas and the second gas to the gas supply device 600, respectively. Here, the first gas may contain a raw material gas, and the second gas may contain a reaction gas. However, the invention is not limited thereto, and the first gas may contain a reaction gas, the second gas may contain a raw material gas, or at least one of the first and second gases may contain a mixed gas containing both the raw material gas and the reaction gas. Furthermore, it goes without saying that at least one of the first and second gases may be a purging gas. That is, each of the first gas supply unit 410 and the second gas supply unit 420 does not necessarily supply a single gas, and each of the first gas supply unit 410 and the second gas supply unit 420 can be used to supply multiple gases simultaneously or to supply a gas selected from multiple gases.

A gas supply device 600 is installed inside the cavity 40 (e.g., on the lower surface of the cover 42), and is installed inside the gas supply device 600, the first gas supply path for supplying a first gas to the substrate, and the second gas supply path for supplying a second gas to the substrate. The first gas supply path and the second gas supply path are provided to be independently separated from each other so that the first gas and the second gas can be supplied to the substrate independently in the gas supply device 600 without mixing.

More specifically, the gas supply device 600 includes a first plate and a second plate 630. The first plate includes a first gas supply port 612 connected to a first gas supply path and a second gas supply port 614 connected to a second gas supply path, and the first gas supply path and the second gas supply path are provided to be independently separated from each other. The second plate 630 may be spaced apart from the first plate and may have a plurality of openings 632 configured to intersect with the first gas supply port 612 and the second gas supply port 614.

The first plate may include an upper frame 610 and a lower frame 620. The upper frame 610 is separately coupled to the lower surface of the cover 42, and a portion of the upper surface (e.g., the center of the upper surface) is spaced apart from the lower surface of the cover 42 by a predetermined distance. Therefore, a first gas supplied from the first gas supply unit 410 can diffuse in the space between the upper surface of the upper frame 610 and the lower surface of the cover 42. Furthermore, the lower frame 620 is mounted spaced apart from the lower surface of the upper frame 610 by a predetermined distance. Therefore, a second gas supplied from the second gas supply unit 420 can diffuse in the space between the upper surface of the lower frame 620 and the lower surface of the upper frame 610. The upper frame 610 and the lower frame 620 may be connected to each other along their outer peripheral surfaces to form an integral structure to provide a space therein, and may be configured such that the outer peripheral surfaces are sealed by a first seal 650. In this case, the first seal 650 may be formed of an insulating material to electrically insulate the upper frame 610 and the lower frame 620 from each other, or conversely, the first seal 650 may be formed of a conductive material to electrically connect the upper frame 610 and the lower frame 620 from each other.

A first gas supply path can be formed, such that the first gas supplied from the first gas supply unit 410 diffuses in the space between the upper frame 610 and the lower surface of the cover 42, and is supplied to the cavity 40 through the upper frame 610 and the lower frame 620. In this case, the first gas supply port 612 can be formed by connecting to the first gas supply path, and can be formed through the upper frame 610 and the lower frame 620, so as to be separated from the space between the upper surface of the lower frame 620 and the lower surface of the upper frame 610 in the bottom of the space between the upper surface of the upper frame 610 and the lower surface of the cover 42.

Furthermore, a second gas supply path can be formed, allowing the second gas supplied from the second gas supply unit 420 to diffuse in the space between the lower surface of the upper frame 610 and the upper surface of the lower frame 620, so as to be supplied to the cavity 40. In this case, the second gas supply port 622 can be formed by connecting to the second gas supply path, and can be formed through the lower frame 620 at the bottom of the space between the multiple lower surfaces of the upper frame 610.

Therefore, the first gas supply path and the second gas supply path may not be interconnected, and the first gas and the second gas may be independently supplied downward from the gas supply unit through the first plate.

The second plate 630 can be mounted spaced from the lower side of the lower frame 620. That is, the second plate 630 is mounted at a predetermined distance D1 from the lower surface of the lower frame 620. Therefore, the first gas and the second gas supplied to the lower side through the first plate can diffuse in the space between the upper surface of the second plate 630 and the lower surface of the lower frame 620. The lower frame 620 and the second plate 630 can be connected to each other along their outer peripheral surfaces to form a single integral shape to provide a space therein, but may have a structure in which the outer peripheral surfaces are sealed by the second seal 660. In this case, the second seal 660 can be formed of an insulating material to electrically insulate the lower frame 620 and the second plate 630 from each other, or conversely, the second seal 660 can be formed of a conductive material to electrically connect the lower frame 620 to the second plate 630.

Here, the second plate 630 can be mounted such that the plasma sheath region that can be formed on the surface of the first plate (i.e., the lower surface of the lower frame 620) and the plasma sheath region that can be formed on the surface of the second plate 630 (i.e., the upper surface of the second plate 630) are separated from the lower side of the first plate by an overlapping distance. Here, the plasma sheath region refers to the dark field region where positive (+) ions are concentrated between the plasma and the surface of the structure to exchange energy but hardly generate plasma.

If the plasma sheath region that can be formed on the lower surface of the lower frame 620 and the plasma sheath region that can be formed on the upper surface of the second plate 630 do not overlap, plasma can be formed between the plasma sheath regions. However, in the embodiments of the present invention, the plasma sheath region that can be formed on the lower surface of the lower frame 620 and the plasma sheath region that can be formed on the upper surface of the second plate 630 are separated from each other by the distance between the overlapping plasma sheath regions that can be formed on the lower surface of the lower frame 620 and the upper surface of the second plate 630, thereby preventing the generation of plasma.

Furthermore, the second plate 630 has multiple openings 632 arranged to intersect with the first gas supply port 612 and the second gas supply port 622. That is, when viewed from above or below, these openings 632 can be formed in the second plate 630 so as not to overlap with either the first gas supply port 612 or the second gas supply port 622. When viewed from above or below, these openings 632 can be formed in at least one direction between the first gas supply port 612 and the second gas supply port 622. Furthermore, these openings 632 can be formed in at least one direction in the central portion between the first gas supply port 612 and the second gas supply port 622. When these openings 632 are configured to intersect with the first gas supply port 612 and the second gas supply port 614, particles may not be formed when the gas supplied from the first gas supply port 612 and the second gas supply port 622 flows uniformly and continuously to form plasma.

Each of these openings 632 may include a first opening formed on one side of the first plate and a second opening connected to the first opening and having a larger diameter than the first opening. That is, each of these openings 632 may include a first opening formed having a predetermined length from the upper surface of the second plate 630 and a second opening formed having a predetermined length from the lower surface of the second plate 630. In this case, the first opening is a gas inlet, and gas diffused in the space between the lower surface of the lower frame 620 and the upper surface of the second plate 630 flows through the first opening into the opening 632. On the other hand, the second opening is a gas outlet, and gas introduced into the opening 632 is supplied to the lower side of the second plate 630 through the second opening. The first opening may be configured to intersect with the first gas supply port 612 and the second gas supply port 622, and the second opening may be formed to extend to the lower side of the first opening to have a larger diameter than the first opening.

Meanwhile, Figure 6 only shows that the opening 632 is configured to intersect with the first gas supply port 612 and the second gas supply port 622, but the substrate processing apparatus according to one embodiment of the present invention is not limited thereto. As another example, in the substrate processing apparatus according to another embodiment of the present invention, the opening 632 may be formed to overlap the first gas supply port 612 and the second gas supply port 622 without intersecting each other. In this case, multiple protrusions may be coupled to the first plate, such that the protrusions may protrude from the lower surface of the first plate 630 to the second plate 630. At least one of the first gas supply port 612 and the second gas supply port 622 may be formed by the protrusions. Furthermore, these protrusions may be configured to correspond to the opening 632, and these protrusions may be formed to have a length that inserts into the opening 632, or to have a length that protrudes to the underside of the second plate 630, but are not limited thereto.

The power supply device 400 can be connected to the gas supply device 600 to supply power for generating plasma in the cavity 40. That is, the power supply device 400 can supply RF power for generating plasma to the cavity 40.

Here, the power supply device 400 can be connected to the second board 630 to supply RF power only to the second board 630, while the first board can be grounded. In this case, the first board and the second board 630 can be insulated from each other by a second seal 660 formed of insulating material. Therefore, when the power supply device 400 supplies RF power to the second board 630 and the first board is grounded, the first board and the second board 630 will respectively form electrodes for generating capacitively coupled plasma (CCP). In addition, the substrate support 52 is also grounded, and capacitively coupled plasma can be generated between the second board 630 and the substrate support 52.

In contrast, the power supply device 400 can also supply power to both the first board and the second board 630. In this case, the second seal 660 can be formed of a conductive material to allow the power supply device 400 to supply RF power to either the first board or the second board 630, or the power supply device 400 can supply RF power to both the first board and the second board 630 respectively. In this case, the same RF power can be supplied to both the first board and the second board 630. Therefore, compared to the case where the first board is grounded, when the power supply device 400 supplies the same RF power to both the first board and the second board 630, the plasma sheath area formed between the first board and the second board 630 is reduced. Therefore, a relatively high density of capacitively coupled plasma can be generated between the substrate support members 52 to be grounded.

In another example of the invention, for instance, as described above, when multiple protrusions are coupled to the first plate and these protrusions protrude from the lower surface of the first plate toward the second plate 630, these protrusions may function as protruding electrodes when the power supply device 400 supplies RF power to the first plate.

Meanwhile, Figure 6 only illustrates an embodiment that includes a first gas supply unit 410 and a second gas supply unit 420, totaling two gas supply units and having two or more diffusion spaces, but the substrate processing apparatus according to one embodiment of the present invention is not limited thereto. As another example, the substrate processing apparatus according to another embodiment of the present invention may include a gas supply unit and a diffusion space, and multiple gases may be stored and mixed from the outside through separate spaces and introduced into the cavity 40 through the gas supply unit, and the gas flowing into the cavity 40 may flow through a diffusion space and be supplied to the substrate S.

Using the substrate processing apparatus of this invention, thin films can be deposited on substrate S by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

First, when the thin film is deposited on the substrate S by chemical vapor deposition (CVD), a source gas and a reaction gas can be simultaneously supplied to the substrate S. In this case, the first gas may contain the source gas, and the second gas may contain the reaction gas. However, the invention is not limited thereto, and the first gas may contain the reaction gas, the second gas may contain the source gas, or at least one of the first and second gases may contain a mixture of the source gas and the reaction gas. Furthermore, at least one of the first and second gases may also be a purging gas. In this case, by supplying RF power to the gas supply device 600 through the power supply device 400, plasma can be formed in the cavity 40 to improve deposition efficiency.

Simultaneously, when the thin film is deposited on the substrate S by atomic layer deposition (ALD), a source gas and a reaction gas can be alternately supplied to the substrate S. In this case, the first gas may contain a source gas, and the second gas may contain a reaction gas, or the first gas may contain a reaction gas and the second gas may contain a source gas. Furthermore, at least one of the first gas and the second gas may be a purging gas. In this case, the steps of supplying the source gas, supplying the purging gas, supplying the reaction gas, and supplying the purging gas form a single process cycle, and the process cycle can be repeated multiple times to deposit the thin film on the substrate S. In this case, plasma can be formed in cavity 40 by supplying RF power to gas supply device 600 through power supply device 400, and this can be done in the step of supplying reaction gas to improve deposition efficiency.

Therefore, the present invention has the following advantages.

According to one embodiment of the present invention, a thin semiconductor layer with high crystallinity can be formed by repeatedly performing a crystallization process of the amorphous semiconductor layer after the deposition of the amorphous semiconductor layer.

According to one embodiment of the present invention, because a thin semiconductor layer with high crystallinity can be formed, a solar cell with high conductivity and improved efficiency can still be implemented even at a thin thickness.

According to one embodiment of the present invention, a buffer layer is provided between an amorphous semiconductor layer and a crystalline semiconductor layer, thereby preventing the amorphous semiconductor layer from crystallizing or being damaged during the fabrication process of forming the crystalline semiconductor layer.

It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made within the scope of this disclosure without departing from its spirit or scope. Therefore, the scope of this disclosure is defined by the appended patent application, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the patent application are intended to fall within the scope of this disclosure.

110: Substrate 120, 120a, 120b: Cushioning Layer 130, 130a, 130b, 140a, 140b: Semiconductor Layer 200a, 200b: Transparent Conductive Layer 300a, 300b: Electrode 40: Cavity 410, 420: Gas Supply Unit 42: Cover 44: Main Body 50: Substrate Support Equipment 52: Substrate Support Component 54: Lifting Component 600: Gas Supply Equipment 610: Upper Frame 612, 622: Gas Supply Port 620: Lower Frame 630: Plate 632: Opening 650, 660: Sealing Component S: Substrate S11,S111,S112,S12,S21,S211,S212,S22,S31,S311,S312: Steps

The above and other objects, features and other advantages of this invention will be more clearly understood through the following detailed description and the accompanying drawings.

Figure 1 is a side cross-sectional schematic diagram of a solar cell according to an embodiment of the present invention.

Figure 2 is a side cross-sectional view of a solar cell according to another embodiment of the present invention.

Figure 3 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention.

Figure 4 is a flowchart of a method for manufacturing a solar cell according to another embodiment of the present invention.

Figure 5 is a graph showing the change over time in the supply of sources, etc., in a method for manufacturing solar cells according to an embodiment of the present invention.

Figure 6 is a cross-sectional view of a substrate processing apparatus for manufacturing solar cells according to an embodiment of the present invention.

110:Substrate

120a, 120b: Buffer layer

130a, 130b, 140a, 140b: Semiconductor layers

200a, 200b: Transparent conductive layer

300a, 300b: Electrodes

Claims (20)

A method of manufacturing a solar cell includes: a step of forming a first semiconductor layer on a surface of a substrate, wherein the step of forming the first semiconductor layer includes a step of forming an amorphous semiconductor layer and a step of repeating a cycle including a step of crystallizing at least a portion of the amorphous semiconductor layer, wherein the step of forming the amorphous semiconductor layer includes a step of supplying a silicon-containing gas and a first gas, and the step of crystallizing the at least a portion of the amorphous semiconductor layer includes a step of forming a plasma containing a second gas. The method of manufacturing a solar cell as described in claim 1, wherein the second gas comprises a gas containing one or more of a hydrogen-containing gas, helium, and argon. The method for manufacturing a solar cell as described in claim 1, wherein the step of forming the amorphous semiconductor layer further includes a step of forming a plasma containing the first gas, wherein the power used to form the plasma containing the first gas is lower than the power used to form the plasma containing the second gas. The method of manufacturing a solar cell as described in claim 3, wherein the first gas comprises a hydrogen-containing gas. The method for manufacturing a solar cell as described in claim 1, wherein the step of forming the amorphous semiconductor layer further includes a step of supplying a P-type dopant or an N-type dopant. The method of manufacturing a solar cell as described in claim 1 further includes, prior to the step of forming the first semiconductor layer, a step of forming a buffer layer, wherein the step of forming the buffer layer includes a step of supplying a silicon-containing gas. The method for manufacturing a solar cell as described in claim 6, wherein the step of forming the buffer layer further includes, after the step of supplying the silicon-containing gas, a step of forming a plasma containing a fourth gas, wherein the fourth gas comprises a gas combining one or more of a hydrogen-containing gas, helium, and argon. The method for manufacturing a solar cell as described in claim 7, wherein the power used to form a plasma containing the second gas is greater than the power used to form a plasma containing the fourth gas. The method for manufacturing a solar cell as described in claim 7, wherein the step of forming the buffer layer further includes a step of forming a plasma containing a third gas, wherein the third gas contains a hydrogen-containing gas. The method for manufacturing a solar cell as described in claim 9, wherein the power used to form a plasma containing the fourth gas is lower than the power used to form a plasma containing the third gas. The method for manufacturing a solar cell as described in claim 1 further includes, prior to the step of forming the first semiconductor layer, a step of forming a physical semiconductor layer on a surface of the substrate, wherein the substrate is made of a semiconductor substrate. The method of manufacturing a solar cell as described in claim 1, wherein the crystallinity of one surface of the first semiconductor layer is different from the crystallinity of another surface of the first semiconductor layer. The method of manufacturing a solar cell as described in claim 12, wherein the crystallization rate on one surface of the first semiconductor layer is higher than the crystallization rate on another surface of the first semiconductor layer, and the one surface of the first semiconductor layer is closer to the substrate than the other surface of the first semiconductor layer. The method for manufacturing a solar cell as described in claim 1 further includes: a step of supplying a first gas from a first gas supply unit to a cavity through a first gas supply pipeline; and a step of supplying a silicon-containing gas from a second gas supply unit to the cavity through a second gas supply pipeline, wherein the first gas supply unit and the second gas supply unit simultaneously supply the first gas and the silicon-containing gas to the cavity. The method of manufacturing a solar cell as described in claim 14, wherein the first gas supply line and the second gas supply line each supply gas to the cavity. The method for manufacturing a solar cell as described in claim 14 further includes a step of forming the amorphous semiconductor layer and forming a plasma containing the first gas, wherein the plasma containing the first gas is formed after the first gas and the silicon-containing gas are supplied. The method for manufacturing a solar cell as described in claim 16, wherein when the formation of the plasma containing the first gas is terminated, the supply of the silicon-containing gas is terminated and the supply of the first gas is maintained. The method for manufacturing a solar cell as described in claim 16, wherein after the formation of the plasma containing the first gas is terminated, when the step of supplying the silicon-containing gas is terminated and the step of supplying the first gas is maintained, a plasma containing the second gas is formed. A solar cell includes: a substrate; and a first semiconductor layer provided on the substrate, wherein the first semiconductor layer is a solar cell formed by a method of manufacturing a solar cell as described in any one of claims 1 to 18. The solar cell as described in claim 19 further comprises: a first buffer layer disposed between the substrate and the first semiconductor layer, wherein the first buffer layer has a thickness of more than 2 Å and less than 5 Å.