TW202512808A - Electronic device - Google Patents

Abstract

An electronic device includes a circuit structure and at least one contact part. The at least one contact part is disposed on the circuit structure and includes an insulating part and a conductive layer. The conductive layer surrounds the insulating part and is electrically connected to the circuit structure.

Description

Electronic devices

The present disclosure relates to an electronic device, and more particularly to an electronic device having a buffering effect or having a longer service life.

Electronic devices or spliced electronic devices have been widely used in different fields such as communication, display, automobile or aviation. With the rapid development of electronic devices, electronic devices are developing towards thinner and lighter, so the reliability or quality requirements for electronic devices are higher.

The present disclosure provides an electronic device that can have a buffering effect (e.g., can reduce damage or scratches on an object to be tested) or can increase the service life of the electronic device (e.g., can reduce aging of a circuit structure).

The electronic device disclosed in the present invention includes a circuit structure and at least one contact portion. The at least one contact portion is disposed on the circuit structure and includes an insulating portion and a conductive layer. The conductive layer surrounds the insulating portion and is electrically connected to the circuit structure.

In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that, in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

In the following description and patent application, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

It should be understood that when an element or film layer is referred to as being "on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or film layer, or there may be an intervening element or film layer between the two (indirect situation). Conversely, when an element is referred to as being "directly" "on" or "directly connected to" another element or film layer, there may be no intervening elements or film layers between the two.

Although the terms "first", "second", "third" ... can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the patent application, but may be replaced by first, second, third ... according to the order of the components declared in the patent application. Therefore, in the following specification, the first component may be the second component in the patent application.

In this document, the terms "about", "approximately", "substantially", and "generally" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", "substantially", and "generally", the meanings of "about", "approximately", "substantially", and "generally" can still be implied.

In some embodiments of the present disclosure, terms such as "connected", "interconnected", etc., related to bonding and connection, unless otherwise specifically defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an elliptical thickness gauge, or other suitable methods may be used to measure the area, width, thickness, or height of each component, or the distance or spacing between components. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the component to be measured, and measure the area, width, thickness, or height of each component, or the distance or spacing between components.

The electronic device or electronic assembly disclosed herein may include a display device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal light emitting diode; the light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (QD, which may be, for example, QLED, QDLED), fluorescence, phosphor or other suitable materials, and the materials may be arranged and combined in any manner, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. The disclosure hereinbelow will be described using electronic devices, but the disclosure is not limited thereto. According to an embodiment of the disclosure, the electronic unit may include a packaging component, and the packaging component may include a system on package (SoC), a system in package (SiP), an antenna package (AiP), a co-packaged optics (COP), a micro electro mechanical system (MEMS), a high density interconnector PCB (HDI PCB), an IC carrier, or a combination thereof, but is not limited thereto. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to represent the same or like parts.

FIG1 is a cross-sectional schematic diagram of an electronic device according to a first embodiment of the present disclosure. FIG2A is a partially enlarged schematic diagram of the electronic device of FIG1. FIG2B is an enlarged schematic diagram of a contact portion of FIG2A. FIG2C is a three-dimensional schematic diagram of a contact portion of FIG2A. FIG3A to FIG3F are partial cross-sectional schematic diagrams of a manufacturing method of the electronic device of FIG2A.

Please refer to FIG. 1 and FIG. 2A at the same time. The electronic device 100 of this embodiment includes a circuit board 110, a carrier 120, a circuit structure 130, at least one contact portion 140, and a surface element 150. The electronic device 100 can be electrically connected to the object to be tested 200 through the contact portion 140. For example, the electronic device 100 has a first operation mode, and the first operation mode can be used to perform electrical testing on the object to be tested 200 through the contact portion 140. In this embodiment, the object to be tested 200 may include a semiconductor wafer, a display device, or other electronic devices or electronic units that need to be electrically tested, but is not limited thereto. The electronic device 100 may further include a through slot 170, and the through slot 170 may separate the circuit board 110. That is, when the electronic device 100 has a plurality of circuit boards 110, the through slot 170 may be disposed between two adjacent circuit boards 110. A suitable width of the through slot 170 may prevent signals of the plurality of circuit boards 110 from interfering with each other in the first operation mode. For example, in the X direction, the maximum width of the through slot 170 may be greater than or equal to 1/10 of the maximum width of the circuit board 110 and less than or equal to 1/2 of the maximum width of the circuit board 110. If the widths of two adjacent circuit boards 110 are different, the one with the larger width is used as the target, but the present invention is not limited thereto. The through slot 170 can be aligned with the object under test 200 , and the through slot 170 can overlap the object under test 200 in the direction Z (the normal direction of the circuit board 110 , the normal direction of the carrier 120 , or the normal direction of the electronic device 100 ).

Specifically, the circuit board 110 can be electrically connected to a tester (not shown) and a circuit structure 130, respectively. The circuit board 110 can be electrically connected to the contact portion 140 through the circuit structure 130. When the electronic device 100 performs an electrical test on the object under test 200, the circuit board 110 or the circuit structure 130 can be used to transmit electrical signals between the tester and the object under test 200, and can be, for example, an HDI board, an IC carrier, a combination of the above, or other circuit structures. In the present embodiment, the circuit board 110 has an upper surface 111, a lower surface 112, and a side surface 113, wherein the side surface 113 is respectively connected to the upper surface 111 and the lower surface 112, and the connection portion has an arc profile. This design can reduce the risk of the circuit structure 130 breaking, but is not limited thereto. The upper surface 111 and the lower surface 112 are opposite to each other and in the first operation mode, the upper surface 111 is farther from the object to be tested 200 than the lower surface 112. The circuit board 110 can be, for example, a PCB board or other suitable connectors.

The carrier 120 is disposed on the upper surface 111 of the circuit board 110. The carrier 120 can be any component that can be used to support the circuit structure 130. The carrier 120 may include steel plate, glass, polyimide (PI), polyethylene terephthalate (PET), wafer, ajinomoto build-up layer (ABF), BT carrier (Bismaleimide triazine resin), flame resistant glass fiber (FR4) substrate or other suitable materials or a combination of the above materials, but is not limited thereto. In this embodiment, the carrier 120 may include a body 121 and a buffer 122. The body 121 is disposed on the upper surface 111 of the circuit board 110. The buffer member 122 is disposed on the body 121, the buffer member 122 is disposed in the through slot 170, and the buffer member 122 is disposed between the body 121 and the circuit structure 130 in the direction Z, thereby supporting the circuit structure 130. The elongation of the buffer member 122 can be 80% to 150%, but is not limited thereto. Furthermore, the elongation of the buffer member 122 can be greater than or equal to the elongation of the body 121. When the electronic device 100 performs an electrical test on the DUT 200 (or in the first operation mode), the buffer 122 of the carrier 120 can press down the circuit structure 130 so that the contact portion 140 can contact and electrically connect to the conductive pad 210 of the DUT 200. Through the above design, since the carrier 120 can provide a supporting or buffering effect, the damage of the DUT 200 can be reduced or the aging of the circuit structure 130 can be reduced.

The circuit structure 130 is disposed on the upper surface 111 of the circuit board 110, and at least a portion of the circuit structure 130 is disposed between the carrier 120 and the upper surface 111 of the circuit board 110. The circuit structure 130 is coupled to the carrier 120. For example, the circuit structure 130 can be electrically connected to the carrier 120 or fixed on the carrier 120. In the present embodiment, the circuit structure 130 can be, for example, a redistribution structure (RDL), but is not limited thereto. The circuit structure 130 has a first surface 130a and a second surface 130b opposite to each other, and the first surface 130a faces the carrier 120. The circuit structure 130 includes a first conductive layer 131, a second conductive layer 132, a third conductive layer 133 and an insulating layer 134. The first conductive layer 131 is disposed on the first surface 130a. The second conductive layer 132 is disposed on the second surface 130b. The insulating layer 134 is disposed between the first conductive layer 131 and the second conductive layer 132. The third conductive layer 133 is disposed between the first conductive layer 131 and the second conductive layer 132, and the third conductive layer 133 is disposed in the insulating layer 134. In the present embodiment, the materials of the first conductive layer 131, the second conductive layer 132, and the third conductive layer 133 may include metal materials, transparent conductive materials, other suitable conductive materials, or a combination thereof, but not limited thereto. In the present embodiment, the insulating layer 134 may be a single-layer structure or a multi-layer structure, and the material of the insulating layer 134 may include polyimide (PI), glass, epoxy, silane coupling, photosensitive material, build-up material, or a combination thereof, but not limited thereto. According to some embodiments, a redistribution layer (RDL) structure can redistribute the circuits of the DUT or electronic components and/or further increase the circuit fan-out area, or different electronic components can be electrically connected to each other through the circuit structure 130. For example, the distance between two adjacent contact pads in the circuit structure 130 near one end of the DUT 200 can be less than or equal to the distance between two adjacent contact pads in the circuit structure 130 near one end of the carrier 120, so the circuit structure 130 can adjust the circuit distribution, but is not limited thereto. Furthermore, the circuit structure 130 may be applied to wafer level chip scale package (WLCSP), wafer level package (WLP), panel level package (PLP) or other packaging methods, but is not limited thereto.

Please refer to FIG. 1, FIG. 2A and FIG. 2B simultaneously. The contact portion 140 is disposed on the second surface 130b of the circuit structure 130. The contact portion 140 can contact and electrically connect to the second conductive layer 132 of the circuit structure 130. In this embodiment, the contact portion 140 includes an insulating portion 141, a conductive layer 142 and an anti-oxidation layer 143. The conductive layer 142 surrounds the insulating portion 141 and can be electrically connected to the circuit structure 130. The anti-oxidation layer 143 surrounds the conductive layer 142 to reduce the probability of the conductive layer 142 being oxidized by contacting the external water oxygen. According to some embodiments, the contact portion 140 may be, for example, a conductive pad for contacting the object under test when executing the first operation mode. For example, when testing a wafer (object under test), the contact portion 140 may be an input/output pad (I/O pad) for contacting the wafer.

In this embodiment, the material of the insulating portion 141 may be a polymer, polyimide, photosensitive polyimide, silicone rubber, resin, other organic materials with elasticity (high elongation) or buffering effect, or a combination thereof, but not limited thereto. According to some embodiments, the elongation of the insulating portion 141 is greater than the elongation of the insulating layer of the circuit structure 130. The conductive layer 142 may be a single-layer structure or a multi-layer structure, and the material of the conductive layer 142 may include copper, titanium, aluminum, nickel, silver, gold, tantalum, platinum, or a combination thereof, but not limited thereto. The anti-oxidation layer 143 may be a single-layer structure or a multi-layer structure, and the material of the anti-oxidation layer 143 may include nickel, palladium, gold, the aforementioned alloy (such as electroless nickel immersion gold (ENIG)) or the aforementioned combination, but is not limited thereto. The activity of the anti-oxidation layer 143 may be less than the activity of the conductive layer 142 to reduce the probability of the conductive layer 142 being oxidized by contact with external water and oxygen.

In this embodiment, the elongation of the insulating portion 141 can be 20% to 900%, and the elongation of the insulating portion 141 can be greater than the elongation of the insulating layer 134 of the circuit structure 130, so as to increase the toughness and deformation of the contact portion 140 containing the insulating portion 141, and enable the contact portion 140 containing the insulating portion 141 to provide a buffering effect to reduce damage to the object under test 200 or reduce aging of the circuit structure 130, but is not limited to this.

In the present embodiment, the conductive layer 142 has a thickness T1, and the anti-oxidation layer 143 has a thickness T2. The thickness T1 is, for example, the maximum thickness of the conductive layer 142 measured along the direction Z, and the thickness T2 is, for example, the maximum thickness of the anti-oxidation layer 143 measured along the direction Z. In the present embodiment, the thickness T2 of the anti-oxidation layer 143 may be less than the thickness T1 of the conductive layer 142, but is not limited thereto.

2C , in the three-dimensional diagram of the contact portion 140 , the bottom surface S1 of the contact portion 140 facing the object to be tested 200 has a length L and a width W, the contact portion 140 has a height H, and there is a distance P between two adjacent contact portions 140 . The length L is, for example, the maximum length of the bottom surface S1 of the contact portion 140 measured along the direction Y, the width W is, for example, the maximum width of the bottom surface S1 of the contact portion 140 measured along the direction X, the height H is, for example, the maximum height of the contact portion 140 measured along the direction Z, and the distance P is, for example, the distance between the centers of the bottom surfaces S1 of the two adjacent contact portions 140 measured along the direction X. In this embodiment, the length L of the contact portion 140 can be 5 μm to 200 μm, and the width W can be 5 μm to 200 μm, so that the bottom surface S1 of the contact portion 140 can have a sufficient contact area to contact the conductive pad 210 of the object under test 200, thereby reducing the contact resistance, but not limited to this. According to some embodiments, the length L of the contact portion 140 is less than or equal to the length of the conductive pad 210 of the object under test 200, or the ratio of the length L of the contact portion 140 to the length of the conductive pad 210 is greater than or equal to 0.5 and less than 1. This design allows the bottom surface S1 of the contact portion 140 to have a sufficient contact area to contact the conductive pad 210 of the object under test 200. In the present embodiment, the height H of the contact portion 140 may be 30 μm to 200 μm, and the ratio of the length L to the height H of the contact portion 140 may be greater than or equal to 0.5 and less than or equal to 1.5 (i.e., 0.5≤L/H≤1.5), so that when the contact portion 140 shrinks due to pressing down on the conductive pad 210 of the object under test 200, there may be sufficient buffer space to reduce aging of the circuit structure 130, but the present invention is not limited thereto. In this embodiment, the distance P between two adjacent contact portions 140 may be 10 micrometers to 500 micrometers, so that the two adjacent contact portions 140 can both contact two adjacent conductive pads 210 on the object under test 200 during electrical testing, but the present invention is not limited thereto.

Please continue to refer to FIG. 2C . In this embodiment, the shape of the contact portion 140 may be a column, but is not limited thereto. In some embodiments, the shape of the contact portion may also be a sphere or any other shape.

In this embodiment, the maximum coplanarity of the circuit structure 130 can be 10% to 20% of the height H of the contact portion 140 to reduce the error of the electrical test. In other words, when the circuit structure 130 coupled to the carrier 120 is pressed down to contact the object under test 200, the average height difference between each contact portion 140 should be greater than or equal to 0 and less than or equal to 0.2 times the height H, or greater than or equal to 0.1 times the height H and less than or equal to 0.2 times the height H, so as not to cause an error in the electrical test. The coplanarity referred to in the present disclosure refers to the property or state of multiple points existing on the same plane, that is, the smaller the average spacing or average height difference between multiple contact portions 140 of the circuit structure 130 or at least more than 10 contact portions 140 and the same plane or a straight line, the better. When it is at least less than or equal to 0.2 times the height H, better test quality can be obtained, wherein the measurement direction of the spacing or height difference is a direction perpendicular to the plane or the straight line, and the plane can be regarded as a plane or a straight line parallel to the carrier 120, for example, the straight line can extend along the X direction in the figure.

In this embodiment, direction X, direction Y, and direction Z are different directions. For example, direction X is, for example, an extension direction of the width W of the bottom surface S1 of the contact portion 140, direction Y is, for example, an extension direction of the length L of the bottom surface S1 of the contact portion 140, and direction Z is, for example, a normal direction of the circuit board 110 or a normal direction of the electronic device 100. Direction X and direction Y are respectively substantially perpendicular to direction Z, and direction X is substantially perpendicular to direction Y, but is not limited thereto.

Please continue to refer to FIG. 1 and FIG. 2A simultaneously. The surface element 150 is disposed on the circuit structure 130. The surface element 150 can be bonded and electrically connected to the circuit structure 130 through the bonding element 151. In the present embodiment, the surface element 150 can be a passive element (such as a capacitor, a resistor, or an inductor) or other electronic element, but is not limited thereto. In the present embodiment, the bonding element 151 can be a solder pad, an anisotropic conductive film (ACF), or other conductive member, but is not limited thereto. The material of the bonding element 151 can be tin, but is not limited thereto.

The object under test 200 is disposed under the circuit board 110 . The object under test 200 may overlap the through slot 170 in the direction Z. The object under test 200 has a conductive pad 210 . The object under test 200 may contact and be electrically connected to the contact portion 140 through the conductive pad 210 .

Then, please refer to FIG. 3A to FIG. 3F , and the manufacturing method of the contact portion 140 of the electronic device 100 of this embodiment will be described below. In this embodiment, the manufacturing method of the contact portion 140 of the electronic device 100 may include but is not limited to the following steps:

First, please refer to FIG. 3A , and provide a circuit structure 130. Specifically, the circuit structure 130 has a first surface 130a and a second surface 130b opposite to each other. The circuit structure 130 includes a first conductive layer 131, a second conductive layer 132, a third conductive layer 133, and an insulating layer 134. The first conductive layer 131 is disposed on the first surface 130a. The second conductive layer 132 is disposed on the second surface 130b. The insulating layer 134 is disposed between the first conductive layer 131 and the second conductive layer 132. The third conductive layer 133 is disposed between the first conductive layer 131 and the second conductive layer 132, and the third conductive layer 133 is disposed in the insulating layer 134.

Next, referring to FIG. 3B , a first photoresist 300 is formed on the second surface 130b of the circuit structure 130, and an insulating portion 141 is formed in the first opening 301 of the first photoresist 300. Specifically, the first photoresist 300 has a first opening 301, and the first opening 301 can expose a portion of the circuit structure 130. The insulating portion 141 is filled in the first opening 301 of the first photoresist 300, so that the insulating portion 141 can contact the portion of the second surface 130b of the circuit structure 130 exposed by the first opening 301.

Next, please refer to FIG. 3C , remove the first photoresist 300, and form a seed layer SL on the insulating portion 141. Specifically, the seed layer SL includes a first portion SL1 and a second portion SL2 connected to each other. The first portion SL1 of the seed layer SL may contact and cover the upper surface 1411 (i.e., the surface facing away from the circuit structure 130) and the side surface 1412 of the insulating portion 141, and the second portion SL2 of the seed layer SL may contact and cover a portion of the second surface 130b of the circuit structure 130. In the present embodiment, the seed layer SL is formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), electroplating, chemical deposition, physical vapor deposition (PVD), but is not limited thereto. The seed layer SL may include a conductive material, such as titanium, copper, tantalum, tungsten, alloys or combinations thereof, or other suitable conductive materials. In the Z direction, the thickness of the seed layer SL is greater than or equal to 0.2 micrometers (micrometer, m) and less than or equal to 3 micrometers, thereby improving the bonding ability between the contact portion 140 and other film layers, but not limited thereto. According to some embodiments, the seed layer SL may include a single layer of conductive material or a stack of multiple layers of conductive material.

Next, please refer to Figure 3D, a second photoresist 310 is formed on the seed layer SL, and a conductive material layer CL is formed in the second opening 311 of the second photoresist 310. Specifically, the second photoresist 310 has a second opening 311. The second opening 311 can expose the first portion SL1 of the seed layer SL, and the second photoresist 310 can cover the second portion SL2 of the seed layer SL. The conductive material layer CL can contact the first portion SL1 of the seed layer SL. In this embodiment, the conductive material layer CL is formed by, for example, electroplating or chemical plating, but is not limited thereto. The conductive material layer CL may include a conductive material, such as titanium, copper, tungsten, tungsten, alloys or combinations thereof, or other suitable conductive materials. In the Z direction, the thickness of the conductive material layer CL is greater than or equal to 2 microns and less than or equal to 7 microns, thereby reducing impedance to avoid signal loss, but not limited thereto. According to some embodiments, the reactivity of the conductive material layer CL is less than or equal to the reactivity of at least one of the seed layers SL.

Next, referring to FIG. 3E , the second photoresist 310 is removed, and the seed layer SL not covered by the conductive material layer CL is removed. Specifically, after removing the second photoresist 310, the second portion SL2 of the seed layer SL is removed, for example, by etching, and the first portion SL1 of the seed layer SL covered by the conductive material layer CL is left. The combination of the conductive material layer CL and the first portion SL1 of the seed layer SL can be regarded as the conductive layer 142 of the contact portion 140.

Next, please refer to FIG3F , in the steps similar to FIG3D to FIG3E , an anti-oxidation layer 143 is formed on the conductive layer 142 . At this point, the contact portion 140 of the electronic device 100 of this embodiment has been substantially manufactured.

In this embodiment, the elongation is measured, for example, by the standard test method for tensile properties of plastics (ASTM D638). Specifically, the component to be subjected to the tensile test is first separated from the electronic device 100; then, two marks are pre-marked on the component, wherein the distance between the two marks is called the gage length; then, the component is stretched using a stretching machine (e.g., a universal testing machine) so that the gage length is gradually extended during the tensile test. Wherein, the elongation = (gage length after stretching - original gage length before stretching) ÷ original gage length before stretching × 100%. Alternatively, the elongation may be the elongation at yield calculated based on the elongation ratio of the component at the yield point (i.e., the maximum elongation before permanent deformation of the component occurs).

In this embodiment, the electronic device 100 may be a testing device, such as a high-frequency testing device, but is not limited thereto.

Other embodiments are listed below for illustration. It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

Fig. 4 is a cross-sectional view of a contact portion of an electronic device according to a second embodiment of the present disclosure. Referring to Fig. 4 and Fig. 2B, the contact portion 140a of this embodiment is similar to the contact portion 140 of Fig. 2B, but the difference between the two is that the contact portion 140a of this embodiment further includes a filler 144a.

Specifically, referring to FIG. 4 , the filling material 144a is dispersed in the insulating portion 141, and the filling rate of the filling material 144a in the insulating portion 141 can be 40 wt% to 88 wt% (40 wt% ≤ filling rate ≤ 88 wt%) to reduce the resistance of the insulating portion 141, but not limited thereto. In the present embodiment, the material of the filling material 144a may include copper, gold, silver, tin, other materials with conductive properties, or a combination thereof, but not limited thereto. The term "dispersed" as used herein means that there is a distance between two particles in the same medium or that they do not contact each other.

In the present embodiment, the filling material 144a has a particle size D, and the particle size D of the filling material 144a can be 0.1 micron to 50 microns (0.1μm ≤ particle size ≤ 50μm), or 0.5 micron to 8 microns (0.5μm ≤ particle size ≤ 8μm), but not limited thereto. By adding the filling material 144a, the buffering ability of the contact portion 140 can be adjusted to make the design more flexible, thereby improving the service life of the circuit structure 130, or reducing the situation of scratching the object to be tested, but not limited thereto.

FIG5 is a cross-sectional schematic diagram of the contact portion of the electronic device of the third embodiment of the present disclosure. Please refer to FIG5 and FIG4 simultaneously. The contact portion 140b of this embodiment is similar to the contact portion 140a of FIG4, but the difference between the two is that in the contact portion 140b of this embodiment, the material of the filling material 144b is an insulating material with a higher hardness than the insulating portion 141, so as to increase the hardness of the insulating portion 141. In this embodiment, the material of the filling material 144b may include silicon oxide, silicon nitride, plastic, other high-hardness insulating materials, or a combination thereof, but is not limited thereto.

Fig. 6 is a cross-sectional view of the electronic device of the fourth embodiment of the present disclosure. Please refer to Fig. 6 and Fig. 1 simultaneously. The electronic device 100c of this embodiment is similar to the electronic device 100 of Fig. 1, but the difference between the two is that the electronic device 100c of this embodiment further includes a connector 160c.

Specifically, referring to FIG6 , the connector 160c is disposed on the lower surface 112 of the circuit board 110 to fix the circuit structure 130. In this embodiment, the connector 160c can be an independent component or a part of the carrier 120.

The circuit structure 130 is disposed between the lower surface 112 of the circuit board 110 and the connector 160c, and the circuit board 110 is disposed between the carrier 120 and the circuit structure 130, thereby shortening the transmission path of the electrical signal between the circuit board 110 and the object under test 200, thereby reducing the loss of the electrical signal or improving the accuracy of the electrical test.

FIG7 is a cross-sectional view of the electronic device of the fifth embodiment of the present disclosure. Referring to FIG7 and FIG1 simultaneously, the electronic device 100d of this embodiment is similar to the electronic device 100c of FIG6 , except that the body 121 and the through slot 170 of FIG6 are omitted in the electronic device 100d of this embodiment.

Specifically, please refer to FIG. 7 , the buffer 122d is directly disposed on the lower surface 112 of the circuit board 110 so that the pressed circuit structure 130 can contact multiple DUTs 200 ( FIG. 7 schematically shows three DUTs 200, but is not limited thereto) through multiple contact portions 140 at the same time, so as to detect multiple DUTs 200 at the same time and reduce the overall detection time.

In addition, in the present embodiment, the circuit board 110d without the through slot 170 can increase the utilization rate of its wiring space.

In summary, in the electronic device of the disclosed embodiment, since the contact portion contains an elastic or high-elongation insulating portion (for example, an insulating portion with an elongation of 20% to 900%, or an insulating portion with an elongation greater than that of the insulating layer of the circuit structure), the toughness and deformation of the contact portion can be increased, and the contact portion can provide a buffering effect to reduce damage to the object to be tested or reduce aging of the circuit structure. Since the length of the contact portion can be 5 microns to 200 microns, and the width can be 5 microns to 200 microns, the bottom surface of the contact portion can have a sufficient contact area to contact the conductive pad of the object to be tested, thereby reducing the contact impedance. Since the height of the contact portion can be 30 microns to 200 microns, and the ratio of the length to the height of the contact portion can be greater than or equal to 1/2, when the contact portion shrinks due to the downward pressure on the conductive pad of the object to be tested, there can be sufficient buffer space to reduce the aging of the circuit structure. Since the insulating portion of the contact portion contains a conductive filling material, and the filling rate of the filling material in the insulating portion can be 40 weight % to 88 weight %, the impedance of the insulating portion can be reduced. Since the insulating portion of the contact portion contains a high-hardness filling material, and the filling rate of the filling material in the insulating portion can be 40 weight % to 88 weight %, the hardness of the insulating portion can be increased.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

100, 100c, 100d: electronic device 110, 110d: circuit board 111: upper surface 112: lower surface 113: side surface 120: carrier 121: body 122, 122d: buffer 130: circuit structure 130a: first surface 130b: second surface 131: first conductive layer 132: second conductive layer 133: third conductive layer 134: insulating layer 140, 140a, 140b: contact part 141: insulating part 1411: upper surface 1412: side surface 142: conductive layer 143: Anti-oxidation layer 144a, 144b: Filling material 150: Surface element 151: Bonding element 160c: Connector 170: Through slot 200: Object to be tested 210: Conductive pad 300: First photoresist 301: First opening 310: Second photoresist 311: Second opening CL: Conductive material layer D: Particle size H: Height L: Length P: Pitch S1: Bottom surface SL: Seed layer SL1: First part SL2: Second part T1, T2: Thickness W: Width X, Y, Z: Direction

FIG. 1 is a schematic cross-sectional view of an electronic device of the first embodiment of the present disclosure. FIG. 2A is a partially enlarged schematic view of the electronic device of FIG. 1. FIG. 2B is an enlarged schematic view of the contact portion of FIG. 2A. FIG. 2C is a three-dimensional schematic view of the contact portion of FIG. 2A. FIG. 3A to FIG. 3F are schematic cross-sectional views of a method for manufacturing the electronic device of FIG. 2A. FIG. 4 is a schematic cross-sectional view of the contact portion of the electronic device of the second embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view of the contact portion of the electronic device of the third embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of the electronic device of the fourth embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view of the electronic device of the fifth embodiment of the present disclosure.

130: Circuit structure

130a: first surface

130b: Second surface

131: First conductive layer

132: Second conductive layer

133: The third conductive layer

134: Insulation layer

140: Contact part

141: Insulation Department

142: Conductive layer

143: Antioxidant layer

150: Surface elements

151:Joint element

200: Object to be tested

210: Conductive pad

S1: bottom surface

X, Y, Z: direction

Claims (10)

An electronic device includes: a circuit structure; and at least one contact portion disposed on the circuit structure and including an insulating portion and a conductive layer; wherein the conductive layer surrounds the insulating portion and is electrically connected to the circuit structure. An electronic device as described in claim 1, wherein the elongation of the insulating portion is 20% to 900%. The electronic device as described in claim 1, wherein the at least one contact portion further comprises: Filling material dispersed in the insulating portion. An electronic device as described in claim 3, wherein the particle size of the filling material is 0.1 micron to 50 microns. An electronic device as described in claim 3, wherein the filling rate of the filling material is 40 wt % to 88 wt %. An electronic device as described in claim 1, wherein the elongation of the insulating portion is greater than the elongation of the insulating layer of the circuit structure. The electronic device as described in claim 1, wherein the at least one contact portion further comprises: An anti-oxidation layer surrounding the conductive layer, wherein the thickness of the anti-oxidation layer is less than the thickness of the conductive layer. An electronic device as described in claim 1, wherein the bottom surface of the at least one contact portion has a length and a width, the length is 5 microns to 200 microns, and the width is 5 microns to 200 microns. An electronic device as described in claim 8, wherein the at least one contact portion has a height, and the height is 30 microns to 200 microns. An electronic device as described in claim 9, wherein a ratio of the length to the height is greater than or equal to 0.5 and less than or equal to 1.5.

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