TW202507821A - Heteroepitaxial growth wafer and manufacturing method thereof - Google Patents

Abstract

The present invention is a heteroepitaxial growth wafer, which is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer, respectively. The heteroepitaxial growth wafer is characterized in that the relationship between the film thickness of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is film thickness (nm) < 1.4 × 10 ⁷ × [Ge (%)] ^-4.5 . Thus, a heteroepitaxial growth wafer that does not capture metal impurities can be provided.

Description

Heteroepitaxial growth wafer and manufacturing method thereof

The present invention relates to a heteroepitaxial growth wafer and a manufacturing method thereof.

As a substrate for making semiconductor integrated circuits, silicon wafers made by the CZ method (Czochralski) are mainly used. In particular, in order to suppress the short channel effect, the GAA (Gate All Around) structure is used in the most advanced technology devices. It is composed of the FinFET structure used today and the channel layer is surrounded by electrodes from four directions. This structure uses a silicon germanium epitaxial growth wafer (hereinafter sometimes referred to as a heteroepitaxial growth wafer), which is formed by stacking a number of silicon germanium (SiGe) epitaxial growth layers (hereinafter referred to as silicon germanium layers) and silicon epitaxial growth layers (hereinafter referred to as silicon layers) on a silicon single crystal substrate (silicon wafer or sometimes simply referred to as a silicon substrate).

Furthermore, a wafer like this, in which a layer of a different material (such as a silicon germanium layer) is epitaxially grown on a substrate (such as a silicon single crystal substrate), is generally called a heteroepitaxially grown wafer.

At this time, the difference in etching speed between the silicon germanium layer and the silicon layer is utilized to remove the silicon germanium layer by etching, thereby using the silicon layer as a channel layer. Therefore, it is necessary to greatly increase the difference in etching speed between the silicon germanium layer and the silicon layer. In order to achieve this, it is effective to increase the germanium concentration of the silicon germanium layer. At this time, the thickness of the silicon germanium layer needs to be set to the same as the thickness of the electrode layer surrounding the channel part in the GAA structure, and the most appropriate thickness is designed according to each device. Specifically, the silicon germanium layer forms an insulating film and an electrode metal film around the silicon layer that will become the channel layer after etching. To achieve this, the silicon germanium layer needs to be made the same thickness as the electrode metal layer.

On the other hand, the covalent radius of germanium is larger than that of silicon, so the lattice constant of the silicon germanium layer also becomes larger than that of the silicon layer or the silicon substrate. Therefore, a lattice mismatch occurs between the silicon germanium layer and the silicon layer or the silicon substrate. The lattice mismatch becomes larger as the germanium concentration increases. In addition, it is known that mismatch dislocations (hereinafter, sometimes simply referred to as dislocations) are introduced at the interface between the silicon germanium layer and the silicon layer or the silicon substrate due to the lattice mismatch.

When the germanium concentration of the silicon germanium layer is fixed, dislocation occurs above a certain fixed thickness of the silicon germanium layer. This thickness is called the critical film thickness for dislocation (hereinafter, the first critical film thickness). The first critical film thickness at each film formation temperature is shown in FIG. 1 of Patent Document 1, and the first critical film thickness becomes thicker as the film formation temperature is lower.

However, even in silicon germanium wafers formed below the first critical film thickness, dislocations may occur when the device is subjected to subsequent heat treatment. These dislocations become capture sites for metal impurities (hereinafter sometimes referred to as gettering sites), and when unexpected contamination occurs during the device process, they may cause device characteristics to fail.

In addition, FIG. 2 of Patent Document 2 shows a situation where the first critical film thickness at which mismatch dislocation occurs at a heterogeneous interface is different due to differences in crystal plane orientation. However, in this case, dislocation may still occur after a device heat treatment is applied to a silicon germanium wafer formed below the first critical film thickness.

When the thickness of the silicon germanium layer is thin, for example, about 5 to 30 nm, the critical film thickness (hereinafter, the second critical film thickness) for capturing metal impurities by the subsequent heat treatment becomes thicker than the first critical film thickness of Patent Documents 1 and 2. The reason is that even if dislocations that become capture sites are generated, their density becomes low, and the density of capture sites for metal impurities also becomes low, making it difficult to capture metal.

When the germanium concentration of the silicon germanium layer is the same, the mismatch dislocation after the epitaxial growth step will become less likely to occur as the film formation temperature of the silicon germanium layer becomes lower, and the first critical film thickness referred to in patent documents 1 and 2 will become thicker.

In contrast, the critical film thickness referred to in the present invention refers to a second critical film thickness that can capture metal impurities in the dislocations generated by additional heat treatment such as device heat treatment performed after the epitaxial growth step.

Here, the focus is on the density of dislocations that will become capture sites for metallic impurities.

The dislocations generated by the additional heat treatment after the epitaxial growth step, when the germanium concentration of the silicon germanium layer is low, the film stress will also be small, and the density of dislocations will be low. As a result, the density of metal capture sites will also be low, making it impossible to capture metal impurities.

On the other hand, when the germanium concentration of the silicon germanium layer is high, the film stress will also increase, the density of dislocations will increase, and the density of metal capture sites will also increase, making it easier to capture metal impurities.

For the reasons mentioned above, the first critical film thickness at which dislocation occurs after the epitaxial growth step is completely different from the second critical film thickness at which metal impurities can be captured after an additional heat treatment.

Here, the point is that the reason for the deterioration of device characteristics is the capture of metal impurities. The metal impurities captured in the additional heat treatment after the epitaxial growth step have a distribution in the depth direction, and metal is also contained in the most important channel layer. Generally speaking, metal impurities form deeper levels and cause carrier recombination centers or generation centers, thereby deteriorating device characteristics. [Prior Art Literature] (Patent Literature)

Patent document 1: Japanese Patent Publication No. 2009-59939 Patent document 2: Japanese Patent Publication No. 5-326398

[Problem to be solved by the invention] It is desired that even if the heteroepitaxial growth wafer represented by the silicon germanium wafer described above is subjected to device heat treatment, it will not capture metal impurities and deteriorate the device characteristics. However, there has always been a technical problem that even if dislocation is not observed immediately after the epitaxial growth step, dislocation will still occur and metal impurities will be captured by heat treatment such as device heat treatment.

The present invention is made in view of the above-mentioned previous technical problems, and its purpose is to provide a heterogeneous epitaxial growth wafer that does not capture metal impurities. [Technical means for solving the problem]

In order to solve the above technical problems, the heteroepitaxial growth wafer of the present invention is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the aforementioned silicon germanium layer, respectively, and the relationship between the film thickness (film thickness) of the aforementioned silicon germanium layer and the germanium concentration (Ge (%)) of the aforementioned silicon germanium layer is film thickness (nm) < 1.4×10 ⁷ × [Ge (%)] ^-4.5 .

As long as the thickness of the silicon germanium layer and the germanium concentration of the silicon germanium layer are in this state, the heteroepitaxial growth wafer will become one that is difficult to capture metal impurities.

Furthermore, it is preferred that even if the heteroepitaxial growth wafer is subjected to a device heat treatment, no impurities are captured at any of the interfaces between the silicon single crystal substrate and the silicon germanium layer and the interfaces between the silicon germanium layer and the silicon layer.

As long as the heteroepitaxial growth wafer does not capture impurities at the interface after the device heat treatment is applied, it will be more reliable to not capture metal impurities. In addition, as long as the heteroepitaxial growth wafer does not capture impurities after the device heat treatment is applied, even if the heat treatment is applied for device manufacturing, the device characteristics can be prevented from being deteriorated due to the capture of metal impurities.

Furthermore, it is preferred that the thickness of the silicon germanium layer is 3 to 140 nm, and the germanium concentration is 10 to 30%.

As long as the thickness of the silicon germanium layer and the germanium concentration are within this range, the heteroepitaxially grown wafer will more reliably not capture metal impurities.

In addition, it is preferred that the silicon germanium layer and the silicon layer are formed in a plurality of sets.

As long as a heteroepitaxial growth wafer with multiple sets of silicon germanium layers and silicon layers is formed in this way, metal impurities will not be captured at the interface between each silicon germanium layer and silicon layer. This can be easily applied to the most advanced technology device such as the GAA structure formed by stacking multiple sets of silicon germanium layers and silicon layers, and can be made into a device that does not capture metal impurities.

In addition, the heteroepitaxial growth wafer manufacturing method of the present invention is obtained by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer, respectively. In the manufacturing method, the silicon germanium layer is epitaxially grown so that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer becomes film thickness (nm) < 1.4 × 10 ⁷ × [Ge (%)] ^-4.5 .

As long as the film thickness and germanium concentration of the silicon germanium layer are set to such a level, a heteroepitaxially grown wafer that does not capture metal impurities can be manufactured even when heat treatment is applied to the device. [Effect of the invention]

The heteroepitaxial growth wafer of the present invention does not capture metal impurities by regulating the relationship between the film thickness of the silicon germanium layer and the germanium concentration of the silicon germanium layer. In addition, the heteroepitaxial growth wafer does not capture metal impurities even when subjected to device heat treatment, and even when subjected to heat treatment for device manufacturing, the device characteristics can be prevented from being deteriorated due to the capture of metal impurities.

Furthermore, the manufacturing method of the present invention can simply and reliably manufacture heteroepitaxially grown wafers that do not capture metal impurities even when subjected to device heat treatment.

The present invention is described in detail below, but the present invention is not limited to the description.

As described above, in a device using a GAA structure, it is desired that dislocation does not occur even if the device is subjected to heat treatment. The cause of the dislocation is the lattice mismatch between the silicon germanium layer and the silicon layer or the silicon single crystal substrate.

The inventors have devoted themselves to research on this technical problem and have found the relationship between the film thickness of the silicon germanium layer and the germanium concentration, which will cause the capture of metal impurities (gettering phenomenon) after the device is heat treated, and have completed the present invention.

That is, the present invention is a heteroepitaxial growth wafer, which is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the aforementioned silicon germanium layer, respectively. The characteristic of the heteroepitaxial growth wafer is that the relationship between the film thickness (film thickness) of the aforementioned silicon germanium layer and the germanium concentration (Ge (%)) of the aforementioned silicon germanium layer is film thickness (nm) < 1.4×10 ⁷ × [Ge (%)] ^-4.5 (Formula 1).

The following is explained with reference to the drawings.

FIG. 1 is a schematic diagram of a heteroepitaxial growth wafer in an embodiment of the present invention, which has a silicon single crystal substrate 1, a silicon germanium layer 2 and a silicon layer 3, wherein the silicon germanium layer 2 is epitaxially grown on the silicon single crystal substrate 1 and the silicon layer 3 is epitaxially grown on the silicon germanium layer 2.

Here, the film thickness of the silicon germanium layer 2 and the germanium concentration of the silicon germanium layer 2 must satisfy the above formula 1. As long as the formula 1 is satisfied, the heteroepitaxial growth wafer will not capture metal impurities.

Furthermore, as long as the epitaxially grown wafer does not capture metal impurities even when subjected to device heat treatment, the device characteristics can be prevented from being deteriorated due to the capture of metal impurities even when subjected to heat treatment for device manufacturing.

Here, the process of discovering Formula 1 is described in detail.

(Experiment 1) On a p-type silicon substrate with a diameter of 300 mm and a resistivity of 10Ω･cm, a silicon germanium layer was epitaxially grown with a target film thickness of 50 nm and a target germanium concentration of 15, 20, and 30%, and then a silicon layer with a film thickness of 50 nm was epitaxially grown.

Subsequently, X-ray topography was used for evaluation and no mismatch was confirmed on any of the wafers after the epitaxial growth step.

After that, the back side of each wafer was contaminated with nickel (Ni) as a metal impurity, and then a heat treatment of 850°C/11 minutes/N ₂ was applied. The 850°C/11 minutes was set as the time for nickel to fully diffuse to the thickness of the wafer (775 μm) based on the diffusion coefficient of nickel.

After that, the concentration distribution of germanium and nickel in the depth direction was measured by SIMS from the epitaxial growth layer side of each wafer. The results are shown in Figure 2. The three graphs in Figure 2 show the cases with target germanium concentrations of 15, 20, and 30% from the left. The horizontal axis of Figure 2 represents the depth from the epitaxial growth layer side, and the vertical axis represents the nickel concentration on the left and the germanium concentration on the right.

In Figure 2, the part where the germanium concentration rises sharply at a depth of 50 nm is located at the interface between the silicon layer and the silicon germanium layer, and the part where the germanium concentration drops sharply at a depth of 100 nm is located at the interface between the silicon germanium layer and the silicon substrate. It can be seen in either graph that the nickel concentration increases at the position of each interface and nickel is trapped at the interface.

Therefore, the criterion for determining whether nickel has been captured is whether a concentration above the detection limit is detected by SIMS analysis.

(Experiment 2) In addition, on a p-type silicon substrate with a diameter of 300 mm and a resistivity of 10Ω･cm, epitaxial growth was performed with a silicon germanium layer having a target film thickness of 20, 60, 130, and 140 nm and a target germanium concentration of 10 and 20%, and then a silicon layer having a film thickness of 50 nm was epitaxially grown.

Subsequently, X-ray topography was used for evaluation, and no mismatched rows were confirmed on any of the wafers at the stage after the epitaxial growth step.

After that, each wafer was contaminated with nickel from the back side, and then subjected to a heat treatment of 850°C/11 minutes/N _2. The 850°C/11 minutes was the same as in Experiment 1, and was set to be a time that allowed nickel to sufficiently diffuse to the thickness of the wafer (775 μm) based on the diffusion coefficient of nickel.

Afterwards, SIMS was used to measure the concentration distribution of germanium and nickel in the depth direction from the epitaxial growth layer side of each wafer. The results are shown in Figure 3. The four graphs in Figure 3 show the cases where the film thickness of the silicon germanium layer is 20, 60, 130, and 140 nm, respectively, from the left, and the target germanium concentration is 20%. The horizontal axis of Figure 3 represents the depth from the epitaxial growth layer side, and the vertical axis represents the nickel concentration on the left and the germanium concentration on the right.

As shown in Figure 3, when the target germanium concentration is 20%, nickel is captured when the silicon germanium layer is thicker than 60 nm and the part where the germanium concentration drops sharply (the interface between the silicon germanium layer and the silicon substrate). However, when the germanium concentration is 10% (not shown), nickel is not captured even when the silicon germanium layer is 140 nm thick.

By carrying out the above experiments 1 and 2, it is possible to determine the germanium concentration and film thickness conditions of the silicon germanium layer that do not capture nickel after the device is heat treated. Specifically, as shown in FIG. 4, the germanium concentration and film thickness of the silicon germanium layer that have been tested are plotted, and the condition that captures nickel is marked as ×, and the condition that does not capture nickel is marked as 0, and Formula 1 is obtained as a formula representing the boundary condition. That is, as long as the germanium concentration and film thickness of the silicon germanium layer satisfy Formula 1, it will be shown that a device that does not capture nickel after the device is heat treated can be manufactured.

(Experiment 3) In addition, for a p-type silicon substrate with a diameter of 300 mm and a resistivity of 10Ω･cm, epitaxial growth was performed with a target film thickness of 50 nm and a target germanium concentration of 20%, and then a silicon layer with a film thickness of 50 nm was epitaxially grown. The second critical film thickness of the silicon germanium layer obtained based on Formula 1 at this time was 20 nm.

Subsequently, X-ray topography was used for evaluation, and no mismatched rows were confirmed on any of the wafers at the stage after the epitaxial growth step.

After that, each wafer was contaminated with nickel from the back side, and then subjected to three different additional heat treatments: 650°C/30 minutes/ _N2 , 850°C/11 minutes/ _N2 , and 1000°C/6 minutes/ _N2 . The heat treatment time at each temperature was set to a time that allowed nickel to diffuse sufficiently to the thickness of the wafer (775 μm) based on the diffusion coefficient of nickel.

Afterwards, the concentration distribution of germanium and nickel in the depth direction was measured from the epitaxial growth layer side of each wafer using SIMS. The results are shown in Figure 5. The three graphs in Figure 5 show the conditions of the additional heat treatments of 650°C/30 minutes/ _N2 , 850°C/11 minutes/ _N2 , and 1000°C/6 minutes/ _N2 , from the left. The horizontal axis of Figure 5 represents the depth from the epitaxial growth layer side, and the vertical axis represents the nickel concentration on the left and the germanium concentration on the right.

As shown in Figure 5, under any heat treatment condition, the nickel concentration increases at the location where the germanium concentration rises suddenly (the interface between the silicon layer and the silicon germanium layer) and the location where the germanium concentration drops suddenly (the interface between the silicon germanium layer and the silicon substrate), and nickel is captured at the interface. This is because the film thickness of the silicon germanium layer of 50 nm is greater than the second critical film thickness of 20 nm (that is, it does not satisfy Formula 1).

On the other hand, when the same experiment was performed with the target film thickness of the silicon germanium layer being 15 nm and the target germanium concentration being 20%, nickel was not captured at any heat treatment temperature. Figure 6 shows the case of 850°C/11 minutes/N _2. In addition, the same results were obtained under other conditions (650°C/30 minutes/N ₂ , 1000°C/6 minutes/N ₂ ). This is because the film thickness of the silicon germanium layer of 15 nm is smaller than the second critical film thickness of 20 nm (i.e., it satisfies Formula 1).

Based on the above, it can be seen that regardless of the difference in additional heat treatment conditions, Formula 1 is valid.

(Experiment 4) In addition, the situation of metal impurities other than nickel (cobalt (Co), copper (Cu), titanium (Ti), and molybdenum (Mo)) was also investigated. For a p-type silicon substrate with a diameter of 300 mm and a resistivity of 10Ω･cm, epitaxial growth was performed with a target film thickness of 50 nm for the silicon germanium layer and a target germanium concentration of 30%, and then a silicon layer with a film thickness of 50 nm was epitaxially grown. The second critical film thickness of the silicon germanium layer obtained based on Formula 1 at this time was 3 nm.

Subsequently, X-ray topography was used for evaluation, and no mismatched rows were confirmed on any of the wafers at the stage after the epitaxial growth step.

Thereafter, additional heat treatment was applied to the contamination with cobalt and copper from the back side of the wafer at 850°C for a time sufficient for each diffusion length to diffuse to the thickness of the wafer.

Similar experiments were conducted on titanium and molybdenum. However, since these elements diffuse more slowly, the contamination was carried out from the front side instead of the back side, and then the heat treatment at 850°C was performed.

Afterwards, SIMS was used to measure the concentration distribution of germanium and various metal impurities in the depth direction from the epitaxial growth layer side of each wafer. The results are shown in Figure 7. The four graphs in Figure 7 respectively show the situation where the metal impurities are cobalt, copper, titanium, and molybdenum. The horizontal axis of Figure 7 represents the depth from the epitaxial growth layer side, and the vertical axis represents the metal impurity concentration on the left side and the germanium concentration on the right side.

As shown in Figure 7, in the case of any metal impurity, the concentration of the metal impurity increases at the location where the germanium concentration rises sharply (the interface between the silicon layer and the silicon germanium layer) and the location where the germanium concentration drops sharply (the interface between the silicon germanium layer and the silicon substrate), and any metal impurity is captured. This is because the film thickness of the silicon germanium layer of 50 nm is thicker than the second critical film thickness of 3 nm (that is, it does not satisfy Formula 1).

On the other hand, when the same experiment was carried out with the target film thickness of the silicon germanium layer being 15 nm and the target germanium concentration being 20%, no metal impurities were captured. The case where the metal impurity was nickel was the same as Figure 6 of the above-mentioned Experiment 3. In addition, the same results were also shown when the metal impurities were cobalt, copper, titanium, and molybdenum. This is because: at this time, the second critical film thickness of the silicon germanium layer calculated based on Formula 1 is 20 nm, and the film thickness of the silicon germanium layer of 15 nm is smaller than the second critical film thickness of 20 nm (that is, Formula 1 is satisfied).

Based on the above, the effectiveness of formula 1 is shown. As long as the film thickness and germanium concentration of the silicon germanium layer satisfy formula 1, a heteroepitaxial growth wafer that does not capture metal impurities can be produced. In addition, as mentioned above, even if the heat treatment temperature or the type of metal impurities is changed, formula 1 is still effective.

As mentioned above, in the past (e.g., Patent Document 1) it was possible to determine the conditions (first critical film thickness) for forming a silicon germanium layer that does not generate mismatch dislocations during the epitaxial growth step. In contrast, in the present invention, it is possible to determine the conditions (second critical film thickness) for forming a silicon germanium layer that does not capture metal impurities based on Formula 1.

By using Formula 1, it is possible to prevent the capture of metal impurities due to mismatch dislocations in a heteroepitaxially grown wafer that has been subjected to heat treatment in the device step. That is, by forming the silicon germanium layer in a manner that satisfies the conditions of Formula 1, metal impurities will not be captured even when heat treatment is applied in the device step, thereby preventing the device characteristics from being deteriorated.

Here, the film thickness of the silicon germanium layer is preferably 3 nm or more. Thus, for example, when manufacturing a GAA structure for suppressing the short channel effect, the film thickness of the silicon germanium layer can be made the same as the thickness of the electrode metal region around the channel (3 nm or more), and the GAA structure can be manufactured without any problem.

Furthermore, the germanium concentration is preferably 10% or more. This can greatly increase the difference in etching rate between the silicon germanium layer and the silicon layer. For example, when the silicon layer is used as a channel layer, the silicon germanium layer can be easily removed by etching.

At this time, the higher the germanium concentration in the silicon germanium layer, the lower the growth rate, and the thickness that can be formed in actual time will also become thinner. Considering this point, it is better to have a silicon germanium layer thickness of 140 nm or less and a germanium concentration of 30% or less.

Based on the above, for example, the film thickness of the silicon germanium layer can be set to 3 to 140 nm.

In addition, the germanium concentration can be set to 10 to 30%.

Furthermore, although not shown, it is more preferable that the aforementioned silicon germanium layer and the aforementioned silicon layer are formed in a plurality of sets. This will prevent metal impurities from being captured at the interface between the respective silicon germanium layer and the silicon layer, and even the most advanced technology device such as the GAA structure formed by stacking a plurality of sets of silicon germanium layers and silicon layers can be easily applied and can be made to not capture metal impurities.

As described above, the present invention can reliably manufacture a heteroepitaxial growth wafer that does not capture impurities at the interface even when subjected to device heat treatment by setting it as a manufacturing method for heteroepitaxial growth wafers. The heteroepitaxial growth wafer is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the aforementioned silicon germanium layer, respectively. In the manufacturing method, the aforementioned silicon germanium layer is epitaxially grown, and the relationship between the film thickness (film thickness) of the aforementioned silicon germanium layer and the germanium concentration (Ge (%)) of the aforementioned silicon germanium layer becomes film thickness (nm) < 1.4 × 10 ⁷ × [Ge (%)] ^-4.5 . [Example]

The present invention is described in detail below with reference to the following embodiments, but the present invention is not limited to these embodiments.

[Example 1] A silicon germanium layer was formed on a silicon single crystal substrate with a diameter of 300 nm, n-type and a resistivity of 10Ω･cm, in a manner that satisfies the conditions of Formula 1, with a target germanium concentration of 20% and a target film thickness of 5 nm. The second critical film thickness calculated based on Formula 1 using this germanium concentration is 20 nm. After that, the back side was contaminated with nickel and a heat treatment of 850℃/11 minutes/ _N2 was applied, and the concentration analysis of germanium and nickel in the depth direction was performed from the front side using SIMS. As a result, no nickel capture was confirmed. This is because the film thickness of the silicon germanium layer, 5 nm, is smaller than the second critical film thickness of 20 nm (that is, it satisfies Formula 1).

[Example 2] A silicon germanium layer was formed on a silicon single crystal substrate with a diameter of 300 nm, n-type and a resistivity of 10Ω･cm, with a target germanium concentration of 10% and a target film thickness of 110 nm. The second critical film thickness calculated based on this germanium concentration and formula 1 was 440 nm. After that, the back side was contaminated with nickel and heat treated at 850℃/11 minutes/ _N2 , and the concentration of germanium and nickel in the depth direction was analyzed by SIMS from the front side. As a result, no nickel capture was confirmed. This is because the film thickness of the silicon germanium layer, 110 nm, is smaller than the second critical film thickness, 440 nm (ie, it satisfies Formula 1).

[Example 3] For a silicon single crystal substrate with a diameter of 300 nm, n-type and a resistivity of 10Ω･cm, a silicon germanium layer was formed under the conditions of a target germanium concentration of 15% and a target film thickness of 12 nm. The germanium concentration and film thickness in this case will be below the first critical film thickness of film formation at 900°C in the past (Patent Document 1), and no mismatch dislocation will occur after the heteroepitaxial growth step. In addition, the second critical film thickness calculated based on Formula 1 using this germanium concentration is 71 nm.

After that, the back side was contaminated with nickel and heat treated at 850℃/11min/ _N2 , and the concentration of germanium and nickel in the depth direction was analyzed by SIMS from the front side. As a result, no nickel capture was confirmed. This is because the film thickness of the silicon germanium layer of 12nm is smaller than the second critical film thickness of 71nm (that is, it satisfies formula 1).

[Comparative Example 1] For a silicon single crystal substrate with a diameter of 300 nm, n-type and a resistivity of 10Ω･cm, a silicon germanium layer was formed under the conditions of a target germanium concentration of 25% and a target film thickness of 30 nm. The germanium concentration and film thickness in this case will be below the first critical film thickness of film formation at 550°C in the past (Patent Document 1), and no mismatch dislocation will occur after the heteroepitaxial growth step. In addition, the second critical film thickness calculated based on Formula 1 using this germanium concentration is 7 nm.

After that, the back side was contaminated with nickel and heat treated at 850℃/11min/ _N2 , and the concentration of germanium and nickel in the depth direction was analyzed by SIMS from the front side. The result showed that nickel was captured. This is because the film thickness of the silicon germanium layer of 30nm is larger than the second critical film thickness of 7nm (that is, it does not satisfy Formula 1).

Here, regarding the mechanism of capturing nickel (metal impurities) when Formula 1 is not satisfied, the reason is presumed to be as follows: the strain energy generated between the silicon germanium layer and the silicon layer changes into dislocations during the heat treatment at 850°C, and the dislocations appear as capture sites for metal impurities.

Based on the above, it is shown that Examples 1 to 3 that meet the present invention do not capture nickel (metal impurities), and Comparative Example 1 that does not meet Formula 1 captures nickel (metal impurities).

The present invention includes the following aspects. [1] A heteroepitaxial growth wafer, which is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer, respectively, wherein the heteroepitaxial growth wafer is characterized in that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is: film thickness (nm) < 1.4 × 10 ⁷ × [Ge (%)] ^-4.5 . [2] The heteroepitaxial growth wafer as described in [1] above, wherein even if the heteroepitaxial growth wafer is subjected to a device heat treatment, no impurities are captured at any of the interfaces between the silicon single crystal substrate and the silicon germanium layer and the interfaces between the silicon germanium layer and the silicon layer. [3] The heteroepitaxial growth wafer as described in [1] or [2] above, wherein the film thickness of the silicon germanium layer is 3 to 140 nm and the germanium concentration is 10 to 30%. [4] The heteroepitaxial growth wafer as described in any one of [1] to [3] above, wherein the silicon germanium layer and the silicon layer are formed in a plurality of sets. [5] A method for manufacturing a heteroepitaxial growth wafer, wherein the heteroepitaxial growth wafer is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer, respectively. The manufacturing method is characterized in that the silicon germanium layer is epitaxially grown so that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer is film thickness (nm) < 1.4×10 ⁷ × [Ge (%)] ^-4.5 .

Furthermore, the present invention is not limited to the above-mentioned embodiments. The above-mentioned embodiments are illustrative only, and all those having substantially the same configuration as the technical concept described in the scope of the patent application of the present invention and being able to exert the same function and effect are all included in the technical scope of the present invention.

1: Silicon single crystal substrate 2: Silicon germanium layer 3: Silicon layer

FIG. 1 is a schematic diagram of a heteroepitaxial growth wafer in an embodiment of the present invention. FIG. 2 is a graph showing the distribution of the germanium concentration and the nickel concentration in the depth direction after heat treatment when the germanium concentration of the silicon germanium layer is different. FIG. 3 is a graph showing the distribution of the germanium concentration and the nickel concentration in the depth direction after heat treatment when the film thickness of the silicon germanium layer is different. FIG. 4 is a graph showing the relationship between the germanium concentration and the film thickness of the silicon germanium layer for not capturing nickel after heat treatment. FIG. 5 is a graph showing the distribution of the germanium concentration and the nickel concentration in the depth direction after heat treatment when the heat treatment temperature is different. FIG. 6 is a graph showing the depth distribution of the germanium concentration and the nickel concentration after heat treatment with a target film thickness of 15 nm for the silicon germanium layer and a target germanium concentration of 20%. FIG. 7 is a graph showing the depth distribution of the germanium concentration and the metal impurity concentration after heat treatment under different metal impurities.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

1: Silicon single crystal substrate

2: Silicon germanium layer

3: Silicon layer

Claims (5)

A heteroepitaxial growth wafer is formed by epitaxially growing a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer, respectively. The heteroepitaxial growth wafer is characterized in that the relationship between the film thickness of the silicon germanium layer (film thickness) and the germanium concentration (Ge (%)) of the silicon germanium layer is film thickness (nm) < 1.4×10 ⁷ × [Ge (%)] ^-4.5 . The heteroepitaxial growth wafer as described in claim 1 is a wafer in which no impurities are captured at any of the interfaces between the silicon single crystal substrate and the silicon germanium layer and the interfaces between the silicon germanium layer and the silicon layer even if the heteroepitaxial growth wafer is subjected to device heat treatment. The heteroepitaxial growth wafer as described in claim 1, wherein the film thickness of the silicon germanium layer is 3 to 140 nm, and the germanium concentration is 10 to 30%. The heteroepitaxial growth wafer as described in any one of claims 1 to 3, wherein the silicon germanium layer and the silicon layer are formed in a plurality of sets. A method for manufacturing a heteroepitaxially grown wafer, wherein a silicon germanium layer on a silicon single crystal substrate and a silicon layer on the silicon germanium layer are epitaxially grown separately. The manufacturing method is characterized in that the silicon germanium layer is epitaxially grown so that the relationship between the film thickness (film thickness) of the silicon germanium layer and the germanium concentration (Ge (%)) of the silicon germanium layer becomes film thickness (nm) < 1.4×10 ⁷ × [Ge (%)] ^-4.5 .