TW202507815A - Semiconductor structure and method for forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor structure, including: an epitaxial layer with a trench; a dielectric spacer layer disposed in the trench; a conductive filling layer disposed on the dielectric spacer layer and including a dopant; a gate dielectric layer disposed on the conductive filling layer; and a gate electrode layer disposed in the trench and separated from the conductive filling layer by the gate electric layer, wherein the dopant has a gradient doping concentration in the conductive filling layer.

Description

Semiconductor structure and method for forming the same

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a dopant with a gradient doping concentration in a conductive filling layer.

In recent years, the semiconductor industry has made significant progress in the development of power devices. Currently, a variety of power devices have been developed, such as high voltage metal-oxide-semiconductor (HVMOS) transistors, insulated gate bipolar transistors (IGBT), junction field effect transistors (JFET), and Schottky barrier diodes (SBD). These devices are usually used in power amplification, power control and other applications in power systems of household appliances, communication equipment and automotive generators.

In existing metal oxide semiconductor transistor designs, the on-resistance of the transistor can be reduced by using a trench transistor structure. In addition, by forming a transistor including a split-gate, the parasitic capacitance of the semiconductor device can be reduced to reduce switching loss. However, in the structure of the split-gate transistor formed by the conventional process, the thickness of the oxide between the source polysilicon and the gate polysilicon, that is, the thickness of the inter-poly oxide (IPO), cannot be independently controlled.

Specifically, the oxide is grown simultaneously on the top surface of the epitaxial layer, the sidewalls of the trench, the sidewalls of the polysilicon, and the top surface of the polysilicon, and the thickness of the oxide on each part of these surfaces is related to each other and has a specific proportional relationship. The thickness of the oxide on these surfaces will affect the device size and electrical performance, and the oxide on the sidewalls and top surface of the source polysilicon will become the inter-polysilicon oxide. If a thinner oxide layer is deposited in order to maintain the turn-on resistance (R _ON ) and critical voltage (V _th ) within a specific range, the inter-polysilicon oxide may be too thin, resulting in a risk of short circuit or breakdown between the source polysilicon and the gate polysilicon. On the other hand, if a thicker inter-polysilicon oxide is formed, the oxides in other parts will also become thicker, affecting the device size and electrical performance.

In summary, although existing trench transistors can generally meet their original intended uses, they still do not fully meet the needs in all aspects. For example, how to increase the thickness of the inter-polysilicon oxide without affecting the size and electrical performance of semiconductor devices is still a topic that the industry is committed to studying. Therefore, the research and development of trench transistors requires continuous updates and adjustments to solve various problems faced by the manufacture of semiconductor devices.

A semiconductor structure includes: an epitaxial layer having a trench; a dielectric spacer layer disposed in the trench; a conductive filling layer disposed on the dielectric spacer layer and including a dopant; a gate dielectric layer disposed on the conductive filling layer; and a gate electrode layer disposed in the trench and separated from the conductive filling layer by the gate dielectric layer, wherein the dopant has a gradient doping concentration in the conductive filling layer.

A method for forming a semiconductor structure includes: forming a dielectric spacer layer in a trench of an epitaxial layer; forming a conductive filling layer in the trench; performing a doping process so that the conductive filling layer includes a dopant; forming a gate dielectric layer on the conductive filling layer; and forming a gate electrode layer in the trench, wherein the gate electrode layer is separated from the conductive filling layer by the gate dielectric layer, wherein the dopant has a gradient doping concentration in the conductive filling layer.

The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, to facilitate description of the relationship between one element or component and another element or component in the drawings, spatially relative terms may be used, such as "under," "below," "lower," "above," "upper," and the like. In addition to the orientations depicted in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (e.g., rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

As used herein, the term "substantially" means that a given amount of value may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that a given amount of value is within a range of, for example, ±5% of a target (or desired) value.

The present disclosure provides a semiconductor structure including a separated gate structure and a method for forming the same. The semiconductor structure formed by such a method has a gradient doping concentration distribution in the conductive filling layer of the separated gate structure, so that the resistance value of the conductive filling layer varies in the vertical direction. In addition, by the formation method disclosed in the present disclosure, the thickness of the gate dielectric layer between the conductive layers of the separated gate structure can be freely controlled without affecting the thickness of the gate dielectric layer located on the top surface of the epitaxial layer and the sidewall of the trench. In this way, the size and electrical performance of the semiconductor device can be maintained, and the risk of short circuit or collapse in the split gate structure can be reduced.

FIG. 1 is a cross-sectional view of a semiconductor structure 10 including a vertical split gate structure according to some embodiments of the present disclosure. The semiconductor structure 10 may include an epitaxial layer 100 having a trench 100T and a dielectric spacer layer 110 disposed in the trench 100T. The semiconductor structure 10 may further include a conductive filling layer 120 disposed on the dielectric spacer layer 110 and including a dopant, and the dopant may have a gradient doping concentration in the conductive filling layer 120. It should be understood that the so-called gradient doping concentration means that the dopant has a gradient concentration distribution in the conductive filling layer 120. The semiconductor structure 10 may further include a gate dielectric layer 130 disposed on the conductive filling layer 120 . In addition, the semiconductor structure 10 may further include a gate electrode layer 140 disposed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate dielectric layer 130 .

The epitaxial layer 100 may be disposed on a substrate (not shown). In some embodiments, the substrate is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, the substrate is formed of silicon, germanium, other suitable semiconductor materials, or a combination thereof. For example, in a specific embodiment, the substrate includes silicon. In some embodiments, the substrate may include a compound semiconductor, such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, other suitable semiconductor materials, or a combination thereof. In some embodiments, the substrate may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, other suitable materials, or a combination thereof. In some embodiments, the substrate may be composed of multiple layers of materials, such as multiple layers of silicon/silicon germanium, silicon/silicon carbide.

In some embodiments of the present disclosure, for example, the substrate is a doped wafer doped with a first conductivity type, and the first conductivity type is n-type. In some other embodiments, the first conductivity type may also be p-type. In the case where the first conductivity type is n-type, the dopant having the first conductivity type may be, for example, nitrogen, phosphorus, arsenic, antimony, and bismuth. In the case where the first conductivity type is p-type, the dopant having the first conductivity type may be, for example, boron, aluminum, gallium, indium, and bismuth. In some embodiments, the doping concentration of the substrate may be between about 1e19 atoms/cm ³ and about 1e21 atoms/cm ³ .

The epitaxial layer 100 may include the same or similar material as the substrate, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or combinations thereof. In some embodiments, the substrate and the epitaxial layer 100 have the same conductivity type (e.g., n-type), and the substrate and the epitaxial layer 100 may include the same dopant. In some embodiments, the doping concentration of the above dopant in the epitaxial layer 100 is less than the doping concentration in the substrate. In some embodiments, the doping concentration of the epitaxial layer 100 may be between about 1e13 atoms/cm ³ and about 1e18 atoms/cm ³ . In some embodiments of the present disclosure, for example, the epitaxial layer 100 includes silicon carbide. By forming the epitaxial layer 100 with silicon carbide, the epitaxial layer 100 can be doped with a dopant that is suitable for the energy band range of silicon carbide and has a lower activation energy. In addition, the epitaxial layer 100 formed of silicon carbide can provide a higher breakdown voltage, a lower leakage current, and a lower on-resistance.

As shown in FIG. 1 , a dielectric spacer 110 and a conductive filling layer 120 may be disposed in a trench 100T of an epitaxial layer 100. The dielectric spacer 110 may extend between the conductive filling layer 120 and the epitaxial layer 100. The material of the dielectric spacer 110 may include silicon oxide, tantalum oxide, zirconia, aluminum oxide, aluminum dioxide tantalum alloy, silicon dioxide tantalum, silicon oxynitride tantalum oxide, tantalum oxide, titanium oxide, zirconia oxide, other suitable high-k dielectric materials, or a combination thereof. In some embodiments, the dielectric spacer 110 includes an oxide having an element in common with the epitaxial layer 100. For example, in one particular embodiment, the epitaxial layer 100 includes silicon or silicon carbide, and the dielectric spacer layer 110 includes silicon oxide.

In some embodiments, the doping concentration of the above-mentioned dopant is higher in the upper part of the conductive filling layer 120 than in the lower part of the conductive filling layer 120. The present disclosure does not limit the types of the above-mentioned dopant, and a person skilled in the art can decide which dopant to use according to design requirements. The conductivity type of the above-mentioned dopant can be n-type or p-type. In the case where the conductivity type of the above-mentioned dopant is n-type, the above-mentioned dopant can be, for example, nitrogen, phosphorus, arsenic, antimony, and bismuth. In the case where the conductivity type of the above-mentioned dopant is p-type, the above-mentioned dopant can be, for example, boron, aluminum, gallium, indium, and bismuth. The material of the conductive filling layer 120 can include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination of the foregoing.

As shown in FIG. 1 , the gate dielectric layer 130 and the gate electrode layer 140 may also be disposed in the trench 100T of the epitaxial layer 100. In some embodiments, as shown in FIG. 1 , the gate electrode layer 140 includes an extension 142 extending between the sidewall of the conductive filling layer 120 and the sidewall of the trench 100T. As shown in FIG. 1 , the bottom surface of the gate electrode layer 140 (e.g., the bottom surface of the extension 142) may be lower than the top surface of the conductive filling layer 120. However, in some other embodiments, the extension 142 does not extend between the sidewall of the conductive filling layer 120 and the sidewall of the trench 100T. In still other embodiments, the gate electrode layer 140 does not have the extending portion 142 extending downward and has a flat bottom surface.

In some embodiments, as shown in FIG. 1 , the gate dielectric layer 130 surrounds the gate electrode layer 140 so that the gate electrode layer 140 is separated from the dielectric spacer layer 110 and the epitaxial layer 100. The gate dielectric layer 130 may extend between the gate electrode layer 140 and the conductive filling layer 120, between the gate electrode layer 140 and the dielectric spacer layer 110, and further between the gate electrode layer 140 and the epitaxial layer 100.

Specifically, as shown in FIG. 1 , the gate dielectric layer 130 may include a lateral portion extending laterally between the top surface of the conductive filling layer 120 and the bottom surface of the gate electrode layer 140. In some embodiments, the thickness of the lateral portion is greater than the thickness of the portion of the gate dielectric layer 130 covering the sidewall of the trench 100T (e.g., the second thickness T2 in FIG. 1 ). In some embodiments, the width of the gate electrode layer 140 is greater than the width of the conductive filling layer 120. The gate dielectric layer 130 may have a first thickness T1 between the conductive filling layer 120 and the sidewall of the gate electrode layer 140 (eg, the sidewall of the extension 142 ) and a second thickness T2 between the gate electrode layer 140 and the sidewall of the trench 100T, and the first thickness T1 may be greater than the second thickness T2.

The gate dielectric layer 130 may include a material that is the same as or similar to the dielectric spacer layer 110. For example, the material of the gate dielectric layer 130 may include silicon oxide, tantalum oxide, zirconia, aluminum oxide, aluminum dioxide tantalum alloy, silicon dioxide tantalum, silicon tantalum oxynitride, tantalum tantalum oxide, titanium tantalum oxide, zirconia tantalum oxide, other suitable high-k dielectric materials, or a combination thereof. The gate electrode layer 140 may include a material that is the same as or similar to the conductive fill layer 120. For example, the material of the gate electrode layer 140 may include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination thereof.

It should be understood that the portion of the semiconductor structure 10 including the epitaxial layer 100, the dielectric spacer layer 110, the conductive filling layer 120, the gate dielectric layer 130, and the gate electrode layer 140 can be referred to as a separated gate structure. In particular, since the conductive filling layer 120 and the gate electrode layer 140 of the semiconductor structure 10 overlap in the vertical direction of the semiconductor structure 10, the separated gate structure of the semiconductor structure 10 can be referred to as a vertical separated gate structure. The formation method of the vertical separated gate structure will be described below with reference to FIGS. 3A to 3F and FIGS. 4A to 4G.

3A to 3F are cross-sectional views showing various stages of a method for forming a vertical split gate structure according to some embodiments of the present disclosure.

First, the epitaxial layer 100 may be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown). The epitaxial layer 100 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

The process for forming the trench 100T may include, for example, a patterning process. A patterned shielding layer (not shown) (e.g., positive/negative photoresist, hard mask, etc.) is formed on the epitaxial layer 100 before patterning. The patterned shielding layer may be formed by forming a shielding layer (not shown) on the epitaxial layer 100 (e.g., by a spin coating process), exposing the shielding layer to a pattern (e.g., by a lithography process, such as photolithography, extreme ultraviolet lithography, etc.), and developing the shielding layer. Thereafter, after the patterned shielding layer is in place, an etching process is performed on the epitaxial layer 100 according to the patterned shielding layer.

The etching process can remove the unshielded portion of the epitaxial layer 100, thereby forming the trench structure 100T. In some embodiments, the etching process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. Then, the patterned shielding layer can be peeled off.

3A , a dielectric spacer layer 110 may be formed in the trench 100T of the epitaxial layer 100 , and a conductive filling layer 120 may be formed in the trench 100T. Specifically, the dielectric spacer layer 110 may be deposited over the epitaxial layer 100 and in the trench 100T, and the conductive filling layer 120 may be formed on the dielectric spacer layer 110 .

In some embodiments, the dielectric spacer layer 110 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sol-gel method, spin coating, other suitable methods, or a combination thereof. The conductive filler layer 120 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof.

Next, referring to FIG. 3B , the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing a removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

After partially removing the dielectric spacer layer 110, a doping process 1000 is performed to make the conductive fill layer 120 include a dopant. The types of dopants are as discussed previously, and a detailed description thereof is omitted here for simplicity. The doping process 1000 is an ion implantation process. After performing the doping process 1000, the dopant has a gradient doping concentration in the conductive fill layer 120. For example, in some embodiments, the dopant has a gradient concentration distribution in the upper portion of the conductive fill layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive fill layer 120 increases. In some embodiments, the doping process 1000 includes introducing dopants into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120. For example, when the doping process 1000 is an ion implantation process, ions in a dopant source may be doped into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120.

After performing the doping process 1000, referring to FIG. 3C , the dielectric spacer layer 110 is partially removed to expose a portion of the sidewall of the trench 100T. In some embodiments, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 is also removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above-mentioned removal process, the exposed area of the sidewall of the conductive filling layer 120 can be further increased, as shown in FIG. 3C . The above-mentioned removal process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

Next, referring to FIG. 3D , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive fill layer 120 may be thicker than other portions of the gate dielectric layer 130. The gate dielectric layer 130 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

Next, referring to FIGS. 3E and 3F , a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140′ on the gate dielectric layer 130 and performing an etching process on the conductive material 140′ to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

Since the dopant can have a higher concentration on the upper portion of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and/or side surface of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other portions is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the portion between the conductive filling layer 120 and the gate electrode layer 140 can be maintained at a certain thickness or above. In other words, the vertical separated gate structure formed by the method of the above embodiment can reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

FIGS. 4A to 4G are cross-sectional views of various stages of a method for forming a vertical split gate structure according to some other embodiments of the present disclosure.

Similar to the embodiment of the formation method shown in FIGS. 3A to 3F, first, the epitaxial layer 100 having the trench 100T can be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown) and performing a patterning process. Next, referring to FIG. 4A, a dielectric spacer layer 110 can be formed in the trench 100T of the epitaxial layer 100, and a conductive filling layer 120 can be formed in the trench 100T. Specifically, the dielectric spacer layer 110 can be deposited above the epitaxial layer 100 and in the trench 100T, and the conductive filling layer 120 can be formed on the dielectric spacer layer 110. The formation methods of the epitaxial layer 100, the dielectric spacer layer 110, and the conductive filling layer 120 may be the same as or similar to the embodiments shown in FIGS. 3A to 3F, and the detailed description thereof is omitted for simplicity.

Next, referring to FIG. 4B , the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing a removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

After partially removing the dielectric spacer layer 110, a doping process 2000 is performed to make the conductive filling layer 120 include a dopant. The doping process 2000 includes performing thermal diffusion using a precursor for the conductive filling layer 120. In a specific embodiment, the doping process 2000 may include performing thermal diffusion using a phosphorus-containing precursor. The phosphorus-containing precursor may include, for example, POCl ₃ . After performing the doping process 2000, the dopant has a gradient doping concentration in the conductive filling layer 120. For example, in some embodiments, the dopant has a gradient concentration distribution at the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 2000 includes introducing the dopant into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120. For example, in the thermal diffusion of the doping process 2000, ions in the precursor may be doped into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120.

Since oxides including doping elements are generated on the top of the conductive filling layer 120, an etching process is required to remove the oxides to prevent the electrical performance of the separated gate structure from being affected. Refer to FIG. 4C. After the thermal diffusion process as the doping process 2000 is performed, a removal process can be performed on the top surface of the conductive filling layer 120 to remove the oxides. The etching process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. For example, in an embodiment where a phosphorus-containing precursor is used for thermal diffusion, the etching process forms a thinner phospho-silicate glass (PSG) layer near the top surface of the conductive fill layer 120. The phospho-silicate glass layer can be removed by, for example, a wet etching process using HF as an etchant or other suitable etching process. In some embodiments, as shown in FIG. 4C, the etching process also removes a portion of the dielectric spacer layer 110. For example, in some embodiments, a portion of the dielectric spacer layer located above the top surface of the epitaxial layer 100 is removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, the portion located on the sidewall of the trench 100T may also be thinned due to the etching process, leaving only a residual portion 112, as shown in FIG. 4C.

Next, referring to FIG. 4D , the dielectric spacer layer 110 is partially removed to expose a portion of the sidewall of the trench 100T. For example, the remaining portion 112 of the dielectric spacer layer 110 shown in FIG. 4C may be completely removed. In the case where there is still remaining dielectric spacer layer 110 above the top surface of the epitaxial layer 100, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 may also be removed together, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above-mentioned removal process, the exposed area of the sidewall of the conductive filling layer 120 may be further increased, as shown in FIG. 4D . The removal process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

Next, referring to FIG. 4E , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive fill layer 120 may be thicker than other portions of the gate dielectric layer 130. The gate dielectric layer 130 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

Next, referring to FIGS. 4F and 4G , a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140′ on the gate dielectric layer 130 and performing an etching process on the conductive material 140′ to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

Since the dopant can have a higher concentration on the upper portion of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and/or side surface of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other portions is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the portion between the conductive filling layer 120 and the gate electrode layer 140 can be maintained at a certain thickness or above. In other words, the vertical separated gate structure formed by the method of the above embodiment can also reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

1, in some embodiments, the epitaxial layer 100 includes a doped structure 150 that laterally surrounds the split gate structure. The doped structure 150 may include a doped well 152, a first heavily doped region 154, and a second heavily doped region 156. In some embodiments, a portion of the doped well 152 adjacent to the split gate structure can be used as a channel region when the semiconductor structure 10 is in operation. For example, when a forward bias is applied to the gate electrode layer 140, an inversion layer can be formed near the sidewall of the split gate structure adjacent to the doped well 152 to generate a current. The second heavily doped region 156 can be used to electrically connect the doped well 152 to an upper electrode layer (e.g., an upper electrode layer 170 formed later). The first heavily doped region 154 can be electrically connected to the source.

The first heavily doped region 154 may have the same first conductivity type (e.g., n-type) as the epitaxial layer 100, and the doped well 152 and the second heavily doped region 156 may have a second conductivity type (e.g., p-type). The doping concentration of the doped well 152 may be between about 1e15 atoms/cm ³ and about 1e18 atoms/cm ^3. The doping concentration of the first heavily doped region 154 may be between about 1e18 atoms/cm ³ and about 1e21 atoms/cm ^3. The doping concentration of the second heavily doped region 156 may be between about 1e18 atoms/cm ³ and about 1e21 atoms/cm ³ .

The doped structure 150 may include a material that is the same as or similar to the portion of the epitaxial layer 100 below the doped structure 150, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or a combination thereof. The doped structure 150 may be formed by performing a doping process on the epitaxial material used to form the epitaxial layer 100. In some embodiments, the top surface of the doped structure 150 is substantially coplanar with the top surface of the gate electrode layer 140.

In some embodiments, a capping layer 160 is formed on the split gate structure. Specifically, the capping layer 160 may be formed on the gate electrode layer 140. The material and formation method of the capping layer 160 may be the same as or similar to the dielectric spacer layer 110 or the gate dielectric layer 130, and a detailed description thereof is omitted for simplicity.

Next, as shown in FIG. 1 , an upper electrode layer 170 may be formed on the doped structure 150 and the capping layer 160 , and a lower electrode layer 180 may be formed under the epitaxial layer 100 .

The upper electrode layer 108 and the lower electrode layer 180 may include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), benzenium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), nimum (Os), thorium (Th), vanadium (V), some other metals or metal nitrides, or a combination of the foregoing.

The formation method of the upper electrode layer 170 and the lower electrode layer 180 may include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, sputtering, electrochemical plating, electroless plating, some other deposition processes, or a combination thereof.

FIG. 2 is a cross-sectional view of a semiconductor structure 20 including a lateral split gate structure according to some embodiments of the present disclosure. The semiconductor structure 20 may include an epitaxial layer 100 having a trench 100T and a dielectric spacer layer 110 disposed in the trench 100T. The semiconductor structure 20 may further include a conductive filling layer 120 disposed on the dielectric spacer layer 110 and including a dopant, and the dopant may have a gradient doping concentration in the conductive filling layer 120. The semiconductor structure 20 may further include a gate dielectric layer 130 disposed on the conductive filling layer 120. In addition, the semiconductor structure 20 may further include a gate electrode layer 140 disposed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate dielectric layer 130 .

It should be understood that the portion of the semiconductor structure 20 including the epitaxial layer 100, the dielectric spacer layer 110, the conductive filling layer 120, the gate dielectric layer 130, and the gate electrode layer 140 can be referred to as a separated gate structure. In particular, since the conductive filling layer 120 and the gate electrode layer 140 of the semiconductor structure 20 are arranged in the lateral direction of the semiconductor structure 20, the separated gate structure of the semiconductor structure 20 can be referred to as a lateral separated gate structure.

As shown in FIG. 2 , the dielectric spacer 110 and the conductive filling layer 120 may be disposed in the trench 100T of the epitaxial layer 100. The dielectric spacer 110 may extend between the conductive filling layer 120 and the epitaxial layer 100. The material of the dielectric spacer 110 may include silicon oxide, tantalum oxide, zirconia, aluminum oxide, aluminum dioxide tantalum alloy, silicon dioxide tantalum, silicon oxynitride tantalum oxide, tantalum oxide, titanium oxide, zirconia oxide, other suitable high-k dielectric materials, or a combination thereof. In some embodiments, the dielectric spacer 110 includes an oxide having an element in common with the epitaxial layer 100. For example, in one particular embodiment, the epitaxial layer 100 includes silicon or silicon carbide, and the dielectric spacer layer 110 includes silicon oxide.

In some embodiments, the doping concentration of the above-mentioned dopant is higher in the upper part of the conductive filling layer 120 than in the lower part of the conductive filling layer 120. The present disclosure does not limit the types of the above-mentioned dopant, and a person skilled in the art can decide which dopant to use according to design requirements. The conductivity type of the above-mentioned dopant can be n-type or p-type. In the case where the conductivity type of the above-mentioned dopant is n-type, the above-mentioned dopant can be, for example, nitrogen, phosphorus, arsenic, antimony, and bismuth. In the case where the conductivity type of the above-mentioned dopant is p-type, the above-mentioned dopant can be, for example, boron, aluminum, gallium, indium, and bismuth. The material of the conductive filling layer 120 can include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination of the foregoing.

As shown in FIG. 2 , the gate dielectric layer 130 and the gate electrode layer 140 may also be disposed in the trench 100T of the epitaxial layer 100 . In some embodiments, as shown in FIG. 1 , the gate dielectric layer 130 surrounds the gate electrode layer 140 , so that the gate electrode layer 140 is separated from both the dielectric spacer 110 and the epitaxial layer 100 . The gate dielectric layer 130 may extend between the gate electrode layer 140 and the conductive filling layer 120, may extend between the gate electrode layer 140 and the dielectric spacer layer 110, and may further extend between the gate electrode layer 140 and the epitaxial layer 100. In addition, the gate electrode layer 140 may be laterally divided into a plurality of parts by the conductive filling layer 120. For example, in the two separated gate structures illustrated in FIG. 2 , the conductive filling layer 120 in each separated gate structure may divide the gate electrode layer 140 into two parts in the lateral direction. In addition, as shown in FIG. 2 . The top surface of the gate electrode layer 140 may be lower than the top surface of the conductive filling layer 120. In other embodiments, the gate dielectric layer 140 may include a lateral portion extending laterally from the top surface of the conductive filling layer 120 (as shown in the subsequent FIG. 5F), and the top surface of the gate electrode layer 140 is lower than the top surface of the lateral portion. The gate dielectric layer 130 may have a first thickness T1 between the conductive filling layer 120 and the sidewall of the gate electrode layer 140 and a second thickness T2 between the gate electrode layer 140 and the sidewall of the trench 100T, and the first thickness T1 may be greater than the second thickness T2.

The gate dielectric layer 130 may include a material that is the same as or similar to the dielectric spacer layer 110. For example, the material of the gate dielectric layer 130 may include silicon oxide, tantalum oxide, zirconia, aluminum oxide, aluminum dioxide tantalum alloy, silicon dioxide tantalum, silicon tantalum oxynitride, tantalum tantalum oxide, titanium tantalum oxide, zirconia tantalum oxide, other suitable high-k dielectric materials, or a combination thereof. The gate electrode layer 140 may include a material that is the same as or similar to the conductive fill layer 120. For example, the material of the gate electrode layer 140 may include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination thereof.

It should be understood that since the semiconductor structure 10 and the semiconductor structure 20 include other identical or similar components and film layers (e.g., the doped structure 150, the capping layer 160, the upper electrode layer 170, and the lower electrode layer 180, etc.), these components and film layers can be formed with identical or similar materials and formation methods, and detailed descriptions are omitted for simplicity. The formation method of the lateral split gate structure will be described below with reference to FIGS. 5A to 5F.

5A to 5F are cross-sectional views of various stages of a method for forming a lateral split gate structure according to some embodiments of the present disclosure.

Similar to the embodiments of the formation method shown in FIGS. 3A to 3F and 4A to 4G, first, the epitaxial layer 100 having the trench 100T can be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown) and performing a patterning process. Next, referring to FIG. 5A , a dielectric spacer layer 110 can be formed in the trench 100T of the epitaxial layer 100, and a conductive filling layer 120 can be formed in the trench 100T. Specifically, the dielectric spacer layer 110 can be deposited above the epitaxial layer 100 and in the trench 100T, and the conductive filling layer 120 can be formed on the dielectric spacer layer 110. The formation method of the epitaxial layer 100, the dielectric spacer layer 110, and the conductive filling layer 120 may be the same or similar to the embodiment of the vertical split gate structure, and the detailed description thereof is omitted for simplicity. In addition, in some embodiments, during the process of forming the conductive filling layer 120, the conductive material is etched so that the top surface of the conductive filling layer 120 is substantially the same height as the epitaxial layer 100.

Next, referring to FIG. 5B , the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing a removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

After partially removing the dielectric spacer layer 110, a doping process 1000 as an ion implantation process or a doping process 2000 as a thermal diffusion process is performed to make the conductive filling layer 120 include dopants. The types of dopants are as discussed above, and a detailed description thereof is omitted here for simplicity.

In the case of performing the doping process 1000 as an ion implantation process, after performing the doping process 1000, the dopant has a gradient doping concentration in the conductive filling layer 120. For example, in some embodiments, the dopant has a gradient concentration distribution in the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 1000 includes introducing the dopant into the conductive filling layer 120 from the top surface and/or sidewall of the conductive filling layer 120. For example, when the doping process 1000 is performed as an ion implantation process, ions in the doping source may be doped into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120 .

In the case of performing the doping process 2000 as a thermal diffusion process, after performing the doping process 2000, the dopant has a gradient doping concentration in the conductive filling layer 120. In a specific embodiment, the doping process 2000 may include performing thermal diffusion using a phosphorus-containing precursor. The phosphorus-containing precursor may include, for example, POCl ₃ . For example, in some embodiments, the dopant has a gradient concentration distribution in the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 2000 includes introducing dopants into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120. For example, in the thermal diffusion of the doping process 2000, ions in the precursor may be doped into the conductive filling layer 120 from the top surface and/or the sidewall of the conductive filling layer 120.

Since oxides including doping elements are generated on the top of the conductive filling layer 120, an etching process is required to remove the oxides to prevent the electrical performance of the separated gate structure from being affected. After the thermal diffusion process as the doping process 2000 is performed, a removal process can be performed on the top surface of the conductive filling layer 120 to remove the oxides. The etching process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. For example, in an embodiment using a phosphorus-containing precursor for thermal diffusion, a thinner phosphosilicate glass (PSG) layer is formed near the top surface of the conductive fill layer 120. The phosphosilicate glass layer can be removed by, for example, a wet etching process using HF as an etchant or other suitable etching process. In some embodiments, the etching process also removes a portion of the dielectric spacer layer 110. For example, in some embodiments, a portion of the dielectric spacer layer located above the top surface of the epitaxial layer 100 is removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, the portion located on the sidewall of the trench 100T may also be thinned due to the etching process.

After the doping process 1000 is performed, referring to FIG. 5C , the dielectric spacer layer 110 is partially removed to expose a portion of the sidewall of the trench 100T. In some embodiments, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 is also removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above-mentioned removal process, the exposed area of the sidewall of the conductive filling layer 120 can also be further increased. The above-mentioned removal process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

Next, referring to FIG. 5D , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive fill layer 120 may be thicker than other portions of the gate dielectric layer 130. The gate dielectric layer 130 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

Next, referring to FIGS. 5E and 5F , a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140′ on the gate dielectric layer 130 and performing an etching process on the conductive material 140′ to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The above-mentioned etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. As shown in FIG. 5F , after the etching process, the conductive material 140' becomes a gate electrode layer 140 having a plurality of portions laterally separated by the conductive filling layer 120. An etching process may be subsequently performed to remove a portion of the gate dielectric layer 130 above the top surface of the epitaxial layer 100 .

Since the dopant can have a higher concentration on the upper portion of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and/or side surface of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other portions is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the portion between the conductive filling layer 120 and the gate electrode layer 140 can be maintained at a certain thickness or above. In other words, the lateral separated gate structure formed by the method of the above embodiment can reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

After forming the lateral split gate structure by the formation method shown in FIGS. 5A to 5F, other components and film layers (such as the doped structure 150, the capping layer 160, the upper electrode layer 170, and the lower electrode layer 180) of the semiconductor structure 20 can be formed. These components and film layers can be formed by the materials and formation methods discussed above, and detailed descriptions are omitted here for simplicity.

In summary, the present disclosure provides a semiconductor structure including a separated gate structure and a method for forming the same. The semiconductor structure formed by such a method has a gradient doping concentration distribution in the conductive filling layer of the separated gate structure, so that the resistance value of the conductive filling layer varies in the vertical direction. In addition, by the formation method disclosed in the present disclosure, the thickness of the gate dielectric layer between the conductive layers of the separated gate structure can be freely controlled without affecting the thickness of the gate dielectric layer located on the top surface of the epitaxial layer and the sidewall of the trench. In this way, the size and electrical performance of the semiconductor device can be maintained, and the risk of short circuit or collapse in the split gate structure can be reduced.

The features of several embodiments are summarized above so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

10,20: Semiconductor structure 100: Epitaxial layer 100T: Trench 110: Dielectric spacer layer 112: Remaining part 120: Conductive filling layer 130: Gate dielectric layer 140: Gate electrode layer 140’: Conductive material 142: Extension part 150: Doping structure 152: Doping well 154: First heavily doped region 156: Second heavily doped region 160: Capping layer 170: Upper electrode layer 180: Lower electrode layer 1000,2000: Doping process T1: First thickness T2: Second thickness

The following will be described in detail with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. FIG. 1 is a cross-sectional view of a semiconductor structure including a vertical separated gate structure according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view of a semiconductor structure including a horizontal separated gate structure according to some embodiments of the present disclosure. FIGS. 3A to 3F are cross-sectional views of various stages of a method for forming a vertical separated gate structure according to some embodiments of the present disclosure. Figures 4A to 4G are cross-sectional views of various stages of a method for forming a vertical split gate structure according to some other embodiments of the present disclosure. Figures 5A to 5F are cross-sectional views of various stages of a method for forming a horizontal split gate structure according to some embodiments of the present disclosure.

10:Semiconductor structure

100: Epitaxial layer

100T: Groove

110: Dielectric spacer layer

120: Conductive filling layer

130: Gate dielectric layer

140: Gate electrode layer

142: Extension

150:Doped structure

152: Mixed Well

154: The first heavily doped area

156: Second mixed area

160: Covering layer

170: Upper electrode layer

180: Lower electrode layer

T1: First thickness

T2: Second thickness

Claims (20)

A semiconductor structure comprises: an epitaxial layer having a trench; a dielectric spacer layer disposed in the trench; a conductive filling layer disposed on the dielectric spacer layer and comprising a dopant; a gate dielectric layer disposed on the conductive filling layer; and a gate electrode layer disposed in the trench and separated from the conductive filling layer by the gate dielectric layer; wherein the dopant has a gradient doping concentration in the conductive filling layer. A semiconductor structure as claimed in claim 1, wherein the doping concentration is higher at an upper portion of the conductive filling layer than at a lower portion of the conductive filling layer. A semiconductor structure as claimed in claim 1, wherein the gate electrode layer includes an extension extending between a sidewall of the conductive filling layer and a sidewall of the trench. A semiconductor structure as claimed in claim 1, wherein the gate dielectric layer surrounds the gate electrode layer so that the gate electrode layer is separated from both the dielectric spacer layer and the epitaxial layer. A semiconductor structure as claimed in claim 1, wherein a bottom surface of the gate electrode layer is lower than a top surface of the conductive filling layer. A semiconductor structure as claimed in claim 1, wherein the gate dielectric layer has a first thickness between the conductive filling layer and the sidewall of the gate electrode layer and a second thickness between the gate electrode layer and the sidewall of the trench, and the first thickness is greater than the second thickness. A semiconductor structure as claimed in claim 1, wherein the gate dielectric layer includes a lateral portion extending laterally between a top surface of the conductive fill layer and a bottom surface of the gate electrode layer. A semiconductor structure as claimed in claim 7, wherein the thickness of the lateral portion is greater than the thickness of a portion of the gate dielectric layer covering the sidewall of the trench. A semiconductor structure as claimed in claim 7, wherein the width of the gate electrode layer is greater than the width of the conductive filling layer. A semiconductor structure as claimed in claim 1, wherein the gate electrode layer is laterally divided into multiple parts by the conductive filling layer. A semiconductor structure as claimed in claim 10, wherein the gate dielectric layer includes a lateral portion extending laterally from a top surface of the conductive filling layer, and the top surface of the gate electrode layer is lower than the top surface of the lateral portion. A semiconductor structure as claimed in claim 10, wherein a top surface of the gate electrode layer is lower than a top surface of the conductive filling layer. A method for forming a semiconductor structure, comprising: forming a dielectric spacer layer in a trench of an epitaxial layer; forming a conductive filling layer in the trench; performing a doping process so that the conductive filling layer includes a dopant; forming a gate dielectric layer on the conductive filling layer; and forming a gate electrode layer in the trench, and the gate electrode layer is separated from the conductive filling layer by the gate dielectric layer; wherein the dopant has a gradient doping concentration in the conductive filling layer. The method for forming a semiconductor structure as claimed in claim 13 further includes: Depositing the dielectric spacer layer above the epitaxial layer and in the trench; Forming the conductive filling layer on the dielectric spacer layer; and Partially removing the dielectric spacer layer to expose a portion of the sidewall of the trench. A method for forming a semiconductor structure as claimed in claim 13, wherein the doping process includes introducing the dopant into the conductive filling layer from the top surface and/or sidewall of the conductive filling layer. A method for forming a semiconductor structure as claimed in claim 13, wherein the doping process is an ion implantation process. A method for forming a semiconductor structure as claimed in claim 13, wherein the doping process includes thermal diffusion using a phosphorus-containing precursor. The method for forming a semiconductor structure as claimed in claim 13 further includes conformally depositing the gate dielectric layer on the conductive filling layer, the dielectric spacer, and the epitaxial layer. A method for forming a semiconductor structure as claimed in claim 13, wherein the formation of the gate electrode layer comprises: Depositing a conductive material on the gate electrode layer; and Performing an etching process on the conductive material to form the gate electrode layer. A method for forming a semiconductor structure as claimed in claim 19, wherein the conductive material becomes the gate electrode layer having multiple parts laterally separated by the conductive filling layer after the etching process.

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