TW202504052A - Electrostatic discharge protection device and transistor structure - Google Patents

Abstract

An electrostatic discharge protection device including a substrate, a deep well, a fist well, a second well, a third well, a fourth well, a fifth well, a first doped region, a second doped region, a third doped region, and a gate structure is provided. The deep well is formed on the substrate. The first to fourth wells are formed on the deep well. The fifth well is formed in the fourth well. The first doped region is formed in the first well. The second doped region is formed in the second well. The third doped region is formed in the fourth well. The gate structure overlaps the third well. Each of the substrate, the second well, the fourth well, the second doped region, the third doped region has a first conductivity type. Each of the deep well, the first well, the third well, the fifth well, and the first doped region has the second conductivity type.

Description

Electrostatic discharge protection device and transistor structure

The present invention relates to an electrostatic discharge protection device, and more particularly to an electrostatic discharge protection device with a transistor structure.

Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the sub-micron level, the gate oxide layer of metal oxide semiconductors is becoming thinner and thinner, making integrated circuits more susceptible to damage due to ESD.

In general industrial standards, the input and output pins (I/O pins) of integrated circuit products must be able to pass the Human-Body Mode (HBM) electrostatic discharge test of more than 2000 volts and the Machine Mode (MM) electrostatic discharge test of more than 200 volts. Therefore, in integrated circuit products, electrostatic discharge protection components must be installed near all input and output pads to protect the internal core circuit from electrostatic discharge current.

An embodiment of the present invention provides an electrostatic discharge protection device, including a substrate, a deep well region, a first well region, a second well region, a third well region, a fourth well region, a fifth well region, a first doped region, a second doped region, a third doped region and a gate structure. The substrate has a first conductivity type. The deep well region is formed on the substrate and has a second conductivity type. The first well region is formed on the deep well region and has a second conductivity type. The second well region is formed on the deep well region and has a first conductivity type. The third well region is formed on the deep well region and has a second conductivity type. The fourth well region is formed on the deep well region and has a first conductivity type. The fifth well region is formed in the fourth well region and has a second conductivity type. The first doped region is formed in the first well region and has a second conductivity type. The second doped region is formed in the second well region and has the first conductivity type. The third doped region is formed in the fourth well region and has the first conductivity type. The gate structure covers the third well region.

The present invention further provides a transistor structure, including a base doped region, a source doped region, a gate structure, a drain doped region, a fifth well region and a sixth well region. The base doped region is formed in a first well region. The source doped region is formed in a second well region. The gate structure covers a third well region. The drain doped region is formed in a fourth well region. The fifth well region is formed in the fourth well region. The sixth well region is formed in the fourth well region. The base doped region, the first well region, the third well region, the fifth well region and the sixth well region have the same conductivity type. The source doped region, the second well region, the drain doped region and the fourth well region have the same conductivity type.

In order to make the purpose, features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments and the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. The configuration of each component in the embodiments is for illustration purposes only and is not intended to limit the present invention. In addition, the repetition of some of the figure numbers in the embodiments is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

FIG. 1A is a schematic top view of the electrostatic discharge protection device of the present invention. In this embodiment, the electrostatic discharge protection device 100A includes doped regions 111, 112, 114, a gate structure 113, and well regions 135 and 136. The doped region 111 is located between the isolation structures 121 and 122. The isolation structure 122 separates the doped regions 111 and 112. The isolation structure 123 separates the doped region 112 and the gate structure 113. The gate structure 113 is located on the isolation structures 123 and 124 and overlaps a portion of the isolation structures 123 and 124. The isolation structure 124 separates the gate structure 113 and the doped region 114 .

The doped region 114 covers the well regions 135 and 136. The present invention does not limit the number of well regions. In FIG. 1B , the doped region 114 covers the well regions 135 to 138. In other embodiments, the doped region 114 covers more well regions. The present invention does not limit the size of the well regions 135 and 136. In one possible embodiment, the well regions 135 and 136 have the same size.

The present invention also does not limit the structure of the well regions 135 and 136. In the present embodiment, the well regions 135 and 136 are located below the doped region 114 and contact the doped region 114. In one possible embodiment, the well regions 135 and 136 may expose the surface of the doped region 114. In another possible embodiment, the well regions 135 and 136 may be located below a first isolation structure and a second isolation structure, respectively. In this example, the first and second isolation structures expose the upper surface of the doped region 114.

FIG. 1C is another top view schematic diagram of the electrostatic discharge protection device of the present invention. FIG. 1C is similar to FIG. 1A, except that in FIG. 1C, well regions 135 and 136 expose the surface of the doped region 114 and divide the doped region 114 into doped regions 114_1 to 114_3. In this embodiment, the well region 135 separates the doped regions 114_1 and 114_2, and the well region 136 separates the doped regions 114_2 and 114_3. In some embodiments, the doped regions 114_1 to 114_3 are electrically connected together.

FIG. 1D is another schematic top view of the electrostatic discharge protection device of the present invention. FIG. 1D is similar to FIG. 1C, except that the electrostatic discharge protection device 100D further includes isolation structures 125 and 126. The isolation structure 125 separates the doped regions 114_1 and 114_2 and covers the well region 135. The isolation structure 126 separates the doped regions 114_2 and 114_3 and covers the well region 136. In this embodiment, the well region 135 does not contact the doped regions 114_1 and 114_2, and the well region 136 does not contact the doped regions 114_2 and 114_3.

FIG. 2 is a schematic cross-sectional view of the ESD protection device 100A of FIG. 1A along the dotted line XX'. The deep well region 102 is formed on a substrate 101. In this embodiment, the substrate 101 has a first conductivity type, and the deep well region 102 has a second conductivity type. The first conductivity type is relative to the second conductivity type. For example, when the first conductivity type is P type, the second conductivity type is N type. When the first conductivity type is N type, the second conductivity type is P type.

The well region 131 is formed on the deep well region 102 and has the second conductivity type. In one possible embodiment, the well region 131 is a high-voltage well region. The doped region 111 is formed in the well region 131 and has the second conductivity type. In one possible embodiment, the doped region 111 has an impurity concentration higher than the impurity concentration of the well region 131.

The well region 132 is formed on the deep well region 102 and has a first conductivity type. In one possible embodiment, the well region 132 is a high-voltage well region. The doped region 112 is formed in the well region 132 and has a first conductivity type. In one possible embodiment, the doped region 112 has an impurity concentration higher than the impurity concentration of the well region 132.

The well region 133 is formed on the deep well region 102 and has the second conductivity type. In a possible embodiment, the well region 133 is a high-pressure well region. The impurity concentration of the well region 133 is similar to the impurity concentration of the well region 131. The gate structure 113 is located on the substrate 101 and completely covers the well region 133.

In some embodiments, the gate structure 113 includes a gate dielectric layer 113_1 and a gate electrode layer 113_2. The gate electrode layer 113_2 may include silicon or polysilicon. In some embodiments, the gate structure 113 further includes sidewall structures SP1 and SP2. The sidewall structure SP1 is located on the left side of the gate dielectric layer 113_1 and the gate electrode layer 113_2. The sidewall structure SP2 is located on the right side of the gate dielectric layer 113_1 and the gate electrode layer 113_2.

The well region 134 is formed on the deep well region 102 and has a first conductivity type. In one possible embodiment, the well region 134 is a high-voltage well region. The doped region 114 is formed in the well region 134 and has a first conductivity type. In one possible embodiment, the impurity concentration of the doped region 114 is higher than the impurity concentration of the well region 134. In other embodiments, the impurity concentration of the doped region 114 is similar to the impurity concentration of the doped region 112. In this example, the impurity concentration of the well region 134 is similar to the impurity concentration of the well region 132.

In some embodiments, the ESD protection device 100A further includes isolation structures 121-124. The doped region 111 is located between the isolation structures 121 and 122. The isolation structure 122 separates the doped regions 111 and 112. The isolation structure 123 separates the doped region 112 and the well region 133. The isolation structure 124 separates the well region 133 and the doped region 114. The gate structure 113 overlaps a portion of the isolation structures 123 and 124.

In other embodiments, the ESD protection device 100A further includes contact structures 151-154. The contact structure 151 is electrically connected to the doping region 111. The contact structure 152 is electrically connected to the doping region 112. The contact structure 153 is electrically connected to the gate structure 113. The contact structure 154 is electrically connected to the doping region 114. In some embodiments, when the first conductivity type is P-type and the second conductivity type is N-type, the ESD protection device 100A acts as a PMOS transistor. In this example, the doping region 111 acts as a base doping region, and the contact structure 151 acts as the base of the PMOS transistor. In addition, the doped region 112 serves as a source doped region, and the contact structure 152 serves as a source of the PMOS transistor. The contact structure 154 serves as a gate of the PMOS transistor. The doped region 114 serves as a drain doped region, and the contact structure 154 serves as a drain of the PMOS transistor.

When the first conductivity type is N-type and the second conductivity type is P-type, the electrostatic discharge protection device 100A acts as an NMOS transistor. In this example, the doped region 111 acts as a base doped region, and the contact structure 151 acts as the base of the NMOS transistor. In addition, the doped region 112 acts as a source doped region, and the contact structure 152 acts as the source of the NMOS transistor. The contact structure 154 acts as the gate of the NMOS transistor. The doped region 114 acts as a drain doped region, and the contact structure 154 acts as the drain of the NMOS transistor.

In a possible embodiment, the electrostatic discharge protection device 100 further includes interconnect structures 161 and 162. The interconnect structure 161 is electrically connected to the contact structures 151-153 and coupled to a wire LN1. The interconnect structure 162 is electrically connected to the contact structure 154 and coupled to a wire LN2. When an electrostatic discharge (ESD) event occurs in the wire LN1 and the wire LN2 is coupled to the ground, the electrostatic discharge current enters from the wire LN1 and passes through the doped region 112, the well regions 132, 133, 134, the doped region 114, and the wire LN2, and is released to the ground.

In some embodiments, the ESD protection device 100A further includes a resist protective oxide 140. The resist protective oxide 140 covers a portion of the gate structure 113, a portion of the isolation structure 124, and a portion of the doped region 114. In this example, the resist protective oxide 140 prevents the impedance of the surface of the doped region 114 from being too low.

FIG. 3 is a cross-sectional view of the ESD protection device 100A of FIG. 1A along the dotted line YY'. As shown in the figure, well regions 135 and 136 are formed in well region 134 and have the second conductivity type. In this embodiment, the doped region 114 completely covers the well regions 135 and 136.

In some embodiments, the electrostatic discharge protection device 100A further includes contact structures 311-313. The contact structures 311-313 are electrically connected to the doped region 114. In one possible embodiment, the contact structures 311-313 are electrically connected to the ground. The present invention does not limit the number of contact structures. In other embodiments, the doped region 114 may be electrically connected to more or fewer contact structures. In some embodiments, the contact structures 311-313 are electrically connected to the contact structure 154 of FIG. 2.

FIG. 4 is a cross-sectional view of the ESD protection device 100C of FIG. 1C along the dotted line CC'. As shown in the figure, the well regions 135 and 136 expose the surface of the doped region 114. In this embodiment, the well regions 135 and 136 divide the doped region 114 into doped regions 114_1~114_3. The well region 135 separates the doped regions 114_1 and 114_2. The well region 136 separates the drain doped regions 114_2 and 114_3. In a possible embodiment, the impurity concentrations of the well regions 135 and 136 are similar and higher than the impurity concentrations of the well regions 131 and 133 of FIG. 2. Since the impurity concentration of the well regions 131 and 133 is relatively low, the well regions 131 and 133 can withstand a relatively high voltage. Therefore, the well regions 131 and 133 can also be referred to as a high-voltage well region.

The doped regions 114_1 to 114_3 have a first conductivity type. The doped regions 114_1 to 114_3 have similar impurity concentrations. The present invention does not limit the size of the doped regions 114_1 to 114_3. In one possible embodiment, the size of the doped region 114_2 is larger than the doped regions 114_1 and 114_3. In another possible embodiment, the size of the doped region 114_1 is similar to the size of the doped region 114_3.

In some embodiments, the ESD protection device 100C further includes contact structures 411-413. The contact structure 411 contacts the doped region 114_1. The contact structure 412 contacts the doped region 114_2. The contact structure 413 contacts the doped region 114_3. In one possible embodiment, the contact structures 411-413 are electrically connected to the ground. In some embodiments, the contact structures 411-413 are electrically connected to the contact structure 154 of FIG. 2.

When an electrostatic discharge event occurs, since the well regions 135 and 136 divide the doped region 114, the electrostatic discharge current is dispersed in the doped regions 114_1 to 114_3, reducing the current amount borne by each of the doped regions 114_1 to 114_3. Therefore, the tolerance of the doped regions 114_1 to 114_3 is improved.

FIG. 5 is another cross-sectional schematic diagram of the ESD protection device of FIG. 1D along the dotted line DD'. FIG. 5 is similar to FIG. 4, except that the well regions 135 and 136 of FIG. 5 are suspended in the well region 134. In this embodiment, the isolation structure 125 covers the well region 135. The isolation structure 126 covers the well region 136. In a possible embodiment, the isolation structure 125 separates the doped regions 114_1, 114_2 and the well region 135. Therefore, the well region 135 does not contact the doped regions 114_1 and 114_2. In addition, the isolation structure 126 separates the doped regions 114_2, 114_3 and the well region 136. In this example, the well region 136 does not contact the doped regions 114_2 and 114_3.

When an electrostatic discharge event occurs, the PN between the well regions 134 and 135 has a large voltage difference, thereby forming a vertical electric field, resulting in a fully depleted phenomenon. The holes in the well region below the doped region 114_1 cannot enter the well region below the doped region 114_2. Similarly, the holes in the well region below the doped region 114_2 cannot enter the well region below the doped region 114_1 or 114_3. Therefore, the electrostatic discharge current will not be concentrated in any of the doped regions 114_1 to 114_3.

It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it may be directly coupled or connected to the other element or layer, or have other elements or layers interposed therebetween. Conversely, if an element or layer is "connected" to another element or layer, there will be no other elements or layers interposed therebetween.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those with ordinary knowledge in the art to which the present invention belongs. In addition, unless otherwise expressly stated, the definitions of terms in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant art, and should not be interpreted as ideal or overly formal. Although terms such as "first" and "second" can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention can be implemented in the form of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100A, 100B, 100C, 100D: ESD protection device 111, 112, 114, 114_1~114_3: doping area 113: gate structure 113_1: gate dielectric layer 113_2: gate electrode layer 135~138: well area 121~126: isolation structure XX’, YY’, CC’, DD’: section line 101: substrate 102: deep well area 131~134: well area 140: resistive protection dielectric layer 151~154, 311~313, 411~413: contact structure 161, 162: internal connection structure LN1, LN2: wires SP1, SP2: side wall structure

FIG. 1A is a schematic diagram of a top view of the electrostatic discharge protection device of the present invention. FIG. 1B is another schematic diagram of a top view of the electrostatic discharge protection device of the present invention. FIG. 1C is another schematic diagram of a top view of the electrostatic discharge protection device of the present invention. FIG. 1D is another schematic diagram of a top view of the electrostatic discharge protection device of the present invention. FIG. 2 is a schematic diagram of a cross-section of the electrostatic discharge protection device of FIG. 1A along the dotted line XX'. FIG. 3 is a cross-section of the electrostatic discharge protection device of FIG. 1A along the dotted line YY'. FIG. 4 is a cross-section of the electrostatic discharge protection device of FIG. 1C along the dotted line CC'. Figure 5 is another cross-sectional schematic diagram of the ESD protection device in Figure 1D along the dotted line DD’.

100A: Electrostatic discharge protection device

111, 112, 114: Mixed areas

113: Gate structure

135, 136: Well area

121~124: Isolation structure

XX’, YY’: section line

Claims (20)

An electrostatic discharge protection device includes: a substrate having a first conductivity type; a deep well region formed on the substrate and having a second conductivity type; a first well region formed on the deep well region and having the second conductivity type; a second well region formed on the deep well region and having the first conductivity type; a third well region formed on the deep well region and having the second conductivity type; a fourth well region formed on the deep well region and having the first conductivity type; a fifth well region formed in the fourth well region and having the second conductivity type; a first doped region formed in the first well region and having the second conductivity type; a second doped region formed in the second well region and having the first conductivity type; A third doped region formed in the fourth well region and having the first conductivity type; and a gate structure covering the third well region. The electrostatic discharge protection device of claim 1 further comprises: A sixth well region formed in the fourth well region and having the second conductivity type. An electrostatic discharge protection device as claimed in claim 2, wherein the third doped region covers the fifth well region and the sixth well region. The electrostatic discharge protection device of claim 2 further includes: a fourth doped region formed in the fourth well region and having the first conductivity type, wherein the fifth well region is located between the third doped region and the fourth doped region. An electrostatic discharge protection device as claimed in claim 4, wherein the fourth doped region is located between the fifth well region and the sixth well region. The electrostatic discharge protection device of claim 4 further includes: A first isolation structure formed between the fourth well region and located between the third doped region and the fourth doped region; Wherein the first isolation structure covers the fifth well region. The electrostatic discharge protection device of claim 6, wherein the first isolation structure separates the third doped region, the fourth doped region and the fifth well region. The electrostatic discharge protection device of claim 7 further includes: A fifth doped region formed in the fourth well region and having the first conductivity type, wherein the sixth well region is located between the fourth doped region and the fifth doped region. The electrostatic discharge protection device of claim 8 further includes: A second isolation structure formed between the fourth well region and located between the fourth doped region and the fifth doped region; Wherein the second isolation structure covers the sixth well region. An electrostatic discharge protection device as claimed in claim 9, wherein the second isolation structure separates the fourth doped region, the fifth doped region and the sixth well region. The electrostatic discharge protection device of claim 4 further includes: a first contact structure formed on the first doped region and in contact with the first doped region; a second contact structure formed on the second doped region and in contact with the second doped region; a third contact structure formed on the gate structure and in contact with the gate structure; a fourth contact structure formed on the third doped region and in contact with the third doped region; a fifth contact structure formed on the fourth doped region and in contact with the fourth doped region. The electrostatic discharge protection device of claim 11 further includes: a first internal connection structure electrically connecting the first contact structure, the second contact structure and the third contact structure; and a second internal connection structure electrically connecting the fourth contact structure and the fifth contact structure. The electrostatic discharge protection device of claim 1 further includes: A resistor protection structure covering a portion of the gate structure and a portion of the third doped region. An electrostatic discharge protection device as claimed in claim 1, wherein the impurity concentration of the fifth well region is higher than the impurity concentration of the first well region and the third well region. A transistor structure includes: a base doped region formed in a first well region; a source doped region formed in a second well region; a gate structure covering a third well region; a first drain doped region formed in a fourth well region; a fifth well region formed in the fourth well region; and a sixth well region formed in the fourth well region; wherein: the base doped region, the first well region, the third well region, the fifth well region and the sixth well region have the same conductivity type, the source doped region, the second well region, the first drain doped region and the fourth well region have the same conductivity type. The transistor structure of claim 15 further includes: a second drain doping region formed in the fourth well region; and a third drain doping region formed in the fourth well region; wherein the fifth well region is located between the first and second drain doping regions, and the sixth well region is located between the second and third drain doping regions. A transistor structure as claimed in claim 16, wherein the fifth well region separates the first drain doped region and the second drain doped region, and the sixth well region separates the second drain doped region and the third drain doped region. A transistor structure as claimed in claim 16, wherein the size of the second drain doping region is larger than the size of the first and third drain doping regions. The transistor structure of claim 16 further includes: a first isolation structure covering the fifth well region; and a second isolation structure covering the sixth well region; wherein: the first isolation structure separates the first drain doping region, the second drain doping region and the fifth well region, the second isolation structure separates the second drain doping region, the third drain doping region and the sixth well region. A transistor structure as claimed in claim 15, wherein the impurity concentration of the fifth and sixth well regions is higher than the impurity concentration of the first and third well regions.

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