TW202501943A - Driving circuit - Google Patents

Abstract

A driving circuit providing power to an internal circuit and including a junction field effect transistor (JFET), a resistance, and an electrostatic discharge (ESD) protection circuit is provided. The source of the JFET is coupled to the internal circuit. The resistance is coupled between the gate of the JFET and a power terminal. The ESD protection circuit is coupled between the source and the power terminal. In a normal operation period, the internal circuit operates according to the voltage of the source. In a protection period, the ESD protection circuit is turned to release an ESD current to the power terminal.

Description

Drive circuit

The present invention relates to a driving circuit, and more particularly to a driving circuit with electrostatic discharge protection capability.

Component damage caused by electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the sub-micron level, the gate oxide layer of metal oxide semiconductors is becoming thinner and thinner, making integrated circuits more susceptible to damage due to ESD.

In general industrial standards, the I/O pins of integrated circuit products must be able to pass the human body model electrostatic discharge test of more than 2000 volts and the mechanical model electrostatic discharge test of more than 200 volts. Therefore, in integrated circuit products, electrostatic discharge protection components must be installed near all input and output pads to protect the internal core circuit from electrostatic discharge current.

One embodiment of the present invention provides a driving circuit for supplying power to an internal circuit, and includes a junction field effect transistor, an impedance element and an electrostatic discharge protection circuit. The junction field effect transistor has a first gate, a first drain and a first source. The first source is coupled to the internal circuit. The impedance element is coupled between the first gate and a first power supply terminal. The electrostatic discharge protection circuit is coupled between the first source and the first power supply terminal. During a normal operation period, the internal circuit operates according to the voltage of the first source. During a protection period, the electrostatic discharge protection circuit is turned on to release an electrostatic discharge current to the first power supply terminal.

In another embodiment, the first drain is coupled to a second power terminal. When the voltage of the second power terminal rises, the voltage of the first source increases.

In another embodiment, the impedance element is a resistor, and the resistance of the resistor is greater than 5M ohms.

In another embodiment, the impedance element is a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor has a second gate, a second source and a second drain. The second gate is coupled to the second source. The second drain is coupled to the first gate. The second source is coupled to the first power terminal.

In another embodiment, the impedance element is a metal oxide semiconductor field effect transistor. The metal oxide semiconductor field effect transistor has a second gate, a second source and a second drain. The second gate is coupled to the second source. The second source is coupled to the first gate. The second drain is coupled to the first power terminal.

In another embodiment, the impedance element is a bipolar junction transistor. The bipolar junction transistor has a base, a collector and an emitter. The base is coupled to the emitter. The collector is coupled to the first gate. The emitter is coupled to the first power terminal.

In another embodiment, the impedance element is a bipolar junction transistor. The bipolar junction transistor has a base, a collector and an emitter. The base is coupled to the emitter. The emitter is coupled to the first gate. The collector is coupled to the first power terminal.

In another embodiment, when an electrostatic discharge event occurs, the voltage of the first gate is greater than the voltage of the first source.

In order to make the purpose, features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments and the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. The configuration of each component in the embodiments is for illustration purposes only and is not intended to limit the present invention. In addition, the repetition of some of the figure numbers in the embodiments is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

FIG. 1 is a schematic diagram of the control chip of the present invention. As shown in the figure, the control chip 100 includes a driver circuit 110 and an internal circuit 120. The driver circuit 110 is coupled between a power terminal 130 and a power terminal 140. During a normal operation period, the driver circuit 110 supplies power to the internal circuit 120. During a protection period, the driver circuit 110 protects the internal circuit 120 to prevent an electrostatic discharge (ESD) current from entering the internal circuit 120.

For example, when an electrostatic discharge event does not occur, the driver circuit 120 operates in a normal mode. In the normal mode, the power terminal 130 receives a first operating voltage, and the power terminal 140 receives a second operating voltage. The second operating voltage may be a ground voltage. In this example, the first operating voltage is greater than the ground voltage. In the normal mode, the driver circuit 110 may transmit the first operating voltage to the internal circuit 120, or provide a voltage slightly less than the first operating voltage to the internal circuit 120. When an electrostatic discharge event occurs at the power terminal 130 and the power terminal 140 receives a ground voltage, the driver circuit 110 operates in a protection mode. In the protection mode, the driving circuit 110 provides a discharge path for discharging an electrostatic discharge current from the power terminal 130 to the power terminal 140 .

The driving circuit 110 includes a junction field effect transistor (JFET) 111, an impedance element 112, and an electrostatic discharge protection circuit 113. In the present embodiment, the junction field effect transistor 111 is an ultra-high voltage (UHV) element and an initial-on element. As shown in the figure, the junction field effect transistor 111 has a gate G_1, a drain D_1, and a source S_1. The gate G_1 is coupled to the impedance element 112. The drain D_1 is coupled to the power terminal 130. The source S_1 is coupled to the internal circuit 120 and the electrostatic discharge protection circuit 113. In this embodiment, a parasitic capacitor Cgd is provided between the drain D_1 and the gate G_1 of the JFET 111 .

When the power terminal 130 receives a first operating voltage and the power terminal 140 receives a second operating voltage, the junction field effect transistor 111 is turned on. Therefore, the voltage of the source S_1 gradually increases. After the voltage of the source S_1 is stable (e.g., close to the first operating voltage), the internal circuit 120 operates according to the voltage of the source S_1. In this example, the voltage of the source S_1 serves as the operating voltage of the internal circuit 120.

When an electrostatic discharge event occurs at the power terminal 130 and the power terminal 140 receives a ground voltage, the voltage of the gate G_1 rises due to the capacitive coupling effect of the parasitic capacitor Cgd. Since the voltage of the gate G_1 is greater than the voltage of the source S_1, the junction field effect transistor 111 remains in the on state. At this time, the voltage of the source S_1 increases. When the voltage of the source S_1 reaches a trigger voltage, the electrostatic discharge protection circuit 113 is activated to provide a discharge path. The discharge path releases an electrostatic discharge current from the power terminal 130 to the power terminal 140.

The impedance element 112 is coupled between the gate G_1 and the power terminal 140 to prevent the electrostatic discharge current from flowing into the gate G_1. In addition, when an electrostatic discharge event occurs, the voltage of the gate G_1 of the junction field effect transistor 111 is greater than the voltage of the source S_1 due to the impedance element 112. Therefore, the impedance element 112 ensures that the junction field effect transistor 111 remains turned on during an electrostatic discharge event.

The present invention does not limit the type of the impedance element 112. In a possible embodiment, the impedance element 112 is a resistor. In this example, the resistance of the resistor is greater than 5M ohms. In some embodiments, the resistance of the resistor is greater than 10M ohms. When an electrostatic discharge event occurs at the power terminal 130 and the power terminal 140 receives a ground voltage, since the impedance element 112 is coupled between the gate G_1 and the power terminal 140, the electrostatic discharge current can be prevented from entering and damaging the gate G_1. In some embodiments, by coupling the impedance element 112 between the gate G_1 of the junction field effect transistor 111 and the power terminal 140, the junction field effect transistor 111 can withstand a voltage of more than 4.6KV.

The electrostatic discharge protection circuit 113 is coupled between the source S_1 of the junction field effect transistor 111 and the power terminal 140 to prevent an electrostatic discharge current from entering the internal circuit 120. For example, when an electrostatic discharge event occurs at the power terminal 130 and the power terminal 140 receives a ground voltage, the voltage of the gate G_1 increases due to the capacitive coupling effect caused by the parasitic capacitor Cgd. Since the voltage of the gate G_1 of the junction field effect transistor 111 is greater than the voltage of the source S_1, the junction field effect transistor 111 is turned on. Therefore, the voltage of the source S_1 gradually increases. When the voltage of the source S_1 of the JFET 111 reaches a trigger voltage, the ESD protection circuit 113 is turned on to discharge an ESD current from the power terminal 130 to the power terminal 140 .

When an ESD event does not occur, the power terminal 130 receives a first operating voltage, and the power terminal 140 receives a second operating voltage. At this time, the junction field effect transistor 111 is turned on. Therefore, the voltage of the source S_1 of the junction field effect transistor 111 rises. Since the voltage of the source S_1 of the junction field effect transistor 111 is not enough to trigger the ESD protection circuit 113, the ESD protection circuit 113 does not operate. At this time, the internal circuit 120 operates according to the voltage of the source S_1.

FIG. 2A is a schematic diagram of an impedance element of the present invention. In this embodiment, the impedance element 112 is an N-type metal-oxide semiconductor field effect transistor (NMOSFET) 210. The N-type metal-oxide semiconductor field effect transistor 210 has a gate G_2, a drain D_2, and a source S_2.

The gate G_2 of the NMOS 210 is coupled to the source S_2 and the power terminal 140. The drain D_2 of the NMOS 210 is coupled to the gate G_1 of the JFET 111. In some embodiments, the gate G_2 is directly electrically connected to the source S_2 and the power terminal 140. In this example, the drain D_2 is directly electrically connected to the gate G_1 of the JFET 111.

When the N-type metal oxide semiconductor field effect transistor 210 is turned on, the N-type metal oxide semiconductor field effect transistor 210 has an equivalent resistance. The equivalent resistance when the N-type metal oxide semiconductor field effect transistor 210 is turned on can prevent the electrostatic discharge current from the power terminal 130 from flowing into the gate G_1 of the junction field effect transistor 111. Therefore, the N-type metal oxide semiconductor field effect transistor 210 does not allow the gate G_1 to be damaged by the electrostatic discharge current.

FIG. 2B is another schematic diagram of the impedance element of the present invention. In this embodiment, the impedance element 112 is a P-type metal oxide semiconductor field effect transistor (PMOSFET) 220. The P-type metal oxide semiconductor field effect transistor 220 has a gate G_3, a drain D_3 and a source S_3.

The gate G_3 of the P-type metal oxide semiconductor field effect transistor 220 is electrically coupled to the source S_3 and the gate G_1 of the junction field effect transistor 111. The drain D_3 of the P-type metal oxide semiconductor field effect transistor 220 is electrically coupled to the power terminal 140. In some embodiments, the gate G_3 is directly electrically connected to the source S_3 and the gate G_1 of the junction field effect transistor 111. In addition, the drain D_3 may be directly electrically connected to the power terminal 140.

When the P-type metal oxide semiconductor field effect transistor 220 is turned on, the P-type metal oxide semiconductor field effect transistor 220 has an equivalent impedance. By means of the equivalent impedance when the P-type metal oxide semiconductor field effect transistor 220 is turned on, the electrostatic discharge current from the power supply terminal 130 can be prevented from directly pouring into the gate G_1 of the junction field effect transistor 111. Therefore, the P-type metal oxide semiconductor field effect transistor 220 can protect the gate G_1 of the junction field effect transistor 111 and prevent the gate G_1 from being damaged by the electrostatic discharge current.

FIG. 2C is another schematic diagram of the impedance element of the present invention. In the present embodiment, the impedance element 112 is a bipolar junction transistor (BJT) 230. The BJT 230 is an npn type. The BJT 230 has a base B_1, a collector C_1, and an emitter E_1.

The collector C_1 of the BJT 230 is coupled to the gate G_1 of the JFET 111. The base B_1 of the BJT 230 is coupled to the emitter E_1 and the power terminal 140. In some embodiments, the collector C_1 of the BJT 230 is directly electrically connected to the gate G_1 of the JFET 111. In this example, the base B_1 of the BJT 230 is directly electrically connected to the emitter E_1 and the power terminal 140.

When the bipolar junction transistor 230 is turned on, the bipolar junction transistor 230 has an equivalent impedance. The equivalent impedance of the bipolar junction transistor 230 when turned on can prevent the electrostatic discharge current from the power terminal 130 from directly flowing into the gate G_1 of the junction field effect transistor 111. Therefore, the bipolar junction transistor 230 can protect the gate G_1 of the junction field effect transistor 111 and prevent the gate G_1 from being damaged by the electrostatic discharge current.

FIG. 2D is another schematic diagram of the impedance element of the present invention. In this embodiment, the impedance element 112 is a bipolar junction transistor 240. The bipolar junction transistor 240 is a pnp type. The bipolar junction transistor 240 has a base B_2, a collector C_2, and an emitter E_2.

The base B_2 of the bipolar junction transistor 240 is electrically coupled to the emitter E_2 and the gate G_1 of the junction field effect transistor 111. The collector C_2 of the bipolar junction transistor 240 is electrically coupled to the power terminal 140. In some embodiments, the base B_2 of the bipolar junction transistor 230 is directly electrically connected to the emitter E_2 and the gate G_1 of the junction field effect transistor 111. In this example, the collector C_2 of the bipolar junction transistor 240 is directly electrically connected to the power terminal 140.

When the bipolar junction transistor 240 is turned on, the bipolar junction transistor 240 has an equivalent impedance. The equivalent impedance of the bipolar junction transistor 240 when turned on can prevent the electrostatic discharge current from the power terminal 130 from directly flowing into the gate G_1 of the junction field effect transistor 111. Therefore, the bipolar junction transistor 240 can protect the gate G_1 of the junction field effect transistor 111 and prevent the gate G_1 from being damaged by the electrostatic discharge current.

It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it may be directly coupled or connected to the other element or layer, or have other elements or layers interposed therebetween. Conversely, if an element or layer is "connected" to another element or layer, there will be no other elements or layers interposed therebetween.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those with ordinary knowledge in the art to which the present invention belongs. In addition, unless otherwise expressly stated, the definitions of terms in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant art, and should not be interpreted as ideal or overly formal. Although terms such as "first" and "second" can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention can be implemented in the form of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Control chip 100: Control chip 110: Drive circuit 120: Internal circuit 130, 140: Power supply terminal 111: Junction field effect transistor 112: Impedance element 113: ESD protection circuit G_1, G_2, G_3: Gate D_1, D_2, D_3: Drain S_1, S_2, S_3: Source Cgd: Parasitic capacitance 210: N-type metal oxide semiconductor field effect transistor 220: P-type metal oxide semiconductor field effect transistor 230, 240: Bipolar junction transistor B_1, B_2: Base C_1, C_2: Collector E_1, E_2: emitter

Figure 1 is a schematic diagram of the control chip of the present invention. Figure 2A is a schematic diagram of the impedance element of the present invention. Figure 2B is another schematic diagram of the impedance element of the present invention. Figure 2C is another schematic diagram of the impedance element of the present invention. Figure 2D is another schematic diagram of the impedance element of the present invention.

100: Control chip

110:Drive circuit

120: Internal circuit

130, 140: Power supply terminal

111: Junction Field Effect Transistor

112: Impedance element

113: Electrostatic discharge protection circuit

G_1: Gate

D_1: Drain

S_1: Source

Cgd: parasitic capacitance

Claims (10)

A driving circuit for supplying power to an internal circuit, comprising: a junction field effect transistor having a first gate, a first drain and a first source, the first source coupled to the internal circuit; an impedance element coupled between the first gate and a first power supply terminal; and an electrostatic discharge protection circuit coupled between the first source and the first power supply terminal, wherein: during a normal operation period, the internal circuit operates according to the voltage of the first source, during a protection period, the electrostatic discharge protection circuit is turned on to release an electrostatic discharge current to the first power supply terminal. A driving circuit as claimed in claim 1, wherein the first drain is coupled to a second power terminal, and when the voltage of the second power terminal rises, the voltage of the first source increases. A driving circuit as claimed in claim 1, wherein the impedance element is a resistor having a resistance greater than 5M ohms. A driving circuit as claimed in claim 1, wherein the impedance element is a metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor has a second gate, a second source and a second drain, and the second gate is coupled to the second source. A driving circuit as claimed in claim 4, wherein the second drain is coupled to the first gate, and the second source is coupled to the first power terminal. A driving circuit as claimed in claim 4, wherein the second source is coupled to the first gate, and the second drain is coupled to the first power terminal. A driving circuit as claimed in claim 1, wherein the impedance element is a bipolar junction transistor having a base, a collector and an emitter, the base being coupled to the emitter. A driving circuit as claimed in claim 7, wherein the collector is coupled to the first gate, and the emitter is coupled to the first power terminal. A driving circuit as claimed in claim 7, wherein the emitter is coupled to the first gate, and the collector is coupled to the first power terminal. The driving circuit of claim 1, wherein when an electrostatic discharge event occurs, the voltage of the first gate is greater than the voltage of the first source.

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