TW202447969A - Semiconductor device and method for forming the same - Google Patents

Abstract

A method for forming a semiconductor device includes the steps of providing a wafer having a top metal layer, forming an etching stop layer having at least two stacked layers on the wafer and covering the top metal layer, forming a bonding layer on the etching stop layer, etching the bonding layer and the etching stop layer to form at least an opening that stops in a non-bottom most layer of the etch stop layer, forming a protection layer filling the opening, removing a portion of the protection layer in the opening and the bonding layer on a sidewall of the opening to form a trench on the opening, removing remaining portions of the protection layer and the etching stop layer under the opening until exposing the top metal layer, forming a filling metal in the trench and the opening and in contact with the top metal layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor element and a manufacturing method thereof.

With the development of chip manufacturing technology, multi-chip stacking technology has received more and more attention from the industry, among which hybrid bonding technology is widely used.

Before bonding, a silicon nitride layer and a bonding layer are formed on the wafers to be bonded, and then a through hole is etched in the bonding layer, and the etching stops in the silicon nitride layer. Then, a bottom anti-reflection layer is filled in the through hole, and the bonding layer and the bottom anti-reflection layer on the top of the through hole sidewall are etched to form a trench at the top of the through hole; then, the remaining bottom anti-reflection layer and the silicon nitride layer on the bottom of the through hole are removed. Next, a metal layer is filled in the trench and through hole to facilitate bonding between the bonding layers on the two wafers and bonding between the metal layers in the subsequent hybrid bonding process.

As shown in FIG. 1 , a silicon nitride layer 13 and a bonding layer 14 are formed on a wafer 11 to be bonded, and a top metal layer 12 is formed on the top of the wafer 11 . In the wafer 11 to be bonded, the top metal layer 12 (e.g., copper) is a redistribution layer and is usually thicker, which causes hillocks 121 to be easily generated on the top metal layer 12. The silicon nitride layer 13 on the hillock 121 is much thinner than the silicon nitride layer 13 at other locations, and silicon nitride is very brittle, which causes the hillock 121 to easily crack the silicon nitride layer 13 thereon. In addition, a small amount of etching will also be performed on the silicon nitride layer 13 during the process of etching to form a through hole, thereby exposing the hillock 121 and causing metal diffusion problems. As shown in FIG2 , after copper diffusion, pits 122 are formed in the top metal layer 12, and the metal diffuses to the inner wall of the through hole and the surface of the wafer 11, thereby causing electrical connection problems or even disconnection between the bonded wafers. Although metal diffusion can be prevented by increasing the thickness of the silicon nitride layer 13, the risk of the silicon nitride layer 13 itself peeling off will increase.

Therefore, how to improve the copper diffusion problem to increase the hybrid bonding yield is a problem that still needs to be solved in this field.

The purpose of the present invention is to provide a semiconductor element and a manufacturing method thereof, which can improve the metal diffusion problem and thus improve the hybrid bonding yield.

To achieve the above-mentioned purpose, the present invention provides a method for manufacturing a semiconductor element, comprising the following steps. First, a wafer is provided, wherein the wafer is formed with a top metal layer, and an etch stop layer covers the top metal layer, and the etch stop layer is a structure of at least two layers stacked. Then, a bonding layer is formed on the etch stop layer, and then the bonding layer is etched, and the etching stops in the non-bottommost structure of the etch stop layer to form a through hole. Then, a protective layer is filled in the through hole, and then a portion of the protective layer in the through hole and the bonding layer at the top of the through hole sidewall are etched away to form a groove at the top of the through hole. Then, the remaining protection layer is removed, and then the etching stop layer on the bottom surface of the through hole is removed by etching to expose the top metal layer. Then, a metal layer is filled in the trench and the through hole, and the metal layer is connected to the top metal layer.

In some embodiments, the etch stop layer includes an oxide layer and a silicon nitride layer stacked from bottom to top, and when the through hole is formed, the etching stops in the silicon nitride layer. Alternatively, in some embodiments, the etch stop layer includes a first silicon nitride layer, an oxide layer, and a second silicon nitride layer stacked from bottom to top, and when the through hole is formed, the etching stops in the second silicon nitride layer or the oxide layer.

In some embodiments, the material of the oxide layer includes silicon oxide and/or silicon oxynitride.

In some embodiments, the bonding layer is a multi-layer stacked structure.

In some embodiments, the protective layer includes at least one of an anti-reflective layer, spin-on carbon, and spin-on glass.

In some embodiments, the method for manufacturing the semiconductor device further includes bonding at least two of the wafers, wherein the bonding layers on adjacent wafers are bonded to each other, and the metal layers on adjacent wafers are bonded to each other.

The present invention also provides a semiconductor element, comprising a substrate, a top metal layer formed on the substrate, an etch stop layer covering the top metal layer, the etch stop layer being a structure of at least two layers stacked, a through hole exposing the top metal layer formed in the etch stop layer, a bonding layer formed on the etch stop layer, a trench formed in the bonding layer, the through hole extending from the etch stop layer into the bonding layer and communicating with the trench, the width of the trench being greater than the width of the through hole. A metal layer is filled in the trench and the through hole, and the metal layer is connected to the top metal layer.

In some embodiments, the etch stop layer includes an oxide layer and a silicon nitride layer stacked from bottom to top, or the etch stop layer includes a first silicon nitride layer, an oxide layer, and a second silicon nitride layer stacked from bottom to top.

In some embodiments, the material of the oxide layer includes silicon oxide and/or silicon oxynitride.

In some embodiments, the semiconductor device includes at least two bonded substrates, wherein the bonding layers adjacent to the substrates are bonded, and the metal layers adjacent to the substrates are bonded.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

1. The method for manufacturing a semiconductor device of the present invention comprises forming an etch stop layer on a wafer, wherein the etch stop layer covers a top metal layer, and the etch stop layer is a structure of at least two stacked layers; forming a bonding layer on the etch stop layer; etching the bonding layer, and the etching stops in a non-bottommost structure of the etch stop layer to form a through hole; filling a protective layer in the through hole; and etching away a portion of the through hole. The protective layer and the bonding layer on the top of the through hole side wall are separated to form a groove at the top of the through hole; the remaining protective layer is removed; the etch stop layer on the bottom surface of the through hole is removed by etching to expose the top metal layer; a metal layer is filled in the groove and the through hole, and the metal layer is connected to the top metal layer, so that the metal diffusion problem can be improved, thereby improving the hybrid bonding yield.

2. The semiconductor device of the present invention comprises a substrate, a top metal layer is formed on the substrate; an etch stop layer, covering the top metal layer, the etch stop layer is a structure of at least two layers stacked, the etch stop layer is formed with a through hole exposing the top metal layer; a bonding layer, formed on the etch stop layer, A trench is formed, the through hole extends from the etch stop layer to the bonding layer and is connected to the trench, the width of the trench is greater than the width of the through hole; a metal layer is filled in the trench and the through hole, the metal layer is connected to the top metal layer, so that the metal diffusion problem can be improved, thereby improving the hybrid bonding yield.

In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and its manufacturing method proposed by the present invention are further described in detail below. It should be noted that the attached figures are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 3 , the steps of the method for manufacturing a semiconductor device include:

Step S1, providing a wafer, wherein a top metal layer is formed on the wafer, an etch stop layer covers the top metal layer, and the etch stop layer is a structure of at least two stacked layers;

Step S2, forming a bonding layer on the etch stop layer;

Step S3, etching the bonding layer, and stopping the etching in the non-bottommost structure of the etch stop layer to form a through hole;

Step S4, filling the protective layer in the through hole;

Step S5, etching and removing a portion of the protection layer in the through hole and the bonding layer at the top of the through hole sidewall to form a groove at the top of the through hole;

Step S6, removing the remaining protective layer;

Step S7, etching away the etching stop layer on the bottom surface of the through hole to expose the top metal layer;

Step S8, filling the groove and the through hole with a metal layer, wherein the metal layer is connected to the top metal layer.

Please refer to Figures 4a to 4k below for a detailed description of the method for manufacturing a semiconductor device provided in this embodiment. Figures 4a to 4k are schematic cross-sectional views of a semiconductor device in the manufacturing steps.

First, in step S1, as shown in FIG. 4a, a wafer 21 is provided, and a top metal layer 213 is formed on the wafer 21.

The wafer 21 includes a substrate 211 and an insulating dielectric layer 212 formed on the substrate 211, the top metal layer 213 is formed in the insulating dielectric layer 212, and the insulating dielectric layer 212 exposes the top metal layer 213. The insulating dielectric layer 212 also has a metal interconnect structure and the like formed therein, and the top metal layer 213 is electrically connected to the metal interconnect structure as a redistribution layer.

The wafer 21 may be a device wafer or a carrier wafer.

The component wafer may be a pixel wafer including a pixel array of an image sensor, or a MEMS wafer including a MEMS microstructure of a MEMS element, or a MOSFET wafer including a power element, or an IGBT wafer, or a passive element wafer, etc. The type of the component wafer depends on the function of the element to be manufactured in the end. The carrier wafer may not include a functional structure. Alternatively, the carrier wafer may include a functional structure, and the functional structure is located inside the carrier wafer rather than on the surface of the carrier wafer. In some embodiments, the functional structure included in the carrier wafer may also be located inside and/or on the surface of the wafer edge.

The material of the top metal layer 213 can be metal materials such as copper or aluminum.

In the wafer 21, the top metal layer 213 is usually thicker as a redistribution layer, so that the stress change of the top metal layer 213 in the high temperature environment during the manufacturing process is more obvious, and then the recrystallization or growth of the crystal will occur, resulting in the easy generation of hillocks (i.e., hillocks 121 shown in FIG. 1 ) on the top metal layer 213. When the material of the top metal layer 213 is copper, copper has very good diffusion properties, resulting in the easy generation of hillocks on the top metal layer 213.

As shown in FIG. 4 a , an etch stop layer 22 is formed on the wafer 21 . The etch stop layer 22 covers the top metal layer 213 . The etch stop layer 22 is a structure of at least two stacked layers.

In the embodiments shown in FIGS. 4a to 4k, the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top. Alternatively, in another embodiment, the etch stop layer 22 includes an oxide layer and a silicon nitride layer stacked from bottom to top. The structure of the etch stop layer 22 is not limited to the above-mentioned embodiments. In other embodiments, the etch stop layer 22 may also be formed by multiple alternating stacks of oxide layers and silicon nitride layers.

The material of the oxide layer may include silicon oxide and/or silicon oxynitride.

Then, step S2 is performed, as shown in FIG. 4 a , to form a bonding layer 23 on the etch stop layer 22 .

Preferably, the bonding layer 23 is a multi-layer stacked structure.

In the embodiments shown in FIG. 4a to FIG. 4j, the bonding layer 23 includes a first dielectric layer 231, a second dielectric layer 232, and a third dielectric layer 233 stacked from bottom to top. In one embodiment, the materials of the first dielectric layer 231 and the third dielectric layer 233 may be oxide layers such as silicon oxide and/or silicon oxynitride, and the material of the second dielectric layer 232 may be nitrogen-doped silicon carbide. In other embodiments, the materials of the first dielectric layer 231, the second dielectric layer 232, and the third dielectric layer 233 may also be other insulating materials.

Then, step S3 is performed to etch the bonding layer 23 , and the etching stops at the non-bottommost structure of the etch stop layer 22 to form a through hole 24 .

It should be noted that the step of stopping etching in the non-bottommost structure of the etch stop layer 22 may include stopping etching at the top surface of the topmost structure of the etch stop layer 22, i.e., just etching through the bonding layer 23. Alternatively, the step of stopping etching at the inside of the non-bottommost structure of the etch stop layer 22 may include, i.e., after etching through the bonding layer 23, the non-bottommost structure of the etch stop layer 22 is also partially etched away. Alternatively, the etching may be stopped at the top surface of the bottommost structure of the etch stop layer 22, that is, after the bonding layer 23 is etched through, the non-bottommost structure of the etch stop layer 22 is also etched through to expose the bottommost structure of the etch stop layer 22.

If the etch stop layer 22 includes an oxide layer and a silicon nitride layer stacked from bottom to top, the etching stops in the silicon nitride layer when forming the through hole 24. If the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top, the etching stops in the second silicon nitride layer 223 or the oxide layer 222 when forming the through hole 24.

In detail, referring to FIG. 4b to FIG. 4d, the step of forming the through hole 24 may include: first, as shown in FIG. 4b, forming a first patterned photoresist layer 241 on the third dielectric layer 233. Then, as shown in FIG. 4c, using the first patterned photoresist layer 241 as a mask, sequentially etching the third dielectric layer 233, the second dielectric layer 232 and the first dielectric layer 231, and stopping in the second silicon nitride layer 223. Then, as shown in FIG. 4d, removing the first patterned photoresist layer 241.

In addition, after forming the through hole 24 and before subsequently filling the protection layer 25 in the through hole 24, the method for manufacturing the semiconductor device may further include performing a wet cleaning process to remove byproducts generated by etching.

Since the etch stop layer 22 is a structure of at least two layers stacked, and when etching to form the through hole 24, the etching stops in the non-bottommost structure of the etch stop layer 22, compared with the single-layer silicon nitride layer 13 as the etch stop layer shown in FIG. 1, the etch stop layer 22 in the embodiment of the present invention has more layers and a larger thickness. , so that in the process of etching to form the through hole 24, the hillock on the top metal layer 213 can always be covered and protected by the thicker etch stop layer 22, and the bottom layer structure of the etch stop layer 22 is pressed by the non-bottom layer structure, which can improve the situation where the bottom layer structure of the etch stop layer 22 is cracked by the hillock on the top metal layer 213. In addition, the embodiment of the present invention retains at least a portion of the etch stop layer 22 after etching to form the through hole 24, and covers the top metal layer 213 with the bottom structure of the entire thickness thereof, so that during the subsequent wet cleaning process, the bottom structure of the etch stop layer 22 can continue to protect the hillock on the top metal layer 213. Therefore, the embodiment of the present invention can prevent the hillock on the top metal layer 213 from being exposed during the process of etching to form the through hole 24 and after etching to form the through hole 24, and further prevent the hillock on the top metal layer 213 from reacting with the cleaning solution during the wet cleaning process, thereby improving the metal diffusion problem.

In some embodiments, when the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top, or the etch stop layer 22 includes an oxide layer and a silicon nitride layer stacked from bottom to top, since the brittleness of oxides such as silicon oxide and/or silicon oxynitride is lower than that of silicon nitride, the oxide has better coating properties, and thus if the oxide layer coats the first silicon nitride layer, the first silicon nitride layer is not easy to crack, and if the oxide layer directly coats the hillock, the oxide layer is not easy to crack. Therefore, the present invention can further prevent the hillock on the top metal layer 213 from being exposed when etching to form the through hole 24.

In some embodiments, when the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top, and the etching stops at the second silicon nitride layer 223 when forming the through hole 24, even if the first silicon nitride layer 221 is cracked, the oxide layer 222 serves as a buffer layer to cover the cracked first silicon nitride layer 221 and the hillock on the top metal layer 213, thereby further preventing the hillock on the top metal layer 213 from being exposed.

Then, step S4 is performed, as shown in FIG. 4 e , to fill the protection layer 25 in the through hole 24 .

The protective layer 25 may also cover the surface of the bonding layer 23.

The protective layer 25 includes at least one of an anti-reflection layer, spin-on carbon, and spin-on glass.

The anti-reflection layer may be formed of a nitride material, an organic material, an oxide material, or the like.

Then, step S5 is performed, as shown in FIGS. 4f to 4g, to etch away a portion of the protective layer 25 in the through hole 24 and the bonding layer 23 at the top of the sidewall of the through hole 24 to form a groove 26 at the top of the through hole 24, wherein the width of the groove 26 is greater than the width of the through hole 24.

In some embodiments, forming the trench 26 at the top of the through hole 24 may include the following steps. First, as shown in FIG4f, a second patterned photoresist layer 261 is formed on the protective layer 25, and then, as shown in FIG4g, the second patterned photoresist layer 261 is used as a mask to etch the protective layer 25 and the bonding layer 23 at the top of the sidewall of the through hole 24 to form the trench 26 at the top of the through hole 24.

After the trench 26 is formed by etching, a partial thickness of the protective layer 25 remains in the through hole 24. The protective layer 25 can protect the etch stop layer 22 at the bottom of the through hole 24 during the process of etching the trench 26, thereby preventing the etch stop layer 22 at the bottom of the through hole 24 from being etched, thereby preventing the hillock on the top metal layer 213 from being exposed.

Then, step S6 is performed, as shown in FIG. 4h, to remove the remaining protective layer 25.

In some embodiments, an ashing process may be used to remove the remaining protective layer 25 in the through hole 24 , the protective layer 25 on the bonding layer 23 , and the second patterned photoresist layer 261 .

Then, in step S7, as shown in FIG. 4i, the etching stop layer 22 on the bottom surface of the through hole 24 is removed by etching to expose the top metal layer 213.

While the etching stop layer 22 on the bottom surface of the through hole 24 is being etched away, a portion of the thickness of the top surface of the bonding layer 23 and the inner wall of the trench 26 will also be etched away.

Then, step S8 is performed, as shown in FIG. 4j to FIG. 4k , to fill the metal layer 27 in the trench 26 and the through hole 24 , and the metal layer 27 is electrically connected to the top metal layer 213 .

When the bonding layer 23 includes a first dielectric layer 231, a second dielectric layer 232, and a third dielectric layer 233 stacked from bottom to top, filling the metal layer 27 in the trench 26 and the through hole 24 may include the following steps. First, as shown in FIG4j, the metal layer 27 is filled in the trench 26 and the through hole 24, and the metal layer 27 covers the third dielectric layer 233. Then, as shown in FIG4k, the metal layer 27 and the third dielectric layer 233 that are higher than the second dielectric layer 232 are ground and removed by a chemical mechanical grinding process, so that in the subsequent bonding process, the second dielectric layer 232 on the adjacent wafer 21 is bonded.

The portion of the metal layer 27 located in the through hole 24 is a transfer layer, and the transfer layer is used to electrically connect to the top metal layer 213. The portion of the metal layer 27 located in the trench 26 is a bonding pad, and the bonding pad is used for a subsequent bonding process.

In some embodiments, the method for manufacturing the semiconductor device may further include bonding at least two of the wafers 21, wherein the bonding layers 23 on adjacent wafers 21 are bonded, and the metal layers 27 on adjacent wafers 21 are bonded.

As can be seen from the above description, in the manufacturing process of the semiconductor element provided by the present invention, the etch stop layer 22 can protect the hillock on the top metal layer 213 from being exposed, thereby improving the metal diffusion problem, avoiding the formation of pits (i.e., pits 122 in FIG. 2) in the top metal layer 213, and avoiding metal diffusion to the surface of the through hole 24 and the groove 26, thereby avoiding electrical connection problems or even circuit breaks between the wafers to be bonded subsequently, thereby improving the hybrid bonding yield.

In addition, it should be noted that the above-mentioned method for manufacturing semiconductor elements is used to form a wafer structure, wherein the wafer structure includes chip structures arranged in an array, and a cutting path is provided between adjacent chip structures. The method for manufacturing semiconductor elements may also include cutting the wafer structure along the cutting path to separate the chip structures arranged in an array.

The semiconductor element shown in Figure 4k can be a part of the wafer structure or the chip structure.

In summary, the present invention provides a method for manufacturing a semiconductor device, the steps comprising: providing a wafer, the wafer having a top metal layer formed thereon, an etch stop layer covering the top metal layer, the etch stop layer being a structure of at least two layers stacked; forming a bonding layer on the etch stop layer; etching the bonding layer, and the etching stops in a non-bottommost structure of the etch stop layer to form a through hole; filling The method comprises the following steps: filling a protective layer in the through hole; etching away a portion of the protective layer in the through hole and the bonding layer on the top of the through hole sidewall to form a trench at the top of the through hole; removing the remaining protective layer; etching away the etching stop layer on the bottom of the through hole to expose the top metal layer; filling a metal layer in the trench and the through hole, wherein the metal layer is connected to the top metal layer. The method for manufacturing a semiconductor element provided by the present invention can improve the metal diffusion problem, thereby improving the hybrid bonding yield.

An embodiment of the present invention provides a semiconductor element, comprising a substrate, a top metal layer formed on the substrate, an etch stop layer covering the top metal layer, the etch stop layer being a structure of at least two layers stacked, a through hole exposing the top metal layer formed in the etch stop layer, and a bonding layer formed on the etch stop layer, a trench formed in the bonding layer, wherein the through hole extends from the etch stop layer into the bonding layer and communicates with the trench, and the width of the trench is greater than the width of the through hole. A metal layer is filled in the trench and the through hole, and the metal layer is connected to the top metal layer.

Please refer to Figure 4k below to explain the semiconductor device provided by this embodiment in detail. Figure 4k is a cross-sectional schematic diagram of the semiconductor device.

A top metal layer 213 is formed on the substrate 211 .

An insulating dielectric layer 212 is formed on the substrate 211, and the top metal layer 213 is formed in the insulating dielectric layer 212, and the insulating dielectric layer 212 exposes the top metal layer 213; a metal interconnect structure and other structures are also formed in the insulating dielectric layer 212, and the top metal layer 213 is electrically connected to the metal interconnect structure as a redistribution layer.

The material of the top metal layer 213 can be metal materials such as copper or aluminum.

The top metal layer 213 is usually thicker as a redistribution layer, so that the stress change of the top metal layer 213 in the high temperature environment during the manufacturing process is more obvious, and then the recrystallization or growth of the crystal will occur, resulting in the easy generation of hillocks (i.e., the hillocks 121 shown in FIG. 1 ); wherein, when the material of the top metal layer 213 is copper, due to the very good diffusion property of copper, it is easier to generate hillocks on the top metal layer 213.

The etch stop layer 22 is formed on the insulating dielectric layer 212 , and covers the top metal layer 213 . The etch stop layer 22 is a structure of at least two layers stacked together, and a through hole exposing the top metal layer 213 is formed in the etch stop layer 22 .

In the embodiment shown in FIG. 4k , the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top; or, in another embodiment, the etch stop layer 22 includes an oxide layer and a silicon nitride layer stacked from bottom to top. The structure of the etch stop layer 22 is not limited to the above embodiment. In other embodiments, the etch stop layer 22 may also be formed by multiple alternating stacks of oxide layers and silicon nitride layers.

In some embodiments, the material of the oxide layer may include silicon oxide and/or silicon oxynitride.

The bonding layer 23 is formed on the etch stop layer 22, a trench is formed in the bonding layer 23, the through hole extends from the etch stop layer 22 to the bottom surface of the trench in the bonding layer 23, and the through hole is connected to the trench, wherein the width of the trench is greater than the width of the through hole.

Preferably, the bonding layer 23 is a multi-layer stacked structure.

In some embodiments, the bonding layer 23 may include a first dielectric layer 231, a second dielectric layer 232, and a third dielectric layer 233 stacked from bottom to top. In one embodiment, the materials of the first dielectric layer 231 and the third dielectric layer 233 may be oxide layers such as silicon oxide and/or silicon oxynitride, and the material of the second dielectric layer 232 may be nitrogen-doped silicon carbide; in other embodiments, the materials of the first dielectric layer 231, the second dielectric layer 232, and the third dielectric layer 233 may also be other insulating materials.

In the embodiment shown in FIG. 4k , the bonding layer 23 includes a first dielectric layer 231 and a second dielectric layer 232 stacked from bottom to top.

The metal layer 27 is filled in the trench and the through hole, and the metal layer 27 is electrically connected to the top metal layer 213.

The portion of the metal layer 27 located in the through hole is a transfer layer, which is used to electrically connect to the top metal layer 213; the portion of the metal layer 27 located in the groove is a bonding pad, which is used for a subsequent bonding process.

The semiconductor device of the present invention may include only a single substrate 211. Alternatively, the semiconductor device of the present invention includes at least two bonded substrates 211, wherein the bonding layer 23 adjacent to the substrate 211 is bonded, and the metal layer 27 adjacent to the substrate 211 is bonded. When the bonding layer 23 includes a first dielectric layer 231 and a second dielectric layer 232 stacked from bottom to top, the second dielectric layer 232 adjacent to the substrate 211 is bonded.

Since the etch stop layer 22 is a structure of at least two layers stacked, when etching to form the through hole, the etching can be stopped in the non-bottommost structure of the etch stop layer 22. Therefore, compared with the etch stop layer 13 with only a single-layer structure as the etch stop layer shown in FIG. 1, the etch stop layer 22 in the embodiment of the present invention has more layers and a thicker thickness. The thickness of the etching stop layer 22 is increased, so that in the process of etching to form the through hole, the hillock on the top metal layer 213 can always be covered and protected by the thicker etch stop layer 22, and the bottommost structure of the etch stop layer 22 is pressed by the non-bottommost structure, which can improve the situation that the bottommost structure of the etch stop layer 22 is broken by the hillock on the top metal layer 213. In addition, after the through hole is etched, at least a portion of the etch stop layer 22 remains at the bottom of the through hole without being etched through, that is, the bottommost structure of the entire thickness of the etch stop layer 22 covers the top metal layer 213, so that during the subsequent wet cleaning process, the bottommost structure of the etch stop layer 22 can continue to protect the hillock on the top metal layer 213. Therefore, the embodiment of the present invention can prevent the hillock on the top metal layer 213 from being exposed during and after etching the through hole, and further prevent the hillock on the top metal layer 213 from reacting with the cleaning solution during the wet cleaning process, thereby improving the metal diffusion problem.

In some embodiments, when the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top, or when the etch stop layer 22 includes an oxide layer and a silicon nitride layer stacked from bottom to top, since the brittleness of oxides such as silicon oxide and/or silicon oxynitride is lower than that of silicon nitride, the oxide has better coating properties, and thus if the oxide layer coats the first silicon nitride layer, the first silicon nitride layer is not easy to crack, and if the oxide layer directly coats the hillock, the oxide layer is not easy to crack. Therefore, the hillock on the top metal layer 213 can be further prevented from being exposed when etching to form the through hole.

In some embodiments, when the etch stop layer 22 includes a first silicon nitride layer 221, an oxide layer 222, and a second silicon nitride layer 223 stacked from bottom to top, and the etching stops at the second silicon nitride layer 223 when forming the through hole, even if the first silicon nitride layer 221 is cracked, the oxide layer 222 serves as a buffer layer to cover the cracked first silicon nitride layer 221 and the hillock on the top metal layer 213, thereby further preventing the hillock on the top metal layer 213 from being exposed.

From the above content, it can be seen that, since the etch stop layer 22 can ensure that the hillocks on the top metal layer 213 are always protected and prevented from being exposed during the manufacturing process of the semiconductor element, the metal diffusion problem is improved, and pits (i.e., pits 122 in FIG. 2) are prevented from forming in the top metal layer 213, and metal diffusion to the through hole and the groove surface is prevented, thereby avoiding electrical connection problems or even circuit breaks between the subsequently bonded wafers, thereby improving the hybrid bonding yield.

It should be noted that the semiconductor element provided by the present invention can be a wafer structure or a chip structure, and the wafer structure includes the chip structures arranged in an array, and cutting paths are provided between adjacent chip structures. By cutting the wafer structure along the cutting paths, the chip structures arranged in an array can be separated.

The semiconductor element shown in Figure 4k can be a part of the wafer structure or the chip structure.

The wafer 21 in the wafer structure may be a device wafer or a carrier wafer.

The component wafer may be a pixel wafer including a pixel array of an image sensor, or a MEMS wafer including a MEMS microstructure of a MEMS component, or a MOSFET wafer including a power component, or an IGBT wafer, or a passive component wafer, etc. The type of the component wafer depends on the function of the component to be manufactured in the end. The carrier wafer may not include a functional structure. Alternatively, the carrier wafer may include a functional structure, and the functional structure is located inside the carrier wafer rather than on the surface of the carrier wafer. In some embodiments, the functional structure included in the carrier wafer may also be located inside and/or on the surface of the wafer edge.

In summary, the present invention provides a semiconductor element, comprising: a substrate, a top metal layer formed on the substrate; an etch stop layer, covering the top metal layer, the etch stop layer being a stacked structure of at least two layers, and a through hole exposing the top metal layer is formed in the etch stop layer; a bonding layer, forming A trench is formed in the bonding layer on the etch stop layer, the through hole extends from the etch stop layer to the bonding layer and is connected to the trench, and the width of the trench is greater than the width of the through hole; a metal layer is filled in the trench and the through hole, and the metal layer is connected to the top metal layer. The semiconductor element provided by the present invention can improve the metal diffusion problem, thereby improving the hybrid bonding yield. The above is only a preferred embodiment of the present invention, and all equal changes and modifications made according to the scope of the patent application of the present invention should be covered by the present invention.

11: Wafer 12: Top metal layer 13: Silicon nitride layer 14: Bonding layer 21: Wafer 22: Etch stop layer 23: Bonding layer 24: Via hole 25: Protective layer 26: Trench 27: Metal layer 121: Hillock 122: Pits 211: Substrate 212: Insulating dielectric layer 213: Top metal layer 221: First silicon nitride layer 222: Oxide layer 223: Second silicon nitride layer 231: First dielectric layer 232: Second dielectric layer 233: third dielectric layer 241: first patterned photoresist layer 261: second patterned photoresist layer S1: step S2: step S3: step S4: step S5: step S6: step S7: step S8: step

FIG. 1 is a schematic diagram showing the formation of hillocks on the top metal layer in a wafer of the prior art. FIG. 2 is a scanning electron microscope image showing metal diffusion in the top metal layer in a wafer of the prior art. FIG. 3 is a flow chart of a method for manufacturing a semiconductor element of an embodiment of the present invention. FIG. 4a to FIG. 4k are schematic cross-sectional views of the steps of the manufacturing method shown in FIG. 3 of a semiconductor element of an embodiment of the present invention.

S1: Steps

S2: Step

S3: Step

S4: Step

S5: Step

S6: Step

S7: Step

S8: Step

Claims (10)

A method for manufacturing a semiconductor element, comprising: Providing a wafer, the wafer having a top metal layer and an etch stop layer covering the top metal layer, the etch stop layer being a structure of at least two stacked layers; Forming a bonding layer on the etch stop layer; Etching the bonding layer, and the etching stops in a non-bottommost structure of the etch stop layer to form at least one through hole; Filling a protective layer in the through hole; Etching away a portion of the protective layer in the through hole and the bonding layer at the top of the through hole sidewall to form a trench at the top of the through hole; Removing the remaining protective layer; Etching away the etch stop layer at the bottom surface of the through hole to expose the top metal layer; and Filling a metal layer in the trench and the through hole, wherein the metal layer is connected to the top metal layer. A method for manufacturing a semiconductor device as described in claim 1, wherein: The etch stop layer includes an oxide layer and a silicon nitride layer stacked from bottom to top, wherein the step of forming the through hole is to stop etching in the silicon nitride layer; or The etch stop layer includes a first silicon nitride layer, an oxide layer and a second silicon nitride layer stacked from bottom to top, wherein the step of forming the through hole is to stop etching in the second silicon nitride layer or the oxide layer. A method for manufacturing a semiconductor device as described in claim 2, wherein the material of the oxide layer includes silicon oxide and/or silicon oxynitride. A method for manufacturing a semiconductor device as described in claim 1, wherein the bonding layer is a multi-layer stacked structure. A method for manufacturing a semiconductor device as described in claim 1, wherein the protective layer includes at least one of an anti-reflective layer, a spin-on carbon layer and a spin-on glass layer. A method for manufacturing a semiconductor element as described in any one of claims 1 to 5, wherein the method for manufacturing a semiconductor element further comprises: Bonding at least two of the wafers, wherein the bonding layers on adjacent wafers are bonded to each other, and the metal layers on adjacent wafers are bonded to each other. A semiconductor element comprises: a substrate, a top metal layer formed on the substrate; an etch stop layer covering the top metal layer, the etch stop layer being a structure of at least two layers stacked, and at least one through hole formed in the etch stop layer to expose the top metal layer; a bonding layer formed on the etch stop layer, a trench formed in the bonding layer, the through hole extending from the etch stop layer to the bonding layer and communicating with a trench formed in the bonding layer, wherein a width of the trench is greater than a width of the through hole; and A metal layer is filled in the trench and the through hole, wherein the metal layer is connected to the top metal layer. A semiconductor device as described in claim 7, wherein: The etch stop layer includes an oxide layer and a silicon nitride layer stacked from bottom to top; or The etch stop layer includes a first silicon nitride layer, an oxide layer, and a second silicon nitride layer stacked from bottom to top. A semiconductor device as described in claim 8, wherein the material of the oxide layer includes silicon oxide and/or silicon oxynitride. A semiconductor element as described in any one of claims 7 to 9, wherein the semiconductor element includes at least two bonded substrates, wherein the bonding layers adjacent to the substrates are bonded, and the metal layers adjacent to the substrates are bonded.