TW202447716A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate, a first electrode layer, a second electrode layer, a hard mask layer, and a plurality of trenches. The first electrode layer is located on the semiconductor substrate. The second electrode layer is located on the first electrode layer. The hard mask layer is located on the second electrode layer. The trenches are located in the first electrode layer, the second electrode layer, and the hard mask layers. Each one of the trenches has a lower portion and an upper portion, in which the lower portion is located in the first electrode layer and the second electrode layer, the upper portion is located in the hard mask layer, and the width of the lower portion is smaller than the width of the upper portion. The differences in width between the upper portions of the trenches and the lower portions of the trenches are the same.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure.

With the advancement of technology, the size of integrated circuit chips is getting smaller and smaller, and the inside of the chip contains many semiconductor structures such as diodes, transistors and capacitors. In the process of integrated circuit chips, as the size of the chip shrinks, the trenches of the semiconductor structure will also become narrower, increasing its aspect ratio, which in turn leads to defects in the material filling the trench. In the traditional process, the thickness of the hard mask layer of the semiconductor structure is reduced to reduce the aspect ratio of the trench to avoid defects in the material filling the trench. However, in the subsequent etching process, if the hard mask layer is not thick enough, the semiconductor structure underneath will be damaged and the yield of the process will be reduced.

One technical aspect of the present disclosure is a semiconductor structure.

According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate, a first electrode layer, a second electrode layer, a hard mask layer, and a plurality of trenches. The first electrode layer is located on the semiconductor substrate. The second electrode layer is located on the first electrode layer. The hard mask layer is located on the second electrode layer. The trenches are located in the first electrode layer, the second electrode layer, and the hard mask layer. Each of the trenches has a lower portion and an upper portion. The lower portion is located in the first electrode layer and the second electrode layer, and the upper portion is located in the hard mask layer. The width of the lower portion is smaller than the width of the upper portion. The width difference between the upper portions and the lower portions of these trenches is the same.

In some embodiments, the second electrode layer further includes a plurality of segments, and the hard mask layer further includes a plurality of segments. The width of the segments of the second electrode layer is greater than the width of the segments of the hard mask layer.

In some embodiments, the first electrode layer includes a plurality of segments, and the widths of the segments of the second electrode layer are respectively equal to the widths of the segments of the first electrode layer.

In some embodiments, the side walls of the segments of the first electrode layer are coplanar with the side walls of the segments of the second electrode layer.

In some embodiments, the sidewalls of each of the segments of the hard mask layer and the top surface and the sidewalls of the corresponding segment of the second electrode layer define a stepped surface.

In some embodiments, the semiconductor structure further includes an insulating layer, which covers the sidewall of the first electrode layer facing the lower portion of the trench, the sidewall of the second electrode layer facing the lower portion of the trench, and the sidewall and top surface of the hard mask layer facing the upper portion of the trench.

In some embodiments, the material of the insulating layer includes silicon nitride or silicon dioxide.

In some embodiments, the material of the first electrode layer includes polysilicon, the material of the second electrode layer includes tungsten, and the material of the hard mask layer includes silicon nitride.

Another technical aspect of the present disclosure is a method for manufacturing a semiconductor structure.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes sequentially forming a first electrode layer, a second electrode layer, and a hard mask layer on a semiconductor substrate, wherein the hard mask layer is covered by a patterned photoresist layer; removing the hard mask layer not covered by the photoresist layer; forming an oxide layer on the top surface of the second electrode layer, the sidewalls of the hard mask layer, the sidewalls and the top surface of the photoresist layer; removing the oxide layer on the top surface of the photoresist layer and the second electrode layer; and removing the oxide layer on the top surface of the photoresist layer and the second electrode layer. The oxide layer on the top surface of the second electrode layer exposes multiple portions of the second electrode layer; these portions of the second electrode layer and the first electrode layer thereunder are removed to form multiple trenches; and the oxide layer on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer is removed so that each of the trenches has a narrower lower portion and a wider upper portion, wherein the lower portion is located in the first electrode layer and the second electrode layer, and the upper portion is located in the hard mask layer.

In some embodiments, the removal of the oxide layer on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer allows the oxide layer to define a width difference between an upper portion and a lower portion of each of the trenches.

In some embodiments, the method for manufacturing the semiconductor structure further includes removing the photoresist layer to expose the hard mask layer after removing the portions of the second electrode layer and the first electrode layer thereunder.

In some embodiments, the manufacturing method of the above-mentioned semiconductor structure further includes forming an insulating layer to cover the sidewalls of the first electrode layer facing the lower part of the trench, the sidewalls of the second electrode layer facing the lower part of the trench, and the sidewalls and top surface of the hard mask layer facing the upper part of the trench after removing the oxide layer located on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer.

In some embodiments, the oxide layer is formed on the top surface of the second electrode layer, the sidewalls of the hard mask layer, and the sidewalls and top surface of the photoresist layer by in-situ atomic layer deposition.

In the above-mentioned embodiments of the present disclosure, since each trench of the semiconductor structure has a lower portion and an upper portion, the lower portion is located in the first electrode layer and the second electrode layer, and the upper portion is located in the hard mask layer, and the width of the lower portion is smaller than the width of the upper portion, defects caused by the aspect ratio of the trench in the material subsequently filled in the trench can be avoided. In addition, since the aspect ratio of the trench can be reduced while maintaining the thickness of the hard mask layer, a sufficiently thick hard mask layer can be provided in the subsequent patterning etching process to avoid damage to the semiconductor substrate, the first electrode layer, and the second electrode layer below the hard mask layer, thereby improving the yield of the process.

The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. As shown in the figure, the semiconductor structure 100 includes a semiconductor substrate 110, a first electrode layer 120, a second electrode layer 130, a hard mask layer 140 and a plurality of trenches 150. The first electrode layer 120 is located on the semiconductor substrate 110. The second electrode layer 130 is located on the first electrode layer 120. The hard mask layer 140 is located on the second electrode layer 130. The trenches 150 are located in the first electrode layer 120, the second electrode layer 130 and the hard mask layer 140. Each of the trenches 150 has a lower portion 151 and an upper portion 152, wherein the lower portion 151 is located in the first electrode layer 120 and the second electrode layer 130, and the upper portion 152 is located in the hard mask layer 140. The width W1 of the lower portion 151 is smaller than the width W2 of the upper portion 152. The width difference between the upper portion 152 and the lower portion 151 thereunder of all trenches 150 is the same. In some embodiments, the first electrode layer 120 can serve as a lower electrode of a bit line structure, and the second electrode layer 130 can serve as an upper electrode of the bit line structure. The hard mask layer 140 can protect the semiconductor substrate 110, the first electrode layer 120 and the second electrode layer 130 below the hard mask layer 140 in a subsequent etching process, and can remove the semiconductor substrate 110 below the trench 150 by etching.

Since each of the trenches 150 of the semiconductor structure 100 has a lower portion 151 and an upper portion 152, the lower portion 151 is located in the first electrode layer 120 and the second electrode layer 130, and the upper portion 152 is located in the hard mask layer 140, and the width W1 of the lower portion 151 is smaller than the width W2 of the upper portion 152, the aspect ratio can be effectively reduced. In this way, in subsequent manufacturing processes, defects caused by the aspect ratio of the trench 150 can be avoided in the material filled in the trench 150. In addition, since the aspect ratio of the trench 150 can be reduced while maintaining the thickness of the hard mask layer 140, a sufficiently thick hard mask layer 140 can be provided to provide protection in the subsequent patterning etching process to prevent the semiconductor substrate 110, the first electrode layer 120 and the second electrode layer 130 under the hard mask layer 140 from being damaged, thereby improving the process yield.

In this embodiment, the second electrode layer 130 of the semiconductor structure 100 may further include a plurality of segments 131, 132, and 133, and the hard mask layer 140 may include a plurality of segments 141, 142, and 143. The widths of the segments 131, 132, and 133 of the second electrode layer 130 are respectively greater than the widths of the segments 141, 142, and 143 of the hard mask layer. In addition, the first electrode layer 120 may include a plurality of segments 121, 122, and 123. The widths of the segments 131, 132, and 133 of the second electrode layer 130 are respectively equal to the widths of the segments 121, 122, and 123 of the first electrode layer 120. In this way, the width of the lower portion 151 of the trench 150 in the first electrode layer 120 and the second electrode layer 130 can be smaller than the width of the upper portion 152 of the trench 150 in the hard mask layer 140, so as to facilitate subsequent material filling to avoid defects. In addition, such a design allows the sections 141, 142, and 143 of the hard mask layer 140 with narrower width to have a greater thickness to provide protection in the subsequent patterning etching step.

In addition, the sidewalls of the segments 121, 122, and 123 of the first electrode layer 120 of the semiconductor structure 100 are coplanar with the sidewalls of the segments 131, 132, and 133 of the second electrode layer 130. Each of the sidewalls of the segments 141, 142, and 143 of the hard mask layer 140 defines a stepped surface with the top surface and sidewalls of the corresponding segment 131, 132, or 133 of the second electrode layer 130, and such a design is beneficial to subsequent material filling.

In this embodiment, the semiconductor structure 100 may further include an insulating layer 160. The insulating layer 160 covers the sidewalls of the first electrode layer 120 facing the lower portion 151 of the trench 150, the sidewalls of the second electrode layer 130 facing the lower portion 151 of the trench 150, and the sidewalls and top surface of the hard mask layer 140 facing the upper portion 152 of the trench 150. In some embodiments, the segments 121, 122, and 123 of the first electrode layer 120 may serve as the lower electrode of the bit line structure, the segments 131, 132, and 133 of the second electrode layer 130 may serve as the upper electrode of the bit line structure, and the insulating layer 160 may serve as a spacer of the bit line structure. The insulating layer 160 as a spacer may prevent the upper electrode and the lower electrode of the bit line structure from being connected or contacting with subsequent filling materials.

In addition, the material of the first electrode layer 120 of the semiconductor structure 100 may include polysilicon, the material of the second electrode layer 130 may include tungsten, the material of the hard mask layer 140 may include silicon nitride, and the material of the insulating layer 160 may include silicon nitride or silicon dioxide. The above are only examples and are not intended to limit the present disclosure.

It should be understood that the structures, materials and functions that have been described will not be repeated, and are described first. In the following description, the manufacturing method of the semiconductor structure according to some embodiments of the present disclosure will be described.

Figure 2 shows a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. The method for manufacturing a semiconductor structure includes the following steps. In step S1, a first electrode layer, a second electrode layer and a hard mask layer are sequentially formed on a semiconductor substrate, wherein the hard mask layer is covered by a patterned photoresist layer. Thereafter, in step S2, the hard mask layer not covered by the photoresist layer is removed so that the hard mask layer and the photoresist layer have the same pattern. Then, in step S3, an oxide layer is formed on the top surface of the second electrode layer, the side walls of the hard mask layer, and the side walls and top surface of the photoresist layer. Thereafter, in step S4, the oxide layer located on the top surface of the photoresist layer and the top surface of the second electrode layer is removed to expose a plurality of portions of the second electrode layer. Then, in step S5, these portions of the second electrode layer and the first electrode layer thereunder are removed to form a plurality of trenches. Then, in step S6, the oxide layer located on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer is removed so that each of the trenches has a narrower lower portion and a wider upper portion, wherein the lower portion is located in the first electrode layer and the second electrode layer, and the upper portion is located in the hard mask layer. In addition, in some implementations, steps S1 to S6 may each include multiple detailed steps, and other steps may be included before step S1 and after step S6. In the following description, at least the above steps S1 to S6 are described.

FIG. 3 to FIG. 7 illustrate cross-sectional views of the manufacturing method of the semiconductor structure 100 of FIG. 1 at an intermediate stage. Referring to FIG. 3, the manufacturing method of the semiconductor structure 100 includes sequentially forming a first electrode layer 120, a second electrode layer 130, and a hard mask layer 140 on a semiconductor substrate 110. Then, the hard mask layer 140 is covered by a patterned photoresist layer 170, and the hard mask layer 140 not covered by the photoresist layer 170 is removed, so that the hard mask layer 140 and the photoresist layer 170 have the same pattern. As such, the hard mask layer 140 may include a plurality of segments 141 , 142 , and 143 and may expose the second electrode layer 130 that is not covered by the segments 141 , 142 , and 143 .

Referring to FIG. 4 , an in-situ atomic layer deposition (ALD) method may then be used to form an oxide layer 180 on the exposed top surface of the second electrode layer 130, the sidewalls of the hard mask layer 140, and the sidewalls and top surface of the photoresist layer 170. In this way, the sidewalls of the sections 141, 142, and 143 of the hard mask layer 140 may be covered by the oxide layer 180.

Referring to FIG. 5 and FIG. 6 at the same time, the oxide layer 180 located on the top surface of the photoresist layer 170 and the top surface of the second electrode layer 130 can then be removed to expose a plurality of portions of the second electrode layer 130. In addition, the oxide layer 180 covering the sidewalls of the sections 141, 142, and 143 of the hard mask layer 140 can be used as a hard mask for a subsequent etching process. Then, the exposed portions of the second electrode layer 130 not covered by the photoresist layer 170 and the oxide layer 180 and the first electrode layer 120 thereunder can be removed to form a plurality of trenches 150. In this way, the first electrode layer 120 can form a plurality of segments 121, 122, and 123, the second electrode layer 130 can form a plurality of segments 131, 132, and 133, and the widths of the segments 121, 122, and 123 of the first electrode layer 120 are respectively equal to the widths of the segments 131, 132, and 133 of the second electrode layer 130. In addition, since the oxide layer 180 can be used as a hard mask for the etching process and has a thickness, the widths of the segments 131, 132, and 133 of the second electrode layer 130 are respectively greater than the widths of the segments 141, 142, and 143 of the hard mask layer 140.

7 , after forming a plurality of trenches 150, hydrofluoric acid (HF) may be used as an etchant to remove the oxide layer 180 located on the sidewalls of the hard mask layer 140 and the sidewalls of the photoresist layer 170, so that each of the trenches 150 has a narrower lower portion 151 and a wider upper portion 152, wherein the lower portion 151 is located in the first electrode layer 120 and the second electrode layer 130, and the upper portion 152 is located in the hard mask layer 140. In other words, the first electrode layer 120 and the second electrode layer 130 surround the lower portion 151 of the trench 150, and the hard mask layer 140 surrounds the lower portion 151 of the trench 150. Specifically, the oxide layer 180 of FIG6 defines a width difference between the lower portion 151 and the upper portion 152 of the trench 150 of FIG7. In addition, the photoresist layer 170 may be removed to expose the hard mask layer 140.

Referring to FIG. 1 , after removing the oxide layer 180 on the sidewalls of the hard mask layer 140 and the sidewalls of the photoresist layer 170, an insulating layer 160 is formed to cover the sidewalls of the first electrode layer 120 facing the lower portion 151 of the trench 150, the sidewalls of the second electrode layer 130 facing the lower portion 151 of the trench 150, and the sidewalls and top surface of the hard mask layer 140 facing the upper portion 152 of the trench 150. In some embodiments, the first electrode layer 120, the second electrode layer 130, and the insulating layer 160 can serve as the lower electrode, the upper electrode, and the spacer of the bit line structure, respectively. In addition, in the subsequent steps of FIG. 1 , a conductive structure may be formed in the trench 150 , wherein the material of the conductive structure may be polysilicon, but this is not intended to limit the present disclosure.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: semiconductor structure 110: semiconductor substrate 120: first electrode layer 121: section 122: section 123: section 130: second electrode layer 131: section 132: section 133: section 140: hard mask layer 141: section 142: section 143: section 150: trench 151: lower part 152: upper part 160: insulating layer 170: photoresist layer 180: oxide layer W1: width W2: width S1, S2, S3, S4, S5, S6: steps

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a semiconductor structure according to an embodiment of the disclosure. FIG. 2 illustrates a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure. FIGS. 3 to 7 illustrate cross-sectional views of the method for manufacturing the semiconductor structure of FIG. 1 at intermediate stages.

100:Semiconductor structure

110:Semiconductor substrate

120: First electrode layer

121: Section

122: Section

123: Section

130: Second electrode layer

131: Section

132: Section

133: Section

140: Hard mask layer

141: Section

142: Section

143: Section

150: Groove

151: Lower part

152: Upper part

160: Insulation layer

W1: Width

W2: Width

Claims (13)

A semiconductor structure includes: a semiconductor substrate; a first electrode layer located on the semiconductor substrate; a second electrode layer located on the first electrode layer; a hard mask layer located on the second electrode layer; and a plurality of trenches located in the first electrode layer, the second electrode layer and the hard mask layer, each of the trenches having a lower portion and an upper portion, the lower portion being located in the first electrode layer and the second electrode layer, and the upper portion being located in the hard mask layer, wherein the width of the lower portion is smaller than the width of the upper portion, and the width difference between the upper portions of the trenches and the lower portions is the same. A semiconductor structure as described in claim 1, wherein the second electrode layer includes a plurality of segments, the hard mask layer includes a plurality of segments, and the widths of the segments of the second electrode layer are respectively greater than the widths of the segments of the hard mask layer. A semiconductor structure as described in claim 2, wherein the first electrode layer includes a plurality of segments, and the widths of the segments of the second electrode layer are respectively equal to the widths of the segments of the first electrode layer. A semiconductor structure as described in claim 3, wherein the plurality of side walls of the segments of the first electrode layer are coplanar with the plurality of side walls of the segments of the second electrode layer. A semiconductor structure as described in claim 2, wherein the side walls of each of the segments of the hard mask layer and the top surface and side walls of the corresponding segment of the second electrode layer define a stepped surface. The semiconductor structure as described in claim 1 further includes: An insulating layer covering the plurality of side walls of the first electrode layer facing the lower portions of the trenches, the plurality of side walls of the second electrode layer facing the lower portions of the trenches, and the plurality of side walls and the plurality of top surfaces of the hard mask layer facing the upper portions of the trenches. A semiconductor structure as described in claim 6, wherein the material of the insulating layer is silicon nitride or silicon dioxide. A semiconductor structure as described in claim 1, wherein the material of the first electrode layer is polysilicon, the material of the second electrode layer is tungsten, and the material of the hard mask layer is silicon nitride. A method for manufacturing a semiconductor structure, comprising: Sequentially forming a first electrode layer, a second electrode layer and a hard mask layer on a semiconductor substrate, wherein the hard mask layer is covered by a patterned photoresist layer; Removing the hard mask layer not covered by the photoresist layer; Forming an oxide layer on a top surface of the second electrode layer, a plurality of side walls of the hard mask layer, a plurality of side walls of the photoresist layer and a plurality of top surfaces; Removing the oxide layer located on the top surfaces of the photoresist layer and the top surface of the second electrode layer to expose a plurality of portions of the second electrode layer; Removing the portions of the second electrode layer and the first electrode layer thereunder to form a plurality of trenches; and Removing the oxide layer on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer so that each of the trenches has a narrower lower portion and a wider upper portion, wherein the lower portion is located in the first electrode layer and the second electrode layer, and the upper portion is located in the hard mask layer. A method for manufacturing a semiconductor structure as described in claim 9, wherein the oxide layer located on the sidewalls of the hard mask layer and the sidewalls of the photoresist layer is removed so that the oxide layer defines a width difference between the upper portion and the lower portion of each of the trenches. The method for manufacturing a semiconductor structure as described in claim 9 further includes: After removing the portions of the second electrode layer and the first electrode layer thereunder, removing the photoresist layer to expose the hard mask layer. The method for manufacturing a semiconductor structure as described in claim 9 further includes: After removing the oxide layer located on the side walls of the hard mask layer and the side walls of the photoresist layer, an insulating layer is formed to cover the plurality of side walls of the first electrode layer facing the lower portions of the trenches, the plurality of side walls of the second electrode layer facing the lower portions of the trenches, and the side walls and the plurality of top surfaces of the hard mask layer facing the upper portions of the trenches. A method for manufacturing a semiconductor structure as described in claim 9, wherein the oxide layer is formed on the top surface of the second electrode layer, the side walls of the hard mask layer, the side walls and the top surface of the photoresist layer using an in-situ atomic layer deposition method.