TW202445189A - Package comprising an optical integrated device - Google Patents

Abstract

A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Description

Package including optically integrated components

Cross-references to related applications

This application claims priority to and the benefit of: (i) U.S. Nonprovisional Application Serial No. 18/607,170, filed in the U.S. Patent and Trademark Office on March 15, 2024; and (ii) U.S. Provisional Application Serial No. 63/491,982, filed in the U.S. Patent and Trademark Office on March 24, 2023, both of which are incorporated herein by reference in their entirety as if fully set forth below and for all applicable purposes.

Various features relate to packages including integrated components.

A package may include a substrate and an integrated element. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components may depend on many factors. There is a continuing need to provide a package that provides improved performance. In addition, there is a continuing need to include a package that includes a more compact form factor so that the package can be implemented in a smaller device.

Various features relate to packages including integrated components.

One example provides a package comprising: a packaging substrate; a first integrated component coupled to the packaging substrate via a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated component; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated component coupled to the metallization portion via a second plurality of solder interconnects; an optical integrated component coupled to the packaging substrate; and an optical fiber coupled to the optical integrated component.

Another example provides a package comprising: a metallized portion; a first integrated element coupled to the metallized portion via a first plurality of solder interconnects, wherein a front face of the first integrated element is oriented in a direction toward the metallized portion; an encapsulation layer at least partially encapsulating the first integrated element; a plurality of post interconnects in the encapsulation layer; a second integrated element coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated element coupled to the metallized portion via a third plurality of solder interconnects; an optical fiber coupled to the optical integrated element; and a packaging substrate coupled to the plurality of post interconnects via a fourth plurality of solder interconnects.

In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, a person skilled in the art will understand that various aspects may be practiced without these specific details. For example, circuits may be illustrated in blocks to avoid obscuring the aspects in unnecessary detail. In other examples, known circuits, structures, and techniques may not be shown in detail so as not to obscure various aspects of the present disclosure.

The present disclosure describes a package including: a package substrate; a first integrated component coupled to the package substrate via a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated component; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated component coupled to the metallization portion via a second plurality of solder interconnects; an optical integrated component coupled to the package substrate; and an optical fiber coupled to the optical integrated component. The optical integrated component coupled to the package substrate provides a short distance for at least one circuit path to various integrated components of the package. In addition, the optical integrated component provides a small IR drop closer to the integrated component, which helps to improve the performance of the integrated component and/or the package. Exemplary package including an optical integrated component

1 shows a cross-sectional view of a package 100 including an optical integration component. The package 100 includes an optical integration component 101, a package substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, and an encapsulation layer 106.

The packaging substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122 (e.g., substrate interconnects). The optical integration component 101 is coupled to the packaging substrate 102. For example, the optical integration component 101 can be embedded in the packaging substrate 102. In some implementations, the optical integration component 101 can be located in a cavity of the packaging substrate 102. The optical integration component 101 can be coupled to the packaging substrate 102 via an adhesive (not shown). The optical fiber 110 is coupled to the optical integration component 101. The optical fiber 110 can be considered to be part of the package 100. The optical fiber 110 can be coupled to another optical integration component (not shown). The other optical integration component can be coupled to another package or board. An example of the optical integration component 101 is shown and described below in FIG. 7 . The optical integration element may include the following capabilities: (i) converting optical signals/energy into electrical signals/energy, and/or (ii) converting electrical signals/energy into optical signals/energy. For example, a signal can be received as an optical signal and can be converted into an electrical signal. Similarly, a signal can be received as an electrical signal and can be converted into an optical signal. The optical integration element can send the signal as an optical signal and/or an electrical signal. More detailed examples of optical integration elements are shown and described below in at least Figures 7 and 8. In some implementations, the optical integration element 101 can be implemented as an optical integration element 700 and/or an optical integration element 800.

The encapsulation layer 106 may at least partially encapsulate the integrated element 103, the integrated element 105, and the plurality of pillar interconnects 160. The integrated element 103 is coupled to the package substrate 102 through a solder interconnect from the plurality of solder interconnects 123. The front side of the integrated element 103 is facing the package substrate 102. For example, the surface of the front side of the integrated element 103 may be oriented in a direction toward the package substrate 102. The integrated element 105 is coupled to the package substrate 102 through a solder interconnect from the plurality of solder interconnects 123. The front side of the integrated element 105 is facing the package substrate 102. For example, the surface of the front side of the integrated element 105 may be oriented in a direction toward the package substrate 102. The plurality of pillar interconnects 160 are coupled to the package substrate 102 through other solder interconnects from the plurality of solder interconnects 123. An underfill 125 is present between the package substrate 102 and the encapsulation layer 106. The underfill 125 may laterally surround the plurality of solder interconnects 123. The underfill 125 may be coupled to and contact the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated component 103, and the integrated component 105.

The metallization portion 104 is coupled to the encapsulation layer 106 and the plurality of pillar interconnects 160. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may be a redistribution portion. The plurality of metallization interconnects 142 may include redistribution interconnects. The plurality of pillar interconnects 160 are coupled to metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104. The back side of the integrated element 103 may face the metallization portion 104. For example, the surface of the back side of the integrated element 103 may be oriented in a direction toward the packaging substrate 104. The back side of the integrated element 105 may face the metallization portion 104. For example, the surface of the back side of the integrated element 105 may be oriented in a direction toward the metallization portion 104. The bottom surface of the metallization portion 104 may be coupled to the encapsulation layer 106.

The passive component 111 can be coupled to the top surface of the metallization portion 104 through the plurality of solder interconnects 112. For example, the passive component 111 can be coupled to the metallization interconnects from the plurality of metallization interconnects 142 through the plurality of solder interconnects 112.

The integrated component 109 can be coupled to the top surface of the metallized portion 104 through the plurality of solder interconnects 190. For example, the integrated component 109 can be coupled to the metallized interconnects from the plurality of metallized interconnects 142 through the plurality of solder interconnects 190. The integrated component 130 can be coupled to the top surface of the metallized portion 104 through the plurality of solder interconnects 131. For example, the integrated component 130 can be coupled to the metallized interconnects from the plurality of metallized interconnects 142 through the plurality of solder interconnects 131.

Integrated element 132 is coupled to integrated element 130 via a plurality of solder interconnects 133. Integrated element 134 is coupled to integrated element 132 via a plurality of solder interconnects 135. Integrated element 130, integrated element 132, and integrated element 134 may be stacked integrated elements.

The connector socket 107 is coupled to the top surface of the metallized portion 104 via a plurality of solder interconnects 170. The connector socket 107 is configured to be electrically coupled to the connector socket 113. The connector socket 107 is configured to provide an electrical path for power. The connector socket 107 is configured to provide an electrical path for grounding. The connector socket 107 can be coupled to the connector socket 113 via one or more wires.

Package 100 is coupled to board 108 via a plurality of solder interconnects 183. Board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. Connector socket 113 is coupled to board 108 via a plurality of solder interconnects 114. Connector sockets (e.g., 107, 113) may include a plurality of connector interconnects. The connector socket may include a connector housing, wherein the plurality of connector interconnects may be at least partially located in the connector housing. One or more wires coupled to the connector socket may include wire interconnects and a dielectric layer surrounding the one or more wires.

The optical fiber 110 is coupled to the optical integration component 101. The optical fiber 110 can extend through the packaging substrate 102. The optical fiber 110 can extend through a cavity in the packaging substrate 102. In some implementations, the optical fiber 110 can extend in the board 108. In some implementations, the optical fiber 110 can extend between the packaging substrate 102 and the board 108. One or more optical signals can travel to and/or from the optical integration component 101 through the optical fiber 110.

Integrating component 103 may be configured to be electrically coupled to optical integrating component 101 via circuit 151, which includes a solder interconnect from a plurality of solder interconnects 123. Integrating component 105 may be configured to be electrically coupled to optical integrating component 101 via circuit 153, which includes a solder interconnect from a plurality of solder interconnects 123. Integrating component 103 may be configured to be electrically coupled to optical integrating component 101 via a circuit including a solder interconnect from a plurality of solder interconnects 123, optical integrating component 101, and another solder interconnect from the plurality of solder interconnects. The integrated component 130 can be configured to be electrically coupled to the optical integrated component 101 through an electrical path 155, which includes solder interconnects from the plurality of solder interconnects 131, metallization interconnects from the metallization portion 104, pillar interconnects from the plurality of pillar interconnects 160, and solder interconnects from the plurality of solder interconnects 123. The electrical path 155 can include an electrical path between the integrated component 130 and the integrated component 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

Integrated component 130 may be configured to be electrically coupled to integrated component 103 via electrical path 157, which includes a solder interconnect from plurality of solder interconnects 131, a metallization interconnect from metallization 104, a post interconnect from plurality of post interconnects 160, a solder interconnect from plurality of solder interconnects 123, an interconnect from package substrate 102, and another solder interconnect from plurality of solder interconnects 123. Electrical path 157 may include an electrical path between integrated component 130 and integrated component 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through-substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through-substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

Integrated component 130 may be configured to be electrically coupled to integrated component 105 via electrical path 159, which includes a solder interconnect from plurality of solder interconnects 131, a metallization interconnect from metallization 104, a post interconnect from plurality of post interconnects 160, a solder interconnect from plurality of solder interconnects 123, an interconnect from package substrate 102, and another solder interconnect from plurality of solder interconnects 123. Electrical path 159 may include an electrical path between integrated component 130 and integrated component 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through-substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through-substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

In some implementations, the optical signal may be received by the optical integration component 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integration component 101, and the electrical signal may be sent to the integration component 103, the integration component 105, and/or the integration component 130 using one or more of the above-mentioned electrical circuits.

In some implementations, the optical integration device 101 may receive an electrical signal through one or more of the above-mentioned electrical circuits, convert the electrical signal into an optical signal by the optical integration device 101, and transmit the optical signal through the optical fiber 110.

Integrated component 103 may be a system on chip (SoC). Integrated component 103 may be a system on chip (SoC). Integrated component 109 may include a power management integrated circuit (PMIC). Passive component 111 may include a capacitor. Integrated component 130, integrated component 132, and/or integrated component 134 may include a memory. The circuit between integrated component 109 and integrated component 130 may include solder interconnects from multiple solder interconnects 190, metallized interconnects from multiple metallized interconnects 142, and solder interconnects from multiple solder interconnects 131. The circuit between integrated component 109 and integrated component 134 may include the circuit between integrated component 130 and integrated component 134, as described above.

In some implementations, optical integration component 101 can be configured to operate as a bridge. Integration component 103 can be configured to be electrically coupled to integration component 105 through optical integration component 101. For example, the circuit between integration component 103 and integration component 105 can include optical integration component 101. The circuit between integration component 103 and integration component 105 can include circuit 151 (described above), interconnects from optical integration component 101, and circuit 153 (described above).

2 shows a cross-sectional view of a package 200 including an optical integration component. The package 200 includes an optical integration component 101, a packaging substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one back power rail interconnect 203, and at least one back power rail interconnect 205.

At least one back power rail interconnect 203 can be considered as part of the integrated component 103. For example, at least one back power rail interconnect 203 can be located in the die substrate of the integrated component 103. The back power rail interconnect 203 can include trace interconnects and/or through-substrate vias. The back power rail interconnect 203 can be considered as part of the back side of the integrated component 103. At least one back power rail interconnect 205 can be considered as part of the integrated component 105. For example, at least one back power rail interconnect 205 can be located in the die substrate of the integrated component 105. The back power rail interconnect 205 can include trace interconnects and/or through-substrate vias. The back power rail interconnect 205 can be considered as part of the back side of the integrated component 105.

Package 200 is similar to package 100. However, some of the components of package 200 are positioned and/or coupled differently than some of the components in package 100.

The integrated component 103 is coupled to the bottom surface of the metallized portion 104 via a plurality of solder interconnects 223. The front side of the integrated component 103 can face the metallized portion 104. For example, the surface of the front side of the integrated component 103 can be oriented in a direction toward the metallized portion 104. The integrated component 105 is coupled to the bottom surface of the metallized portion 104 via a plurality of solder interconnects 225. The front side of the integrated component 105 can face the metallized portion 104. For example, the surface of the front side of the integrated component 105 can be oriented in a direction toward the metallized portion 104. The integrated component 109 is coupled to the bottom surface of the metallized portion 104 via a plurality of solder interconnects 190. The passive component 111 is coupled to the bottom surface of the metallized portion 104 via a plurality of solder interconnects 112. Encapsulation layer 106 may at least partially encapsulate integrated element 103, integrated element 105, integrated element 109, passive element 111, back power rail interconnect 203, back power rail interconnect 205, and plurality of pillar interconnects 160. Encapsulation layer 106 may include a molding, a resin, and/or an epoxy. Encapsulation layer 106 may be formed using a compression molding process, a transfer molding process, or a liquid molding process.

The package 200 is coupled to the board 108 via a plurality of solder interconnects 183. The connector socket 113 is coupled to the board 108 via a plurality of solder interconnects 114.

Integrated component 130 may be configured to be electrically coupled to integrated component 103 via electrical path 257, which includes solder interconnects from plurality of solder interconnects 131, metallized interconnects from metallized portion 104, and solder interconnects from plurality of solder interconnects 223. Integrated component 130 may be configured to be electrically coupled to integrated component 105 via electrical path 259, which includes solder interconnects from plurality of solder interconnects 131, metallized interconnects from metallized portion 104, and solder interconnects from plurality of solder interconnects 225. Electrical path 257 may include an electrical path between integrated component 130 and integrated component 134. The electrical path between integrated element 130 and integrated element 134 may include a die interconnect from integrated element 130, a through substrate via from integrated element 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated element 132, a through substrate via from integrated element 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated element 134. In some implementations, a pillar interconnect may exist between: (i) integrated element 130 and integrated element 132, and/or (ii) integrated element 132 and integrated element 134. In such a case, the electrical path between integrated element 130 and integrated element 134 may also include the pillar interconnects described above. The electrical path 259 may include the electrical path between integrated element 130 and integrated element 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through-substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through-substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

The integrated component 130 can be configured to be electrically coupled to the optical integrated component 101 through the electrical path 255, which includes solder interconnects from the plurality of solder interconnects 131, metallization interconnects from the metallization portion 104, pillar interconnects from the plurality of pillar interconnects 160, and solder interconnects from the plurality of solder interconnects 123. The electrical path 255 can include an electrical path between the integrated component 130 and the integrated component 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through-substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through-substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

In some implementations, integrated component 103 can be configured to be electrically coupled to integrated component 105 via plurality of solder interconnects 223 , metallized interconnects from plurality of metallized interconnects 142 , and plurality of solder interconnects 225 .

In some implementations, the integrated component 103 can be configured to be electrically coupled to the integrated component 105 through solder interconnects from the plurality of solder interconnects 123, the optical integrated component 101, and other solder interconnects from the plurality of solder interconnects 123. In some implementations, the optical integrated component 101 can be configured as a bridge. In some implementations, the optical integrated component 101, the integrated component 103, and/or the integrated component 105 can be one or more chiplets. In some implementations, the integrated component 103 can be manufactured using a first technology node, and the integrated component 105 can be manufactured using a second technology node that is not as advanced as the first technology node. The optical integrated component 101 can be manufactured using a third technology node that is different from the first technology node and/or the second technology node.

In some implementations, the optical signal may be received by the optical integration component 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integration component 101, and the electrical signal may be sent to the integration component 103, the integration component 105, and/or the integration component 130 using one or more of the above-mentioned circuits.

In some implementations, the optical integration device 101 may receive an electrical signal through one or more of the above-mentioned electrical circuits, convert the electrical signal into an optical signal by the optical integration device 101, and transmit the optical signal through the optical fiber 110.

The optical integration component 101 is coupled to the packaging substrate 102. For example, the optical integration component 101 can be embedded in the packaging substrate 102. In some implementations, the optical integration component 101 can be located in a cavity of the packaging substrate 102. The optical integration component 101 can be coupled to the packaging substrate 102 via an adhesive (not shown). The optical fiber 110 is coupled to the optical integration component 101. The optical fiber 110 can be considered as part of the package 200.

Power can be provided to integrated component 103 through the back side of integrated component 103. For example, a circuit for providing power to integrated component 103 can include interconnects from plurality of interconnects 122, at least one solder interconnect from plurality of solder interconnects 123, and at least one back power rail interconnect 203. Similarly, power can be provided to integrated component 105 through the back side of integrated component 105. For example, a circuit for providing power to integrated component 105 can include interconnects from plurality of interconnects 122, at least one solder interconnect from plurality of solder interconnects 123, and at least one back power rail interconnect 205.

3 shows a cross-sectional view of a package 300 including an optical integration component. The package 300 includes an optical integration component 101, a packaging substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one back power rail interconnect 203, and at least one back power rail interconnect 205.

Package 300 is similar to package 200. However, some of the components of package 300 are positioned and/or coupled differently than some of the components in package 200.

For example, optical integration component 101 is coupled to the top surface of metallized portion 104 via a plurality of solder interconnects 310. An example of optical integration component 101 is shown and described below in FIG8. Optical integration component 101 is coupled to optical integration component 301 via optical fiber 110. Optical integration component 301 is coupled to board 108. Optical integration component 301 may be coupled to board 108 via a plurality of solder interconnects.

Integrated component 130 may be configured to be electrically coupled to integrated component 103 via an electrical path 257 that includes solder interconnects from plurality of solder interconnects 131, metallization interconnects from metallization 104, and solder interconnects from plurality of solder interconnects 223. Integrated component 130 may be configured to be electrically coupled to integrated component 105 via an electrical path that includes solder interconnects from plurality of solder interconnects 131, metallization interconnects from metallization 104, and solder interconnects from plurality of solder interconnects 225.

The integrated component 130 can be configured to be electrically coupled to the optical integrated component 101 through an electrical path 355, which includes solder interconnects from the plurality of solder interconnects 131, metallized interconnects from the metallized portion 104, and solder interconnects from the plurality of solder interconnects 310. The electrical path 355 can include an electrical path between the integrated component 130 and the integrated component 134. The electrical path between integrated component 130 and integrated component 134 may include a die interconnect from integrated component 130, a through-substrate via from integrated component 130, a solder interconnect from plurality of solder interconnects 133, a die interconnect from integrated component 132, a through-substrate via from integrated component 132, a solder interconnect from plurality of solder interconnects 135, and a die interconnect from integrated component 134. In some implementations, pillar interconnects may exist between: (i) integrated component 130 and integrated component 132, and/or (ii) integrated component 132 and integrated component 134. In such a case, the electrical path between integrated component 130 and integrated component 134 may also include the pillar interconnects described above.

The integrated component 103 may be configured to be electrically coupled to the optical integrated component 101 via an electrical path 353 including solder interconnects from the plurality of solder interconnects 223 , metallized interconnects from the metallized portion 104 , and solder interconnects from the plurality of solder interconnects 310 .

The integrated component 105 may be configured to be electrically coupled to the optical integrated component 101 via an electrical path 357 including solder interconnects from the plurality of solder interconnects 225 , metallized interconnects from the metallized portion 104 , and solder interconnects from the plurality of solder interconnects 310 .

In some implementations, the optical signal may be received by the optical integration component 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integration component 101, and the electrical signal may be sent to the integration component 103, the integration component 105, and/or the integration component 130 using one or more of the above-mentioned circuits.

In some implementations, the optical integration device 101 may receive an electrical signal through one or more of the above-mentioned electrical circuits, convert the electrical signal into an optical signal by the optical integration device 101, and transmit the optical signal through the optical fiber 110.

4 shows a cross-sectional view of a package 400 including an optical integration component. The package 400 includes an optical integration component 101, a packaging substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one back power rail interconnect 203, and at least one back power rail interconnect 205.

Package 400 is similar to package 300. However, some of the components of package 400 are positioned and/or coupled in a different manner than some of the components in package 300. For example, package substrate 102 includes interconnect 122a and interconnect 122b. Interconnect 122a and interconnect 122b are configured as a heat sink in package substrate 102. Board 108 includes board interconnect 182a and board interconnect 182b. Heat sink 403 is coupled to board 108. Thermal interface material can be used to couple heat sink 403 to board 108. Heat sink 405 is coupled to board 108. Thermal interface material can be used to couple heat sink 405 to board 108. Heat generated by the integrated component 103 and/or the back power rail interconnect 203 may be dissipated through the solder interconnects from the plurality of solder interconnects 123, interconnect 122a, solder interconnects from the plurality of solder interconnects 183, board interconnect 182a, and heat sink 403. Heat generated by the integrated component 105 and/or the back power rail interconnect 205 may be dissipated through the solder interconnects from the plurality of solder interconnects 123, interconnect 122b, solder interconnects from the plurality of solder interconnects 183, board interconnect 182b, and heat sink 405.

In some implementations, integrated component 103 may be a first chiplet, and integrated component 105 may be a second chiplet. Integrated component 103 may be configured to perform a first plurality of functions and/or operations. Integrated component 105 may be configured to perform a second plurality of functions and/or operations. The second plurality of functions and/or operations include at least one function and/or operation that is different from the first plurality of functions and/or operations. In some implementations, integrated component 103 may be manufactured using a first technology node, and integrated component 105 may be manufactured using a second technology node that is less advanced than the first technology node.

5 shows a cross-sectional view of a package 500 including an optical integration component. The package 500 includes an optical integration component 101, a packaging substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one back power rail interconnect 203, and at least one back power rail interconnect 205.

Package 500 is similar to package 300 and/or package 400. However, some of the components of package 500 are positioned and/or coupled differently than some of the components in package 300 and/or package 400.

5 , the optical integration component 101 is coupled to the top surface of the metallized portion 104 (e.g., the second integration component) via a plurality of solder interconnects 310. The integration component 109 is coupled to the top surface of the metallized portion 104 via a plurality of solder interconnects 190. The passive component 111 is coupled to the top surface of the metallized portion 104 via a plurality of solder interconnects 112.

In some implementations, an optical signal may be received by optical integration component 101 via optical fiber 110. The optical signal may be converted into an electrical signal by optical integration component 101, and the electrical signal may be sent to integration component 103, integration component 105, and/or integration component 130 using one or more of the electrical circuits described above in at least FIG. 3 .

In some implementations, the electrical signal may be received by the optical integration component 101 through one or more of the electrical circuits described above in at least FIG. 3. The electrical signal may be converted into an optical signal by the optical integration component 101, and the optical signal may be transmitted through the optical fiber 110.

6 shows a cross-sectional view of a package 600 including an optical integration component. The package 600 includes an optical integration component 101, a packaging substrate 102, an integration component 103, a metallization portion 104, an integration component 105, an integration component 109, a connector socket 107, a passive component 111, an integration component 130, an integration component 132, an integration component 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one back power rail interconnect 203, and at least one back power rail interconnect 205.

Package 600 is similar to package 300 and/or package 400. However, some of the components of package 600 are positioned and/or coupled differently than some of the components in package 300 and/or package 400.

Package substrate 102 includes interconnect 122a and interconnect 122b. Interconnect 122a and interconnect 122b are configured as a heat sink in package substrate 102. Board 108 includes board interconnect 182a and board interconnect 182b. Heat sink 403 is coupled to board 108. Thermal interface material can be used to couple heat sink 403 to board 108. Heat sink 405 is coupled to board 108. Thermal interface material can be used to couple heat sink 405 to board 108. Heat generated by integrated component 103 and/or back power rail interconnect 203 can be dissipated by: solder interconnect from multiple solder interconnects 123, interconnect 122a, solder interconnect from multiple solder interconnects 183, board interconnect 182a, and heat sink 403. Heat generated by the integrated component 105 and/or the back power rail interconnect 205 may be dissipated through: solder interconnects from the plurality of solder interconnects 123 , interconnect 122 b , solder interconnects from the plurality of solder interconnects 183 , board interconnect 182 b , and heat sink 405 .

In some implementations, an optical signal may be received by optical integration component 101 via optical fiber 110. The optical signal may be converted into an electrical signal by optical integration component 101, and the electrical signal may be sent to integration component 103, integration component 105, and/or integration component 130 using one or more of the electrical circuits described above in at least FIG. 3 .

In some implementations, the electrical signal may be received by the optical integration component 101 through one or more of the electrical circuits described above in at least FIG. 3. The electrical signal may be converted into an optical signal by the optical integration component 101, and the optical signal may be transmitted through the optical fiber 110.

It should be noted that any of the packages may include additional components and/or other components. For example, an integrated element may be replaced with an integrated element stack. For example, integrated element 103 and/or integrated element 105 may each be replaced with an integrated element stack (e.g., similar to integrated element 130, integrated element 132, and integrated element 134). The integrated element stack may include a front-to-front integrated element, a front-to-back integrated element, and/or a back-to-back integrated element. In another example, a substrate and/or an interposer may be located between the package substrate 102 and the integrated element 103 and/or the integrated element 105.

It should be noted that any of the multiple solder interconnects described in the present disclosure may be implemented as multiple bump interconnects. Bump interconnects may include pillar interconnects and solder interconnects. In some implementations, multiple bump interconnects may include multiple microbump interconnects. Microbump interconnects may be similar to bump interconnects. However, microbump interconnects may have a smaller size than bump interconnects to accommodate finer interconnect pitches. For example, in some implementations, multiple solder interconnects 123 may be implemented as multiple microbump interconnects, and multiple solder interconnects 183 may be implemented as multiple bump interconnects. In some implementations, one or more bump interconnects may have a pitch (e.g., a minimum pitch) in the range of approximately 80 to 120 microns. In some implementations, one or more microbump interconnects can have a pitch (e.g., a minimum pitch) in the range of about 25 to 50 microns. Exemplary Optically Integrated Components

FIG7 shows an exemplary optical integration component 700. The optical integration component 700 may be the optical integration component 101 described in FIGS. 1 to 6. The optical integration component 700 includes a substrate 702 (e.g., a silicon substrate), an optical component 704, a waveguide 706, a waveguide 708, a waveguide 709, an oxide layer 710, a plurality of interconnects 730, and an optical fiber sleeve 720. The optical fiber 110 is coupled to the waveguide 706 and the optical fiber sleeve 720. An optical signal from the optical fiber 110 may travel through the waveguide 706, the waveguide 709, and the waveguide 708. The optical signal may be processed by the optical component 704, where the optical signal may be converted into an electrical signal. The electrical signal may be transmitted through the plurality of interconnects 730. The oxide layer 710 may surround the waveguide 709 and the waveguide 708. Waveguide 709 may include silicon (S) or silicon nitride. Waveguide 709 may extend through the thickness of substrate 702 like a through silicon via (TSV). Waveguide 708 may include silicon (S), germanium (Ge), or silicon nitride.

FIG8 shows an exemplary optical integration component 800. The optical integration component 800 may be the optical integration component 101 described in FIGS. 1 to 6. The optical integration component 800 includes a substrate 702 (e.g., a silicon substrate), an optical component 704, a waveguide 706, a plurality of interconnects 830, a plurality of interconnects 840, and an optical fiber sleeve 720. The optical fiber 110 is coupled to the waveguide 706 and the optical fiber sleeve 720. An optical signal from the optical fiber 110 may travel through the waveguide 706. The optical signal may be processed by the optical component 704, where the optical signal may be converted into an electrical signal. The electrical signal may be transmitted through the plurality of interconnects 830 and/or the plurality of interconnects 840.

Although not shown, the fiber ferrule 720 can be coupled to a carrier (eg, a silicon carrier), and the carrier is used to help couple the fiber ferrule 720 to the waveguide 706. In some implementations, there can be more than one optical fiber.

Different implementations may use different waveguide designs. In some implementations, the waveguide may include a silicon ridge waveguide, a silicon rib waveguide, a silicon groove waveguide, and/or a silicon nitride ridge waveguide. However, other implementations may use other waveguide designs. For example, some implementations may use germanium in combination with silicon.

The integrated component (e.g., 103) may include a die (e.g., a bare semiconductor die). The integrated component may include a power management integrated circuit (PMIC). The integrated component may include an application processor. The integrated component may include a data processor. The integrated component may include a radio frequency (RF) component, a passive component, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated component, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated component, a silicon (Si)-based integrated component, a silicon carbide (SiC)-based integrated component, a memory, a power management processor, and/or a combination thereof. The integrated element (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated element may include a transistor. The integrated element may be an example of an electrical component and/or an electrical element. In some implementations, the integrated element may be a small chip. In some implementations, the optical integrated element (e.g., 101) may be a small chip. Compared with other processes for manufacturing other types of integrated elements, a process that provides a better yield can be used to manufacture small chips, which can reduce the total cost of manufacturing small chips. Different small chips may have different sizes and/or shapes. Different small chips may be configured to provide different functions. Different small chips may have different interconnect densities (e.g., interconnects with different widths and/or spacings). In some implementations, several small chips may be used to perform the functions of one or more chips (e.g., one or more integrated elements). Thus, for example, a single integrated element may be divided into several small chips. As described above, using several chiplets that perform several functions can reduce the overall cost of a package relative to using a single chip to perform all functions of a package. In some implementations, one or more chiplets in the chiplets described in the present disclosure and/or one or more integrated elements in the integrated elements (e.g., 103) can be manufactured using the same technology node or two or more different technology nodes. For example, the integrated element can be manufactured using a first technology node, and the chiplets can be manufactured using a second technology node that is not as advanced as the first technology node. In such an example, the integrated element can include a component (e.g., interconnect, transistor) having a first minimum size, and the chiplet can include a component (e.g., interconnect, transistor) having a second minimum size, wherein the second minimum size is greater than the first minimum size. In some implementations, the integrated element of the package and another integrated element can be manufactured using the same technology node or different technology nodes. In some implementations, the dielet of the package and the other dielet may be fabricated using the same technology node or different technology nodes.

A technology node may refer to a specific manufacturing process and/or technology used to manufacture integrated components and/or chiplets. A technology node may specify the smallest possible size (e.g., minimum size) that can be manufactured (e.g., the size of a transistor, the width of a trace, the gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes that produce components with fine details (e.g., traces, transistors) are more expensive and may have higher yield losses than technology nodes that produce components with less fine details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses than less advanced technology nodes. When all functions of a package are implemented in a single integrated component, the entire integrated component is manufactured using the same technology node, even if some of the functions of the integrated component do not need to be manufactured using that particular technology node. Therefore, the integrated component is locked into one technology node. In order to optimize the cost of the package, some of the functions can be implemented in different integrated components and/or small chips, where different integrated components and/or small chips can be manufactured using different technology nodes to reduce the overall cost. For example, functions that require the use of the most advanced technology node can be implemented in an integrated component, while functions that can be implemented using a less advanced technology node can be implemented in another integrated component and/or one or more small chips. An example would be an integrated device configured to provide a computing application fabricated using a first technology node (e.g., the most advanced technology node) and at least one chiplet configured to provide other functionality fabricated using a second technology node, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node fabricates components having a minimum size that is greater than the minimum size of components fabricated using the first technology node. Examples of computing applications may include high performance computing and/or high performance processing, which may be achieved by fabricating and packaging as many transistors as possible in the integrated device, which is why the integrated device configured for computing applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes, as these chiplets may not require as many transistors to be fabricated in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and/or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all functions of the package.

Another advantage of separating the functionality into several integrated elements and/or chiplets is that it allows for improvements in the performance of the package without having to redesign each individual integrated element and/or chiplet. For example, if the configuration of the package uses a first integrated element and a first chiplet, it is possible to improve the performance of the package by changing the design of the first integrated element while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and/or differently configured first integrated element. This saves costs when manufacturing a package with an improved integrated element by not having to redesign the first chiplet. Exemplary sequence for manufacturing a package including an optical integrated element

In some implementations, manufacturing a package includes several processes. Figures 9A to 9D show an exemplary sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 9A to 9D can be used to provide or manufacture the package 300 of Figure 3. However, the process of Figures 9A to 9D can be used to manufacture any of the packages (e.g., 100, 200, 400, 500, 600) described in this disclosure.

It should be noted that the sequence of Figures 9A to 9D may combine one or more stages to simplify and/or illustrate the sequence for providing or manufacturing a package. In some implementations, the order of these processes may be changed or modified. In some implementations, one or more processes in the process may be replaced or substituted without departing from the spirit of the present disclosure.

As shown in FIG9A , stage 1 shows a state after providing a metallization portion 104 on a carrier 900. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may be formed on the carrier 900. The metallization portion 104 may be formed using a deposition process, a masking process, an exposure process, an etching process, a plating process, and/or a stripping process. The at least one dielectric layer may be formed and patterned using a deposition, lamination, exposure, development, and/or etching process. The metallization interconnects may be formed using a plating process and/or a patterning process.

Stage 2 shows a state after a plurality of pillar interconnects 160 are formed over and coupled to the metallization portion 104. The plurality of pillar interconnects 160 are coupled to the plurality of metallization interconnects 142. The plurality of pillar interconnects 160 may be formed using a plating process.

Stage 3 shows a state after a plurality of integrated components and/or at least one passive device are coupled to the surface of metallized portion 104. For example, integrated component 103 is coupled to the surface of metallized portion 104 via a plurality of solder interconnects 223. For example, a front side of integrated component 103 is coupled to the surface of metallized portion 104. Integrated component 103 may include back power rail interconnect 203. Integrated component 105 is coupled to the surface of metallized portion 104 via a plurality of solder interconnects 225. For example, a front side of integrated component 105 is coupled to the surface of metallized portion 104. Integrated component 105 may include back power rail interconnect 205. Integrated component 109 is coupled to the surface of metallized portion 104 via a plurality of solder interconnects 190. Passive component 111 is coupled to the surface of metallized portion 104 via a plurality of solder interconnects 112. One or more solder reflow processes may be used to couple integrated components and/or passive devices to the metallization 104 .

As shown in FIG9B , stage 4 shows a state after encapsulation layer 106 is formed on and coupled to metallization portion 104. Encapsulation layer 106 may include a molded article, a resin, and/or an epoxy resin. Encapsulation layer 106 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. Encapsulation may encapsulate (e.g., partially encapsulate) integrated element 103/back power rail interconnect 203, integrated element 105/back power rail interconnect 205, integrated element 109, passive element 111, and multiple pillar interconnects 160.

Phase 5 shows the state after the carrier 900 has been decoupled from the metallization part 104.

Stage 6 shows a state after the packaging substrate 102 is coupled to the back power rail interconnects (e.g., 203, 205), the plurality of pillar interconnects 160 of the integrated element (e.g., 103, 105) through the plurality of solder interconnects 123. A solder reflow process can be used to couple the power rail interconnects and the plurality of pillar interconnects 160 through the plurality of solder interconnects 123. The packaging substrate 102 can be coupled to the back side of the integrated element 103 and the back side of the integrated element 105. The packaging substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. In some implementations, the packaging substrate 102 can include the optical integration element 101, and/or the optical integration element 101 can be coupled to the packaging substrate 102. As shown and described in Figures 1 and 2, in some implementations, the optical integration element 101 can be a part of the packaging substrate 102. The optical integration component 101 may be located in a cavity of the package substrate 102. The optical integration component 101 may be coupled to the package substrate 102 by an adhesive.

Stage 7 shows a state after providing an underfill 125 between the package substrate 102 and the encapsulation layer 106. The underfill 125 may be formed such that the underfill 125 laterally surrounds the plurality of solder interconnects 123. The underfill 125 may be coupled to and contact the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated component 103, and/or the integrated component 105.

9C , stage 8 shows a state after one or more integrated components are coupled to the surface of metallized portion 104. For example, an integrated component stack can be coupled to metallized portion 104. In one example, an integrated component stack including integrated component 130, integrated component 132, and integrated component 134 can be coupled to metallized portion 104 through a solder reflow process.

Stage 9 shows the state after the package substrate 102 is coupled to the board 108 through the plurality of solder interconnects 183. The package substrate 102 may be coupled to the board 108 using a solder reflow process.

9D, stage 10 shows a state after optical integration component 101 is coupled to metallization portion 104 via multiple solder interconnects 310. Optical integration component 301 is coupled to board 108. Optical integration component 301 can be similar to optical integration component 101. Optical integration component 301 can be coupled to board 108 via multiple solder interconnects. Optical fiber 110 can be coupled to optical integration component 101 and optical integration component 301.

Stage 10 also shows a state after connector socket 107 is coupled to metallization 104 via multiple solder interconnects 170 and connector socket 113 is coupled to board 108 via multiple solder interconnects 114. A solder reflow process may be used to couple connector socket 107 to metallization 104 and connector socket 113 to board 108. Connector socket 107 may be coupled to connector socket 113 via one or more wires. Exemplary Flowchart of a Method for Manufacturing a Package Including an Optically Integrated Component

In some implementations, manufacturing a package includes several processes. FIG. 10 shows an exemplary flow chart of a method 1000 for providing or manufacturing a package. In some implementations, the method 1000 of FIG. 10 can be used to provide or manufacture at least the packages of FIG. 1 to FIG. 6.

It should be noted that the method 1000 of Figure 10 may combine one or more processes to simplify and/or illustrate a method for providing or manufacturing a package. In some implementations, the order of these processes may be changed or modified.

The method provides (at 1005) a metallization and a plurality of pillar interconnects. The metallization may be provided on a carrier. In some implementations, providing the metallization and the plurality of pillar interconnects includes fabricating the metallization and the plurality of pillar interconnects. Stages 1 and 2 of FIG. 9A illustrate and describe an example of providing a metallization 104 and a plurality of pillar interconnects 160. Stage 1 of FIG. 9A illustrates and describes an example of providing a metallization. The metallization 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization 104 may be formed on a carrier 900. The at least one dielectric layer may be formed and patterned using deposition, lamination, exposure, development and/or etching processes. The metallization interconnects may be formed using a plating process and/or a patterning process.

9A shows and describes an example of a plurality of pillar interconnects 160 formed over and coupled to the metallization portion 104. The plurality of pillar interconnects 160 are coupled to the plurality of metallization interconnects 142. The plurality of pillar interconnects 160 may be formed using a plating process.

The method couples (at 1010) a plurality of integrated components and/or at least one passive device to the metallization portion. Stage 3 of FIG. 9A shows and describes an example of a plurality of integrated components and/or at least one passive component coupled to the surface of the metallization portion 104. For example, the integrated component 103 is coupled to the surface of the metallization portion 104 via a plurality of solder interconnects 223. The integrated component 105 is coupled to the surface of the metallization portion 104 via a plurality of solder interconnects 225. The integrated component 109 is coupled to the surface of the metallization portion 104 via a plurality of solder interconnects 190. The passive component 111 is coupled to the surface of the metallization portion 104 via a plurality of solder interconnects 112. One or more solder reflow processes may be used to couple the plurality of integrated components and/or passive devices to the metallization portion 104.

The method forms (at 1015) an encapsulation layer. The encapsulation layer can at least partially encapsulate multiple pillar interconnects, integrated components and/or passive components. Stage 4 of Figure 9B shows and describes an example of an encapsulation layer 106 formed over and coupled to the metallization portion 104. The encapsulation layer 106 can include a molding, a resin and/or an epoxy resin. The encapsulation layer 106 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation can encapsulate the integrated component 103/back power rail interconnect 203, the integrated component 105/back power rail interconnect 205, the integrated component 109, the passive component 111, and multiple pillar interconnects 160.

The method may also remove (at 1015) the carrier coupled to the metallized portion. An example of a carrier 900 decoupled from the metallized portion 104 is shown and described at stage 5 of FIG. 9B.

The method can couple (at 1020) the package substrate to the plurality of pillar interconnects via a plurality of solder interconnects. Stage 6 of FIG. 9B shows and describes an example of a package substrate 102 coupled to a power rail interconnect (e.g., 203, 205) of an integrated component (e.g., 103, 105), a plurality of pillar interconnects 160 via a plurality of solder interconnects 123. A solder reflow process can be used to couple the power rail interconnects and the plurality of pillar interconnects 160 via the plurality of solder interconnects 123. The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122.

In some implementations, the package substrate 102 may include the optical integration component 101, and/or the optical integration component 101 may be coupled to the package substrate 102. As shown and described in Figures 1 and 2, in some implementations, the optical integration component 101 may be a part of the package substrate 102. The optical integration component 101 may be located in a cavity of the package substrate 102. The optical integration component 101 may be coupled to the package substrate 102 via an adhesive.

In some implementations, once the package substrate 102 is coupled to the plurality of pillar interconnects via the plurality of solder interconnects, an underfill 125 may be provided between the package substrate 102 and the encapsulation layer 106. An example of providing the underfill is shown and described in stage 7 of FIG. 9B. The underfill 125 may be formed such that the underfill 125 laterally surrounds the plurality of solder interconnects 123. The underfill 125 may be coupled to and contact the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated component 103, and/or the integrated component 105.

The method can also couple (at 1020) the integrated element and/or the passive device to the package. For example, the method can couple the integrated element and/or the passive device to the surface of the metallized portion. Stage 8 of Figure 9C shows and describes an example of one or more integrated elements coupled to the surface of the metallized portion 104. For example, an integrated element stack can be coupled to the metallized portion 104. In one example, an integrated element stack including integrated element 130, integrated element 132, and integrated element 134 can be coupled to the metallized portion 104 via a solder reflow process.

The method may couple (at 1025) the package substrate to the board via a plurality of solder interconnects. Stage 9 of FIG. 9C shows and describes an example of a package substrate 102 coupled to the board 108 via a plurality of solder interconnects 183. A solder reflow process may be used to couple the package substrate 102 to the board 108 via the plurality of solder interconnects 183.

The method may couple (at 1030) the connector receptacle to the package and the board. The method may also couple (at 1030) an optical integration component to the package and another optical integration component to the board. Stage 10 of FIG. 9D illustrates and describes an example of an optical integration component 101 coupled to a metallization 104 via a plurality of solder interconnects 310. Optical integration component 301 is coupled to board 108. Optical integration component 301 may be similar to optical integration component 101. Optical integration component 301 may be coupled to board 108 via a plurality of solder interconnects. Fiber 110 may be coupled to optical integration component 101 and optical integration component 301.

Stage 10 of FIG. 9D also shows and describes an example of a connector socket 107 coupled to metallized portion 104 via multiple solder interconnects 170, and a connector socket 113 coupled to board 108 via multiple solder interconnects 114. A solder reflow process may be used to couple connector socket 107 to metallized portion 104 and connector socket 113 to board 108. Connector socket 107 may be coupled to connector socket 113 via one or more wires. Exemplary Electronic Device

FIG. 11 shows various electronic devices that may be integrated with any of the following: the aforementioned components, integrated components, integrated circuit (IC) packages, integrated circuit (IC) components, semiconductor components, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or single chip systems (SoC). For example, a mobile phone device 1102, a laptop device 1104, a fixed location terminal device 1106, a wearable device 1108, or a motor vehicle 1110 may include a component 1100 as described herein. Component 1100 may be, for example, any of the components and/or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108 and the vehicle 1110 shown in FIG11 are exemplary only. Other electronic devices may also be characterized by element 1100, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT), and the like. The invention may include an IoT (Internet of Things) device, a server, a router, an electronic device implemented in a motor vehicle (e.g., an autonomous vehicle), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions shown in Figures 1 to 8, Figures 9A to 9D, and/or Figures 10 to 11 may be rearranged and/or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional components, components, processes, and/or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1 to 8, Figures 9A to 9D, and/or Figures 10 to 11 and their corresponding descriptions in the present disclosure are not limited to die and/or ICs. In some implementations, Figures 1 to 8, Figures 9A to 9D, and/or Figures 10 to 11 and their corresponding descriptions may be used to manufacture, create, provide, and/or produce components and/or integrate components. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and/or an interposer.

It should be noted that the various figures in the present disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, elements, packages, integrated components, integrated circuits and/or transistors. In some cases, the figures may not be to scale. In some cases, for clarity, not all components and/or parts are shown. In some cases, the positions, locations, sizes and/or shapes of the various parts and/or components in the figures may be exemplary. In some implementations, the various components and/or parts in the figures may be optional.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct coupling or an indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. The term "electrically coupled" can mean that two objects are coupled together directly or indirectly so that electrical current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current running between the two objects. The use of the terms "first," "second," "third," and "fourth" (and/or anything higher than the fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially encapsulate or completely encapsulate another object. A first component "located in" a second component may mean that the first component is "partially located" in the second component or "completely located" in the second component. A first component "embedded" in a second component may mean that the first component is "partially embedded" in the second component or "completely embedded" in the second component. The terms "top" and "bottom" are arbitrary. A component located on top may be located above a component that is located on the bottom. A top component may be considered a bottom component and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It should also be noted that the term "above" as used in the present application in the context of a component located above another component may be used to mean a component on and/or in (e.g., on the surface of or embedded in) another component. Thus, for example, a first component being above a second component may mean: (1) the first component being above the second component, but not directly contacting the second component, (2) the first component being on (e.g., on a surface of) the second component, and/or (3) the first component being in (e.g., embedded in) the second component. Values of about X to XX may mean values between X and XX, inclusive. Values between X and XX may be discrete or continuous. The term "about 'value X'" or "approximate value X" as used in the present disclosure means within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components may include all possible components or only some components from all possible components. For example, if a device includes ten components, use of the term "plurality of components" may refer to all ten components or only some of the ten components.

In some implementations, an interconnect is an element or component in a component or package that allows or facilitates electrical connection between two points, components, and/or components. In some implementations, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and/or under bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect is a conductive material that can be configured to provide a path for current (e.g., data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process is used to form the interconnects. For example, a sputtering process, a spray coating process, and/or an electroplating process or an electroless plating process may be used to form the interconnects.

In addition, it should be noted that various disclosures contained herein may be described as processes, which are depicted as flow charts, process diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as a sequential process, many of these operations may be performed in parallel or concurrently. In addition, the order of these operations may be rearranged. A process terminates when its operations are completed.

Hereinafter, further examples are described to facilitate understanding of the present invention.

Aspect 1: A package comprises: a packaging substrate; a first integrated element coupled to the packaging substrate via a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated element; a plurality of post interconnects located in the encapsulation layer; a metallized portion coupled to the plurality of post interconnects; a second integrated element coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated element coupled to the packaging substrate; and an optical fiber coupled to the optical integrated element.

Aspect 2: The package according to aspect 1, wherein a front surface of the first integrated component is oriented in a direction toward the package substrate.

Aspect 3: A package according to aspects 1 to 2, wherein the second integrated component is configured to be electrically coupled to the optical integrated component via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, pillar interconnects from the plurality of pillar interconnects, and solder interconnects from the first plurality of solder interconnects.

Aspect 4: The package of aspects 1 to 3, wherein the first integrated component is configured to be electrically coupled to the optical integrated component via an electrical path, the electrical path comprising solder interconnects from the first plurality of solder interconnects.

Aspect 5: A package according to aspects 1 to 4, wherein the second integrated element is configured to be electrically coupled to the first integrated element via an electrical path, the electrical path including a solder interconnect from the second plurality of solder interconnects, a metallized interconnect from the metallized portion, a pillar interconnect from the plurality of pillar interconnects and a solder interconnect from the first plurality of solder interconnects, an interconnect from the package substrate, and another solder interconnect from the first plurality of solder interconnects.

Aspect 6: A package according to aspects 1 to 5, wherein the second integrated component is configured to be electrically coupled to the first integrated component via an electrical path, the electrical path including a solder interconnect from the second plurality of solder interconnects, a metallized interconnect from the metallized portion, a post interconnect from the plurality of post interconnects and a solder interconnect from the first plurality of solder interconnects, the optical integrated component, and another solder interconnect from the first plurality of solder interconnects.

Aspect 7: The package according to aspects 1 to 6, further comprising: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

Aspect 8: The package according to aspects 1 to 7, wherein the optical integration component comprises a waveguide and a circuit for processing optical signals and/or electrical signals.

Aspect 9: The package of aspects 1 to 8, wherein the optical fiber extends through the package substrate.

Aspect 10: The package according to aspects 1 to 9, wherein the second integrated component comprises a memory.

Aspect 11: A package comprises: a metallized portion; a first integrated element coupled to the metallized portion via a first plurality of solder interconnects, wherein a front face of the first integrated element is oriented in a direction toward the metallized portion; an encapsulation layer encapsulating the first integrated element; a plurality of post interconnects in the encapsulation layer; a second integrated element coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated element coupled to the metallized portion via a third plurality of solder interconnects; an optical fiber coupled to the optical integrated element; and a packaging substrate coupled to the plurality of post interconnects via a fourth plurality of solder interconnects.

Aspect 12: The package of aspect 11, wherein the second integrated component is coupled to the optical integrated component via an electrical path, the electrical path comprising solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the third plurality of solder interconnects.

Aspect 13: A package according to aspects 11 to 12, wherein the first integrated component is coupled to the optical integrated component via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the third plurality of solder interconnects.

Aspect 14: A package according to aspects 11 to 13, wherein the second integrated component is coupled to the first integrated component via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the first plurality of solder interconnects.

Aspect 15: The package according to aspects 11 to 14, further comprising: a passive device coupled to the metallized portion.

Aspect 16: The package of aspect 15, wherein the passive device is at least partially encapsulated by the encapsulation layer.

Aspect 17: The package according to aspects 11 to 16, further comprising: a plurality of power rail interconnections located in the encapsulation layer.

Aspect 18: The package of aspect 17, wherein the plurality of power rails are interconnected between the back side of the first integrated component and the package substrate.

Aspect 19: The package according to aspects 11 to 18, wherein the second integrated component comprises a memory.

Aspect 20: The package of aspects 11 to 19, further comprising: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

Aspect 21: A package according to aspects 11 to 20, wherein the package is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet, a computer, a wearable device, a laptop, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

Aspect 22: A package according to aspects 1 to 10, wherein the package is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet, a computer, a wearable device, a laptop, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

Without departing from the present disclosure, the various features of the present disclosure described herein can be implemented in different systems. It should be noted that the above aspects of the present disclosure are merely examples and are not to be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the various aspects. Therefore, the teachings herein can be easily applied to other types of devices, and many changes, modifications, and variations will be apparent to those having ordinary knowledge in the art.

100: Package 101: Optical integrated component 102: Package substrate 103, 105, 109, 130, 132, 134: Integrated component 104: Metallized part 106: Encapsulation layer 107, 113: Connector socket 108: Board 110: Fiber optics 111: Passive component 112, 114, 123, 131, 133, 135, 170, 183, 190: Solder interconnects 120, 140, 180: Dielectric layer 122: Interconnects 125: Bottom filler 142: Metallized interconnects 151, 153, 155, 157, 159: Circuit paths 160: Pillar interconnects 182: Board interconnects 200: Package 203, 205: Backside power rail interconnects 223, 225: Solder interconnects 255, 257, 259: Circuit paths 300: Package 122a, 122b: Interconnects 182a, 182b: Board interconnects 301: Optically integrated components 310: Solder interconnects 353, 355, 357: Circuit paths 403, 405: Heat sinks 500, 600: Package 700: Optically integrated components 702: Substrate 704: Optical components 706, 708, 709: Waveguides 710: Oxide layer 720: Fiber ferrule 730: Interconnects 800: optically integrated device 830, 840: interconnection 900: carrier 1000: method 1005, 1010, 1015, 1020, 1025, 1030: process 1100: component 1102: mobile phone device 1104: laptop device 1106: fixed position terminal device 1108: wearable device 1110: motor vehicle

Various features, properties and advantages will become apparent from the following detailed description of the embodiments when taken in conjunction with the drawings, in which like reference numerals designate corresponding elements throughout.

FIG. 1 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG. 2 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG3 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG. 4 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG5 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG6 illustrates a cross-sectional view of an exemplary package including an optically integrated component.

FIG. 7 shows a cross-sectional view of an exemplary optical integration component.

FIG8 shows a cross-sectional view of an exemplary optical integration component.

9A-9D illustrate an exemplary sequence for fabricating a package including an optically integrated component.

FIG. 10 shows an exemplary flow chart of a method for manufacturing a package including an optically integrated component.

FIG. 11 illustrates various electronic devices that may incorporate the dies, integrated components, integrated passive devices (IPDs), passive assemblies, packages, and/or component packages described herein.

100:Packaging parts

101:Optical integrated components

102:Packaging substrate

103, 105, 109, 130, 132, 134: integrated components

104:Metalized part

106: Encapsulation layer

107, 113: Connector socket

108: Board

110: Optical fiber

111: Passive components

112, 114, 123, 131, 133, 135, 170, 183, 190: solder interconnection

120, 140, 180: Dielectric layer

122: Interconnection

125: Bottom filler

142:Metalized interconnection

151, 153, 155, 157, 159: Circuit path

160: Column interconnection

182: Board interconnection

Claims (20)

A package includes: a package substrate; a first integrated component coupled to the package substrate by a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated component; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated component coupled to the metallization portion by a second plurality of solder interconnects; an optical integrated component coupled to the package substrate; and an optical fiber coupled to the optical integrated component. A package as described in claim 1, wherein a front surface of the first integrated component is oriented in a direction toward the package substrate. A package as described in claim 1, wherein the second integrated element is configured to be electrically coupled to the optical integrated element via an electrical circuit, the electrical circuit including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, column interconnects from the plurality of column interconnects, and solder interconnects from the first plurality of solder interconnects. The package of claim 1, wherein the first integrated component is configured to be electrically coupled to the optical integrated component via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects. A package as described in claim 1, wherein the second integrated element is configured to be electrically coupled to the first integrated element via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, column interconnects from the plurality of column interconnects and solder interconnects from the first plurality of solder interconnects, interconnects from the package substrate, and another solder interconnect from the first plurality of solder interconnects. A package as described in claim 1, wherein the second integrated element is configured to be electrically coupled to the first integrated element via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, post interconnects from the plurality of post interconnects and solder interconnects from the first plurality of solder interconnects, the optical integrated element, and another solder interconnect from the first plurality of solder interconnects. The package as described in claim 1 further includes: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power. A package as described in claim 1, wherein the optical integration component includes a waveguide and a circuit for processing optical signals and/or electrical signals. A package as described in claim 1, wherein the optical fiber extends through the packaging substrate. A package as described in claim 1, wherein the second integrated component includes a memory. A package includes: a metallized portion; a first integrated element coupled to the metallized portion by a first plurality of solder interconnects, wherein a front face of the first integrated element is oriented in a direction toward the metallized portion; an encapsulation layer at least partially encapsulating the first integrated element; a plurality of post interconnects located in the encapsulation layer; a second integrated element coupled to the metallized portion by a second plurality of solder interconnects; an optical integrated element coupled to the metallized portion by a third plurality of solder interconnects; an optical fiber coupled to the optical integrated element; and a package substrate coupled to the plurality of post interconnects by a fourth plurality of solder interconnects. A package as described in claim 11, wherein the second integrated element is coupled to the optical integrated element via an electrical circuit, the electrical circuit including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the third plurality of solder interconnects. A package as described in claim 11, wherein the first integrated element is coupled to the optical integrated element via an electrical circuit, the electrical circuit including solder interconnects from the first plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the third plurality of solder interconnects. A package as described in claim 11, wherein the second integrated element is coupled to the first integrated element via an electrical circuit, the electrical circuit including solder interconnects from the second plurality of solder interconnects, metallized interconnects from the metallized portion, and solder interconnects from the first plurality of solder interconnects. The package as described in claim 11 further includes: a passive element coupled to the metallized portion. A package as described in claim 15, wherein the passive element is at least partially encapsulated by the encapsulation layer. The package as described in claim 11 further includes: multiple power rail interconnections located in the packaging layer. A package as described in claim 17, wherein the multiple power rails are interconnected between the back side of the first integrated component and the packaging substrate. A package as described in claim 11, wherein the second integrated component includes a memory. The package of claim 11, further comprising: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

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