TW202439645A - Optoelectronic semiconductor device - Google Patents

Abstract

An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes a stack of semiconductor layers, a first electrode, a first conductive structure, and a second conductive structure. The stack of semiconductor layers includes an upper surface, a first sidewall, and a second sidewall. The first electrode covers the upper surface of the stack of semiconductor layers. The first conductive structure is physically separated from the first electrode and covers the first sidewall. The second conductive structure is physically separated from the first electrode and covers the second sidewall. The first sidewall has a first slope and the second sidewall has a second slope that is different from the first slope.

Description

Optoelectronic semiconductor components

The present disclosure relates to a photoelectric semiconductor device, and more particularly to a light emitting diode device.

Semiconductor components have a wide range of uses, and the development and research of related materials is also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor components such as light-emitting chips (e.g., light-emitting diodes or laser diodes), light-absorbing chips (photodetectors or solar cells) or non-light-emitting chips (e.g., power components of switches or rectifiers), and can be used in lighting, medical, display, communication, sensing, power supply systems and other fields.

With the advancement of technology, the size of optoelectronic semiconductor components has gradually developed towards miniaturization. In recent years, due to the breakthrough in the size of light-emitting diode (LED) manufacturing, micro-LED displays, which are made by arranging LEDs in arrays, have gradually gained attention in the market. Compared with organic light-emitting diode (OLED) displays, micro-LED displays are more power-saving, have better reliability, longer service life, better contrast performance, and can be visible in sunlight. With the development of technology, there are still many technical research and development needs for optoelectronic semiconductor components. Although existing optoelectronic semiconductor devices have generally met various requirements, they are not satisfactory in all aspects and still need further improvement.

An embodiment of the present disclosure provides a photoelectric semiconductor element. The above-mentioned photoelectric semiconductor element includes a semiconductor stack, a first electrode, a first conductive structure and a second conductive structure. The semiconductor stack includes an upper surface, a first sidewall and a second sidewall. The first electrode covers the upper surface of the semiconductor stack. The first conductive structure is physically separated from the first electrode and covers the first sidewall. The second conductive structure is physically separated from the first electrode and covers the second sidewall. The first sidewall has a first slope, and the second sidewall has a second slope different from the first slope.

The present disclosure is described more fully below with reference to the drawings of the embodiments of the present disclosure. However, the present disclosure may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the drawings represent the same or similar elements.

The disclosed embodiment provides a photoelectric semiconductor device. The photoelectric semiconductor device includes a semiconductor stack located on a substrate, an insulating structure covering the sidewall of the semiconductor stack, a first electrode and a second electrode located on the semiconductor stack and separated from each other, and a conductive structure physically separated from the first electrode and the second electrode. The conductive structure located on the sidewall of the semiconductor stack has a first region and a second region separated from each other. When the first electrode and the second electrode of the optoelectronic semiconductor element are respectively assembled and electrically connected to the external circuit, the first region and the second region of the conductive structure can avoid the problem of short circuit of the optoelectronic semiconductor element caused by the residues left on the side wall of the semiconductor stack during the process of forming the first electrode, the second electrode and the conductive structure.

FIG. 1 is a schematic top view of an optoelectronic semiconductor device 500a according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view of an optoelectronic semiconductor device 500a according to some embodiments of the present disclosure taken along the tangent line A-A' in FIG. 1. In some embodiments, the length of the optoelectronic semiconductor device 500a is not greater than 150 microns, preferably in the range of 10 microns to 150 microns, or 10 microns to 60 microns, or 60 microns to 150 microns, and the width is not greater than 100 microns, preferably in the range of 5 microns to 100 microns, or 5 microns to 30 microns, or 30 microns to 75 microns.

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor device 500a includes a substrate 204, a semiconductor stack 208, an insulating structure 236, a first electrode 246, a second electrode 248, and a first conductive structure 242.

As shown in FIGS. 1 and 2 , the substrate 204 has a top surface 201 and a bottom surface 203 facing each other, and an edge 205. In some embodiments, the substrate 204 may include a growth substrate or a bonding substrate. The material of the substrate 204 may include sapphire, gallium arsenide (GaAs), silicon (Si), gallium nitride (GaN), indium phosphide (InP), glass, ceramic material or metal. As shown in FIG. 2 , the optoelectronic semiconductor element 500a selectively includes a bonding layer 206 between the substrate 204 and the semiconductor stack 208. The material of the bonding layer 206 includes benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO ₂ ), silicon nitride (SiNx), titanium dioxide (TiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or a combination thereof.

As shown in FIG. 2 , the semiconductor stack 208 is an epitaxial structure layer, which includes a first-type semiconductor layer 208a, a second-type semiconductor layer 208c, and an active layer 208b located between the first-type semiconductor layer 208a and the second-type semiconductor layer 208c. In some embodiments, the first-type semiconductor layer 208a and the second-type semiconductor layer 208c have opposite conductivity types. For example, the first-type semiconductor layer 208a is an n-type semiconductor layer, and the second-type semiconductor layer 208c is a p-type semiconductor layer. Alternatively, the first-type semiconductor layer 208a can be a p-type semiconductor layer, and the second-type semiconductor layer 208c can be an n-type semiconductor layer. The materials of the first type semiconductor layer 208a, the second type semiconductor layer 208c and the active layer 208b may include gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), or aluminum indium gallium phosphide (AlGaInP).

In FIG. 2 , the semiconductor stack 208 includes a first high plateau 210, a second high plateau 212, a first flat region 216, a second flat region 214, and a third flat region 218. The first flat region 216 is located between the first high plateau 210 and the second high plateau 212, the first high plateau 210 is located between the first flat region 216 and the second flat region 214, and the second high plateau 212 is located between the first flat region 216 and the third flat region 218. Specifically, the first high plateau 210 and the second high plateau 212 include a first type semiconductor layer 208a, a second type semiconductor layer 208c, and an active layer 208b; the first flat region 216, the second flat region 214, and the third flat region 218 include only the first type semiconductor layer 208a.

As shown in FIG. 2 , the semiconductor stack 208 includes a plurality of high plateaus and flat areas, and thus includes a plurality of sidewalls 220 and 224. Specifically, the sidewall 220 may include a sidewall 220a of the second flat area 214 and a sidewall 220b of the third flat area 218, and the sidewall 224 may include sidewalls 224a1 and 224a2 of the first high plateau area 210 and sidewalls 224b1 and 224b2 of the second high plateau area 212. As shown in FIGS. 1 and 2 , the sidewalls 220 and 224 are not aligned with each other. The sidewall 220 is closer to the edge 205 of the substrate 204 than the sidewall 224, and the angle θ between the sidewall 220 and the top surface 201 of the substrate 204 may be between 60 degrees and 90 degrees. As shown in FIG. 2 , the sidewall 220 may have a first slope, and the sidewall 224 may have a second slope different from the first slope.

As shown in FIGS. 1 and 2 , the insulating structure 236 covers the semiconductor stack 208 and extends to cover a portion of the top surface 201 of the substrate 204. The insulating structure 236 may cover the top surface and sidewalls 220a of the second flat region 214, the top surface and sidewalls 224a1, 224a2 of the first high plateau region 210, a portion of the top surface of the first flat region 216, the sidewalls 224b1, 224b2 and a portion of the top surface of the second high plateau region 212, and the top surface and sidewalls 220b of the third flat region 218. In some embodiments, the insulating structure 236 has a first insulating portion 236a covering the sidewall 220 and a second insulating portion 236b covering the sidewall 224. The first insulating portion 236a and the second insulating portion 236b are connected to each other. The insulating structure 236 has openings on the top surfaces of the first flat area 216 and the second high plateau area 212, respectively, to expose a portion of the first type semiconductor layer 208a and a portion of the second type semiconductor layer 208c, respectively. In some embodiments, the insulating structure 236 can be composed of two or more materials with different refractive indices stacked. For example, the material of the insulating structure 236 may include silicon dioxide (SiO ₂ ), titanium dioxide (TiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), silicon nitride (SiN _x ), or a stacked combination thereof. The insulating structure 236 may include a Bragg reflector (DBR).

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor device 500a includes a first contact layer 230 and a second contact layer 234 located on the semiconductor stack 208. The first contact layer 230 and the second contact layer 234 are respectively located at the openings of the insulating structure 236 on the first flat area 216 and the second high plateau area 212 and cover a portion of the top surface of the first flat area 216 and the second high plateau area 212, and are respectively electrically connected to the first type semiconductor layer 208a and the second type semiconductor layer 208c. The width of the first contact layer 230 may be smaller than the width of the first flat area 216, and the width of the second contact layer 234 may be smaller than the width of the second high plateau area 212. The insulating structure 236 is separated from the first contact layer 230 and the second contact layer 234 and has no direct contact therewith.

In some embodiments, the first contact layer 230 and the second contact layer 234 may be a single layer or multiple layers. The first contact layer 230 and the second contact layer 234 may include a metal, an alloy, or a metal oxide. The metal first contact layer and the second contact layer include gold (Au), copper (Cr), titanium (Ti), aluminum (Al), nickel (Ni), platinum (Pt), silver (Ag), zinc (Zn), germanium (Ge), and benzium (Be). The alloy is a combination of the above metals. The metal oxide includes indium tin oxide (ITO), indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium gallium oxide. In some embodiments, the first contact layer 230 and the second contact layer 234 may be selectively formed successively, and both may be formed of the same or different materials.

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor device 500a includes a first electrode 246 and a second electrode 248 that are physically separated from each other and are respectively located on the semiconductor stack 208 and away from the substrate 204. The first electrode 246 conformably covers the first flat region 216 and the first contact layer 230, and extends to cover a portion of the insulating structure 236 located on the first high plateau region 210 and the second high plateau region 212. The second electrode 248 conformably covers the second high plateau region 212 and the second contact layer 234, and extends to cover a portion of the insulating structure 236 on the second high plateau region 212. The first electrode 246 may have a first thickness T1, and the second electrode 248 may have a second thickness T2, and the first thickness T1 and the second thickness T2 may be the same or different. For example, the first electrode 246 located in the first high plateau region 210 may have a first thickness T1 along the normal direction of the substrate 204, and the second electrode 248 located in the second high plateau region 212 may also have a second thickness T2 along the normal direction of the substrate 204, and the first thickness T1 is equal to the second thickness T2. In the top view of FIG. 1, the first electrode 246 and the second electrode 248 are separated by a distance W2. In some embodiments, the first electrode 246 is electrically connected to the first type semiconductor layer 208 a of the semiconductor stack 208 through the first contact layer 230 , and the second electrode 248 is electrically connected to the second type semiconductor layer 208 c of the semiconductor stack 208 through the second contact layer 234 .

In some embodiments, the first electrode 246 and the second electrode 248 may be a single layer or multiple layers. The first electrode 246 and the second electrode 248 may include a metal, an alloy, or a metal oxide. In some embodiments, the first electrode 246 and the second electrode 248 are transparent to the light emitted by the active layer 208b, so that the light can be emitted from the first electrode 246 and the second electrode 248 in the direction 250 outside the optoelectronic semiconductor device 500a. The first electrode 246 and the second electrode 248 may have the same or different materials.

As shown in FIGS. 1 and 2 , the optoelectronic semiconductor device 500a includes a first conductive structure 242 and a second conductive structure 244 that are physically separated from a first electrode 246 and a second electrode 248. The first conductive structure 242 covers the first insulating portion 236a of the insulating structure 236, and the second conductive structure 244 covers the second insulating portion 236b of the insulating structure 236. In some embodiments, from the top view of FIG. 1 , the first conductive structure 242 has a first region 242a and a second region 242b that are physically separated from each other. Specifically, the first region 242a covers the side wall 220a of the second flat region 214, and the second region 242b covers the side wall 220b of the third flat region 218. In some embodiments, as shown in the top view of FIG. 1 , the second conductive structure 244 has a third region 244a and a fourth region 244b separated from each other. Specifically, the third region 244a covers the sidewall 224a1 of the first mesa region 210 , and the fourth region 244b covers the sidewall 224b1 of the second mesa region 212 .

As shown in FIG. 1 , the third region 244a and the fourth region 244b of the second conductive structure 244 are spaced apart by a distance W1, and the first region 242a and the second region 242b of the first conductive structure 242 are spaced apart by a distance W1′, and the distance W1 and the distance W1′ may be equal to or different from each other. In some embodiments, the distance W1 and the distance W1′ are smaller than the distance W2 between the first electrode 246 and the second electrode 248. As shown in FIG. 2 , the first region 242a of the first conductive structure 242 may have a third thickness T3, for example, the first region 242a has a third thickness T3 along the normal direction of the sidewall 220a, and the second region 242b has a fourth thickness T4 along the normal direction of the sidewall 220b, and the third thickness T3 and the fourth thickness T4 may be the same or different. Similarly, the third region 244a of the second conductive structure 244 has a fifth thickness T5 along the normal direction of the sidewall 224a1, and the fourth region 244b of the second conductive structure 244 has a sixth thickness T6 along the normal direction of the sidewall 224b1. The fifth thickness T5 and the sixth thickness T6 may be the same or different. In some embodiments, the thickness of the first conductive structure 242 (the third thickness T3 or/and the fourth thickness T4 or/and the fifth thickness T5 or/and the sixth thickness T6) is less than the thickness of the first electrode or the second electrode. For example, the thickness of the first conductive structure 242 is 0.3 to 0.8 times the thickness of the first electrode or the second electrode (e.g., the third thickness T3/first thickness T1, the fourth thickness T4/first thickness T1, the fifth thickness T5/first thickness T1, the sixth thickness T6/first thickness T1, the third thickness T3/second thickness T2, the fourth thickness T4/second thickness T2, the fifth thickness T5/second thickness T2, the sixth thickness T6/second thickness T2). In some embodiments, the first electrode 246, the second electrode 248, the first conductive structure 242, and the second conductive structure 244 have the same material. In one embodiment, the thickness of the first conductive structure 242 may be gradually changed, for example, the third thickness T3, the fourth thickness T4, the fifth thickness T5, or/and the sixth thickness T6 are gradually increased or decreased from the first electrode 246 to the substrate 204. When the thickness of the first conductive structure 242 is gradual, the maximum thickness is defined as the third thickness T3, the fourth thickness T4, the fifth thickness T5, or/and the sixth thickness T6.

FIG. 3 is a schematic top view of a photoelectric semiconductor element 500b according to some embodiments of the present disclosure. FIG. 4 is a schematic cross-sectional view of a photoelectric semiconductor element 500b according to some embodiments of the present disclosure taken along the tangent line A-A' in FIG. 3. Component symbols in FIGS. 3 and 4 that are the same or similar to those in FIGS. 1 and 2 represent the same or similar components. The difference between the photoelectric semiconductor element 500b and the photoelectric semiconductor element 500a is that the photoelectric semiconductor element 500b replaces the second contact layer 234 with the third contact layer 232 as an electrical connection between the second electrode 248 and the second type semiconductor layer 208c. In some embodiments, the third contact layer 232 completely covers the top surface of the first type semiconductor layer 208a in the second high plateau region 212, and the width of the third contact layer 232 may be equal to or smaller than the width of the first type semiconductor layer 208a in the second high plateau region 212. The third contact layer 232 is located between the semiconductor stack 208 and the second electrode 248 and is partially covered by the insulating structure 236, and the top surface of the third contact layer 232 contacts the insulating structure 236 and the second electrode 248 at the same time.

Figures 5A, 6A, 7A, and 8 are top views of the intermediate stages of manufacturing a photoelectric semiconductor device 500a according to some embodiments of the present disclosure. Figures 5B, 6B, and 7B are cross-sectional views taken along the tangent line AA' in Figures 5A, 6A, and 7A, respectively. The following uses the photoelectric semiconductor device 500a as an example, and with Figures 5A, 5B, 6A, 6B, 7A, 7B, and 8 to illustrate the formation method of the conductive structures 242 and 244, the first electrode 246, and the second electrode 248 of the photoelectric semiconductor device 500a.

5A and 5B, after forming the semiconductor stack 208, the first contact layer 230, the second contact layer 234 and the insulating structure 236 on the substrate 204, the conductive material layer 240 is formed on the semiconductor stack 208. The conductive material layer 240 fully covers the semiconductor stack 208, the first contact layer 230, the second contact layer 234 and the insulating structure 236, and extends to cover a portion of the substrate 204. In some embodiments, the conductive material layer 240 can be formed by a deposition process. The deposition process includes evaporation, sputtering, or other suitable vacuum coating processes. In an embodiment where the deposition process is an evaporation process, due to the principle of the evaporation process, the thickness of the deposited conductive material layer 240 on the sidewalls 220, 224 of the semiconductor stack 208 may be less than or equal to the thickness of the conductive material layer 240 on the top surfaces of the first high plateau region 210, the second high plateau region 212, the first flat region 216, the second flat region 214 and the third flat region 218 of the semiconductor stack 208.

6A and 6B, then, masks 310 and 320 separated from each other are formed on the conductive material layer 240. The masks 310 and 320 are respectively located directly above the first flat area 216 and the second high plateau area 212 to define the formation position and size of the first electrode 246 and the second electrode 248. In some embodiments, the mask 310 covers the first flat area 216 and the first contact layer 230, and extends to cover the first high plateau area 210 and the second high plateau area 212 adjacent to the first flat area 216. The mask 320 covers a portion of the second high plateau area 212 and the second contact layer 234. In some embodiments, the masks 310 and 320 are separated from each other by a distance W2.

7A and 7B, the conductive material layer 240 is then subjected to a first etching process to form a first electrode 246 and a second electrode 248 on the top surfaces of the first flat region 216 and the second high plateau region 212 of the semiconductor stack 208, and to form conductive structures 242 and 244 on the sidewalls 220 and 224 of the semiconductor stack 208, respectively. The conductive structure 242 surrounds and covers the sidewall 220 of the semiconductor stack 208, and the conductive structure 244 surrounds and covers the sidewall 224 of the semiconductor stack 208. In some embodiments, the first etching process includes dry etching. After the first etching process is performed, the masks 310 and 320 are removed.

Referring to FIG. 8 , masks 330 and 340 separated from each other are then formed on the first electrode 246 and the second electrode 248 to cover the first electrode 246 and the second electrode 248, respectively. In some embodiments, the top-view areas of the masks 330 and 340 are respectively larger than the top-view areas of the first electrode 246 and the second electrode 248. As shown in FIG. 8 , the mask 330 is located directly above the first electrode 246 and extends to cover part of the sidewalls 220 and 224 of the semiconductor stack 208. In detail, the mask 330 completely covers the first electrode 246, and covers the top and sidewalls 224a1 of the first high plateau region 210, and the top and sidewalls 220a of the second flat region 214. The mask 340 is located directly above the second electrode 248, and extends to cover part of the sidewalls 220, 224 of the semiconductor stack 208. In detail, the mask 340 completely covers the second electrode 248, and covers the top and sidewalls 224b1, 224b2 of the second high plateau region 212, and the top and sidewalls 220b of the third flat region 218. As shown in FIG. 8 , the masks 330 and 340 are spaced apart from each other by a distance W1, so that portions of the conductive structures 242 and 244 on the sidewalls 220 and 224 of the semiconductor stack 208 are exposed. Then, a second etching process is performed on the conductive structures 242 and 244 to remove portions of the conductive structures 242 and 244 on the sidewalls 220 and 224 surrounding the semiconductor stack 208, and the conductive structure 242 has separated first regions 242a and second regions 242b, and the conductive structure 244 has separated third regions 244a and fourth regions 244b. After the second etching process is performed, the masks 330 and 340 are removed to form the optoelectronic semiconductor device 500a shown in FIG. 1 . In some embodiments, the distance W1 between the masks 330 and 340 is smaller than the distance W2 between the first electrode 246 and the second electrode 248 to ensure that the first electrode 246 and the second electrode 248 are not damaged during the second etching process. In some embodiments, the second etching process is a different etching process from the first etching process, such as a wet etching process, to completely remove the conductive structures 242, 244 on the side walls 220, 224 of the semiconductor stack 208 that are not covered by the masks 330, 340, so as to ensure that when the first electrode 246 and the second electrode 248 of the finally formed optoelectronic semiconductor element 500a are assembled and electrically connected to the external circuit, they will not be electrically connected to the conductive structures 242, 244 on the side walls 220, 224 surrounding the semiconductor stack 208, causing a short circuit problem in the optoelectronic semiconductor element.

FIG. 9 is a schematic top view of a photoelectric semiconductor element 500c according to some embodiments of the present disclosure. FIG. 10 is a schematic cross-sectional view of a photoelectric semiconductor element 500c according to some embodiments of the present disclosure taken along the tangent line A-A' in FIG. 9. Component symbols in FIGS. 9 and 10 that are the same or similar to those in FIGS. 1 and 2 represent the same or similar components. The difference between the photoelectric semiconductor element 500c and the photoelectric semiconductor element 500a is that the semiconductor stack 208 of the photoelectric semiconductor element 500c does not include the second flat area 214 and the third flat area 218, that is, the semiconductor stack 208 only includes the first high plateau area 210, the second high plateau area 212 and the first flat area 216. The semiconductor stack 208 includes a side wall 226. In detail, the sidewall 226 may include the sidewalls 226a1 and 226a2 of the first high plateau region 210 and the sidewalls 226b1 and 226b2 of the second high plateau region 212. The insulating structure 236 may cover the top surface and the sidewalls 226a1 and 226a2 of the first high plateau region 210, a portion of the top surface of the first flat region 216, and the sidewalls 226b1 and 226b2 and a portion of the top surface of the second high plateau region 212. The first conductive structure 242 has a first region 242a and a second region 242b that are physically separated from each other. The first region 242a covers the sidewall 226a1, and the second region 242b covers the sidewall 226b1.

Although the present disclosure is disclosed in the above embodiments, they are not intended to limit the present disclosure. A person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the attached patent application.

201: top surface 203: bottom surface 204: substrate 205: edge 206: bonding layer 208: semiconductor stack 208a: first type semiconductor layer 208b: active layer 208c: second type semiconductor layer 210: first high plateau area 212: second high plateau area 214: second flat area 216: first flat area 218: third flat area 220,220a,220b,224,224a1,224a2,224b1,224b2,226,226a1,226a2,226b1,226b2: sidewall 230: first contact layer 232: third contact layer 234: second contact layer 236: insulating structure 236a: first insulating portion 236b: second insulating portion 240: conductive material layer 242, 244: conductive structure 242a: first region 242b: second region 244a: third region 244b: fourth region 246: first electrode 248: second electrode 250: direction 310, 320, 330, 340: mask 500a, 500b, 500c: optoelectronic semiconductor element A-A': tangent T1: first thickness T2: second thickness T3: third thickness T4: fourth thickness T5: Fifth thickness T6: Sixth thickness W1, W1', W2: Spacing θ: Angle

The following will be described in detail with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present disclosure. Figure 1 is a top view of a photoelectric semiconductor element according to some embodiments of the present disclosure. Figure 2 is a cross-sectional schematic diagram of a photoelectric semiconductor element according to some embodiments of the present disclosure taken along the tangent line A-A' in Figure 1. Figure 3 is a top view of a photoelectric semiconductor element according to some embodiments of the present disclosure. Figure 4 is a cross-sectional schematic diagram of a photoelectric semiconductor element according to some embodiments of the present disclosure taken along the tangent line A-A' in Figure 3. Figures 5A, 6A, 7A, and 8 are schematic top views of the intermediate stages of manufacturing optoelectronic semiconductor devices according to some embodiments of the present disclosure. Figures 5B, 6B, and 7B are schematic cross-sectional views taken along the tangent line A-A' in Figures 5A, 6A, and 7A, respectively, of the intermediate stages of manufacturing optoelectronic semiconductor devices according to some embodiments of the present disclosure. Figure 9 is a schematic top view of an optoelectronic semiconductor device according to some embodiments of the present disclosure. Figure 10 is a schematic cross-sectional view of an optoelectronic semiconductor device according to some embodiments of the present disclosure taken along the tangent line A-A' in Figure 9.

206:Joint layer

205: Edge

208:Semiconductor stacking

220,220a,220b,224,224a1,224b1: Side wall

230: First contact layer

234: Second contact layer

236: Insulation structure

236a: First Insulation Section

236b: Second insulation section

242,244: Conductive structure

242a: First area

242b: Second area

244a: The third area

244b: The fourth area

246: First electrode

248: Second electrode

500a: Optoelectronic semiconductor components

A-A': Tangent

W1,W1',W2: Spacing

Claims (10)

A photoelectric semiconductor element comprises: A semiconductor stack, wherein the semiconductor stack comprises an upper surface, a first sidewall and a second sidewall; A first electrode, covering the upper surface of the semiconductor stack; A first conductive structure, physically separated from the first electrode and covering the first sidewall; and A second conductive structure, physically separated from the first electrode and covering the second sidewall; wherein the first sidewall has a first slope, and the second sidewall has a second slope different from the first slope. A photoelectric semiconductor device as claimed in claim 1, wherein the first electrode, the first conductive structure and the second conductive structure have the same material. A photoelectric semiconductor element as described in claim 1 or 2, wherein the first electrode comprises a metal oxide. A photoelectric semiconductor element as described in claim 1, wherein the photoelectric semiconductor element has a length of 10 microns to 150 microns and a width of 5 microns to 100 microns. The optoelectronic semiconductor device as described in claim 1 further includes an insulating structure located between the first conductive structure and the first sidewall, and between the second conductive structure and the second sidewall. The optoelectronic semiconductor device as described in claim 5 further comprises a substrate and a bonding layer, wherein the bonding layer is located between the substrate and the insulating structure. A optoelectronic semiconductor element as described in claim 6, wherein the second side wall is closer to the substrate than the first side wall. The optoelectronic semiconductor device as described in claim 1, wherein the thickness of the first conductive structure is smaller than the thickness of the first electrode. The optoelectronic semiconductor element as described in claim 1 or 8, wherein the thickness of the first conductive structure is 0.3 to 0.8 times the thickness of the first electrode. The optoelectronic semiconductor element as described in claim 1 further includes a contact layer completely covering the upper surface of the semiconductor stack.