TW202433616A - Electronic device and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of an electronic device and an electronic device are disclosed. The method includes: forming an intermediate layer on a first carrier and patterning the intermediate layer to form a plurality of alignment marks; forming a release layer on the first carrier; disposing a plurality of chips on the release layer, each of the chips including a bonding pad and a surface adjacent to the bonding pad; forming an insulating layer on the release layer to surround the chips, so as to form a package structure; transferring the package structure to the second carrier and enabling the surface of each of the chips to face away from the second carrier and an upper surface of the insulating layer to expose the surface of each of the chips, wherein a step difference is formed between the surface of each of the chips and at least a portion of the upper surface of the insulating layer in a normal direction of the surface of each of the chips; and forming a redistribution layer on the package structure, the redistribution layer electrically connected to each of the chips through the bonding pads.

Description

Electronic device and method of manufacturing the same

The present disclosure relates to a method for manufacturing an electronic device and a related electronic device, and in particular to a method for manufacturing an electronic device with improved alignment accuracy and an electronic device manufactured by the method.

The manufacturing and production technologies of some electronic devices today often include the process of packaging electronic components or rerouting circuits. However, if the circuits and electronic components in the electronic device are misaligned, it will cause electrical failure or reliability abnormality. Therefore, how to improve the alignment accuracy between electronic components in electronic devices or between electronic components and circuits is an important issue.

One of the purposes of the present disclosure is to provide a method for manufacturing an electronic device and a related electronic device to solve the problems encountered in the existing method for manufacturing an electronic device, thereby improving the alignment accuracy and reducing the cost.

An embodiment of the present disclosure provides a method for manufacturing an electronic device, comprising: forming an intermediate layer on a first carrier and patterning the intermediate layer to form a plurality of alignment marks; forming a release layer on the first carrier; placing a plurality of chips on the release layer, wherein each chip includes a bonding pad and a surface adjacent to the bonding pad; forming an insulating layer on the release layer, the insulating layer surrounding the plurality of chips so that the insulating layer is in contact with the plurality of chips. A package structure is formed; the package structure is transferred to a second carrier so that the surface of each chip faces away from the second carrier and the upper surface of the insulating layer exposes the surface of each chip, wherein a step is formed between the surface of each chip and at least a portion of the upper surface of the insulating layer in the normal direction of the surface of each chip; and a redistribution layer is formed on the package structure, and the redistribution layer is electrically connected to each chip through a bonding pad.

An embodiment of the present disclosure provides an electronic device, including a chip, an insulating layer, and a redistribution unit. The chip includes a bonding pad and a surface adjacent to the bonding pad. The insulating layer surrounds the chip, and the upper surface of the insulating layer exposes the surface of the chip. The redistribution unit is disposed on the chip and the insulating layer and is electrically connected to the chip through the bonding pad. In the normal direction of the surface of the chip, there is a step difference between the surface of the chip and at least a portion of the upper surface of the insulating layer, and the step difference range is greater than or equal to 2 microns and less than or equal to 10 microns.

The following is a detailed description of the contents of the present disclosure in conjunction with specific embodiments and drawings. It should be noted that, in order to facilitate the reader's understanding and simplify the drawings, the multiple drawings in the present disclosure only depict a portion of the device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawing are only for illustration and are not used to limit the scope of the present disclosure.

Certain terms are used throughout the specification and patent application to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document is not intended to distinguish between components that have the same function but different names. In the following specification and patent application, the words "containing" and "including" are open-ended words, so they should be interpreted as "including but not limited to..." When the terms "including", "including", "containing" and/or "having" are used in this specification, they specify the presence of the features, regions, steps, operations and/or elements, but do not exclude the presence or addition of one or more other features, regions, steps, operations, elements and/or combinations thereof.

When an element or a layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or directly connected to the other element or layer, or there may be intervening elements or layers therebetween. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there may be no intervening elements or layers therebetween.

The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used for explanation, and are not used to limit the present disclosure.

The terms "approximately," "equal to," "equal" or "same," "substantially" or "substantially" are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

The ordinal numbers used in the specification and patent application, such as "first", "second", etc., are used to modify the components. They do not imply or represent any previous ordinal number of the component (or components), nor do they represent the order of one component to another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms. Accordingly, the first component in the specification may be the second component in the patent application.

The electronic device disclosed herein can be applied to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device can be a bendable or flexible electronic device. The display device can be a non-self-luminous display device or a self-luminous display device. The antenna device can be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device can be a sensing device for sensing capacitance, light, heat energy or ultrasound, but is not limited thereto. The electronic device can include electronic components such as passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The splicing device can be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above arrangements, but is not limited thereto. The process of the electronic device disclosed herein can be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, and can be a chip-first or chip-last process, but is not limited thereto.

It should be understood that features of several different embodiments may be replaced, reorganized, or mixed to implement other embodiments without departing from the spirit of the present disclosure.

Please refer to FIG. 1 and FIG. 2A to FIG. 2F. FIG. 1 is a schematic flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 2A to FIG. 2F are schematic process charts of a method for manufacturing an electronic device according to a first embodiment of the present disclosure. As shown in FIG. 1, the method for manufacturing an electronic device according to an embodiment of the present disclosure may include steps S100 to S150, which are described in detail as follows. According to the method for manufacturing an electronic device according to the first embodiment of the present disclosure, as shown in FIG. 2A, step S100 is first performed to form an intermediate layer 110 on a first carrier 100 and pattern the intermediate layer 110 to form a plurality of alignment marks 112. The "carrier" described in the present disclosure may include steel plates, glass, polyimide (PI), polyethylene terephthalate (PET), wafers, other suitable materials or combinations of the above materials. The middle layer 110 may include at least one of an organic material, an inorganic material, a metal material and a photoresist material, that is, the middle layer 110 may include one of an organic material, an inorganic material, a metal material and a photoresist material or a composite material formed by a combination of the above materials. The photoresist material may include a positive photoresist material or a negative photoresist material. The middle layer 110 may include, for example, a polymer, titanium, molybdenum, silicon oxide (SiOx), silicon nitride (SiNx), other suitable materials or combinations of the above materials, but is not limited thereto. In some embodiments, as shown in FIG. 2A , before the step of forming the intermediate layer 110, a release layer 102 and a light-transmitting substrate 104 may be selectively formed on the first carrier 100. That is, the intermediate layer 110 is formed on the light-transmitting substrate 104, and the light-transmitting substrate 104 may be disposed between the first carrier 100 and the patterned alignment mark 112. The light-transmitting substrate 104 is attached to the first carrier 100 through the release layer 102, which can increase the thickness of the overall structure to reduce the probability of warpage in subsequent processes (such as a molding process). The light-transmitting substrate 104 may include glass or other suitable materials with high light transmittance, so that the alignment mark 112 formed on the surface of the light-transmitting substrate 104 can be more easily identified. The "release layer" described in the present disclosure may include an adhesive material, such as a glue material that can be separated by laser, light or thermal decomposition, but is not limited thereto. The light-transmissive substrate or substrate with high light transmittance referred to in the present disclosure means that visible light, ultraviolet light and/or infrared light can penetrate the substrate. For example, the transmittance of the substrate to the light source is at least greater than or equal to 75%, wherein the transmittance can be measured by an optical instrument.

Next, as shown in FIG. 2B , step S110 may be performed to form a release layer 120 on the first carrier 100. The step S110 of forming the release layer 120 on the first carrier 100 may be performed after the step of forming a plurality of alignment marks 112, and the release layer 120 covers the alignment marks 112, for example, the release layer 120 may cover the upper surface and the side surface of the alignment mark 112. Then, step S120 may be performed to place a plurality of chips 130 on the release layer 120, wherein each chip 130 includes a bonding pad 132 and a surface 130a adjacent to the bonding pad 132. In detail, each chip 130 may have a surface 130a adjacent to the bonding pad 132 and another surface 130b away from the bonding pad 132 and opposite to the surface 130a, wherein the surface 130a of each chip 130 may contact the release layer 120. As shown in FIG2B, each chip 130 may include a plurality of (e.g., two) bonding pads 132 and an insulating layer 134 covering the bonding pads 132, wherein the lower surface of the insulating layer 134 may be the surface 130a of the chip 130 contacting the release layer 120. The bonding pad 132 may include copper, aluminum, titanium, gallium, tantalum, other suitable materials, or combinations thereof. The insulating layer 134 may include an organic material, an inorganic material, a dielectric material or other suitable insulating material, such as (but not limited to) polyimide, epoxy resin, silicon nitride (SiNx), silicon oxide (SiOx) or a combination thereof. According to some embodiments, the chip 130 may have at least one insulating layer 134, that is, the chip 130 may include a single layer or multiple layers of insulating layers, and the insulating layer may be used to protect the bonding pad 132 or reduce the probability of wafer breakage during cutting, but is not limited thereto. The chip 130 may include, for example, a diode or a semiconductor die, but is not limited thereto. The diode may include a light-emitting diode or a photodiode. For example, the light emitting diode may include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED, but not limited thereto. The chip 130 may be a known good die (KGD), which may include various electronic components, such as (but not limited to) wires, transistors, etc. Adjacent chips 130 may have different functions from each other, such as an integrated circuit, a radio frequency integrated circuit (RFIC), a dynamic random access memory (D-RAM), but not limited thereto. According to the embodiment shown in FIG. 2B , the step S120 of placing a plurality of chips 130 on the release layer 120 is to place each chip 130 between two adjacent alignment marks 112, that is, each chip 130 does not overlap the alignment mark 112 in the direction Z, wherein the direction Z may be parallel to the normal direction of the surface 130a of the chip 130 and perpendicular to the horizontal direction. The term "adjacent to" in the present disclosure may mean that in a direction, the distance between component A and component B is very small or has a minimum distance, or may mean that in a direction, there are no other identical components between two identical components.

Next, as shown in FIG. 2C , step S130 may be performed to form an insulating layer 140 on the release layer 120, wherein the insulating layer 140 surrounds the plurality of chips 130 so that the insulating layer 140 and the plurality of chips 130 form a package structure PS. The term “surrounding” in the present disclosure may mean that in a cross-sectional view, the insulating layer 140 at least contacts one surface of the chip 130, for example, the insulating layer 140 covers the side surface and/or the surface 130b of the chip 130. The insulating layer 140 may be used to isolate moisture, air, and/or reduce damage to the chip 130. The insulating layer 140 may include organic resin, epoxy resin, epoxy molding compound (EMC), ceramic, poly(methyl methacrylate) (PMMA), polydimethylsiloxane (PDMS), other suitable materials or combinations of the above materials, but not limited thereto. The insulating layer 140 may include fillers, such as silicon oxide, but not limited thereto. According to some embodiments, the particle size of the filler is greater than or equal to 0.05 micrometers (µm) and less than or equal to 30 micrometers (µm), or greater than or equal to 0.1 micrometers (µm) and less than or equal to 25 micrometers (µm). When the insulating layer 140 is formed, each chip 130 is subjected to pressure due to the packaging process, so that a portion of each chip 130 sinks into the release layer 120 , that is, as shown in FIG. 2C , the bottom surface 130 a of each chip 130 is lower than the bottom surface of the insulating layer 140 .

Then, as shown in FIG. 2D , step S140 may be performed to transfer the package structure PS to the second carrier 200, so that the surface 130a of each chip 130 faces away from the second carrier 200, and the upper surface 140a of the insulating layer 140 exposes the surface 130a of each chip 130. In the direction Z, a step difference ST is formed between the surface 130a of each chip 130 and at least a portion of the upper surface 140a of the insulating layer 140. The step difference ST may range from greater than or equal to 2 microns to less than or equal to 10 microns (i.e., 2µm≤ST≤10µm). If the step difference ST exceeds the above range, the reliability of the package structure PS and the manufactured electronic device may be affected. For example, when the step difference ST is too large, the structure formed by the subsequent process on the package structure PS may be unstable, such as causing the conductive layer to rupture, thereby affecting the electrical properties. When the step difference ST is too small, it may not be sufficient to allow the film layers in the structure formed by the subsequent process to be engaged and/or fixed, but the invention is not limited thereto. The multiple step differences ST between the surface 130a of each chip 130 and the upper surface 140a of the insulating layer 140 are formed by the chip 130 being pressed when the insulating layer 140 is formed as described above, thereby forming a height difference in the direction Z. In detail, as shown in FIG. 2D , in the direction Z, there is a first distance between the surface 130a of the chip 130 and the lower surface 140b of the insulating layer 140 opposite to the upper surface 140a, and there is a second distance between the upper surface 140a and the lower surface 140b of the insulating layer 140. The difference between the first distance and the second distance can be defined as a step difference ST, wherein the first distance can be greater than the second distance. In some embodiments, the step S140 of transferring the package structure PS to the second carrier 200 may include: first, the second carrier 200 may be attached to one side of the package structure PS (e.g., the side opposite to the first carrier 100) through the release layer 202. Next, the whole structure can be turned upside down, and the first carrier 100, the release layer 120, and the plurality of alignment marks 110 can be removed. Then, the bonding pads 132 of the chip 130 are exposed. For example, holes can be formed in the insulating layer 134 of the chip 130 at positions corresponding to the conductive pads 132 to expose the bonding pads 132. For example, (but not limited to) the holes are formed by a patterning process such as etching. According to some embodiments, a hole may be formed in the insulating layer 134 of the chip 130 at a position corresponding to the conductive pad 132 to expose the bonding pad 132, and then the chip 130 is disposed on the release layer 120, and then the insulating layer 140 is disposed on the release layer 120, so that the insulating layer 140 surrounds the multiple chips 130 so that the insulating layer 140 and the multiple chips 130 constitute a package structure PS. However, the step S140 of transferring the package structure PS to the second carrier 200 is not limited to the above. In other embodiments, the first carrier 100, the release layer 120 and the plurality of alignment marks 110 may be removed first, and then the package structure PS is turned over and attached to the second carrier 200 through the release layer 202.

Next, as shown in FIG. 2E and FIG. 2F , step S150 may be performed to form a redistribution layer (RDL) 210 on the package structure PS, and the redistribution layer 210 is electrically connected to each chip 130 through the bonding pad 132. The redistribution layer 210 may include at least one conductive layer 212 and at least one insulating layer 214. The redistribution layer 210 may redistribute the circuit and/or further increase the circuit fan-out area, or different electronic components may be electrically connected to each other through the redistribution layer 210. In some embodiments, before forming the redistribution wiring layer 210, the warpage of the structure may be suppressed by a warpage reduction device, and then the redistribution wiring layer 210 may be formed by processes such as thin film deposition, acid etching, alkaline etching, surface treatment, plasma treatment, exposure and/or laser, but not limited thereto. Specifically, as shown in FIG. 2E , a patterned conductive layer 212 may be formed on the insulating layer 140 and the insulating layer 134 of each chip 130 , and the conductive layer 212 may be filled in the holes of the insulating layer 134 and electrically connected to the bonding pads 132 of each chip 130 . The step difference ST between the surface 130a of the chip 130 and the upper surface 140a of the insulating layer 140 (as shown in FIG. 2D ) can achieve a locking and/or fixing effect at the junction of the conductive layer 212, the insulating layer 134 and the insulating layer 140, thereby improving the adhesion between the film layers. Then, as shown in FIG. 2F , an insulating layer 214 can be formed on the conductive layer 212 to form a redistribution layer 210. The conductive layer 212 may include copper, aluminum, titanium, tantalum or other suitable conductive materials. The conductive layer 212 may be a single layer or a multi-layer stack. The insulating layer 214 may include organic materials, inorganic materials, dielectric materials or other suitable insulating materials, such as (but not limited to) polyimide, epoxy resin and/or silicon dioxide. Any two of the insulating layer 134, the insulating layer 140 and the insulating layer 214 may include the same or different materials, which may be selected according to the overall stress size or actual design. The redistribution layer 210 may include a plurality of redistribution units 210U, each of which is electrically connected to at least one of the plurality of chips 130. As shown in FIG. 2F , a portion of the conductive layer 212 and a portion of the insulating layer 214 in the redistribution layer 210 may constitute a redistribution unit 210U, and each redistribution unit 210U may correspond to and be electrically connected to a chip 130. The chip 130 may be electrically connected to at least one external component through the redistribution layer 210, wherein the external component may include another chip, a resistor, a capacitor, an inductor, an antenna unit, a sensing unit, a printed circuit board, a driving unit, a combination thereof, or other suitable external components or electronic units.

As shown in FIG. 2F , after step S150 of forming the redistribution wiring layer 210, a plurality of bonding elements 220 may be formed on the redistribution wiring layer 210, wherein the plurality of bonding elements 220 are electrically connected to the redistribution wiring layer 210. Specifically, the insulating layer 214 of the redistribution wiring layer 210 may expose the surface of the conductive layer 212 located at the uppermost layer, and then a plurality of bonding elements 220 may be formed on the exposed conductive layer 212 in the redistribution wiring layer 210, so that the bonding elements 220 may be electrically connected to the bonding pads 132 of each chip 130 through one of the redistribution wiring units 210U. The bonding element 220 may be a bump, a pad, a solder ball or other suitable bonding elements. The bonding element 220 may include, for example, copper, tin, nickel, gold, lead, silver, gallium, other suitable conductive materials or a combination of the above materials, but is not limited to the above. After forming a plurality of bonding elements 220, the package structure PS may be cut along the cutting line CL, and then the second carrier 200 and the release layer 202 may be removed, thereby obtaining an electronic device ED including the chip 130 as shown in FIG. 3 .

Please refer to FIG. 3, which is a cross-sectional schematic diagram of an electronic device of an embodiment of the present disclosure. As shown in FIG. 3, the electronic device ED manufactured by the method of the first embodiment includes a chip 130, an insulating layer 140, and a redistribution unit 210U. The chip 130 includes a bonding pad 132 and a surface 130a adjacent to the bonding pad 132. The insulating layer 140 surrounds the chip 130, and the upper surface 140a of the insulating layer 140 exposes the surface 130a of the chip 130. The redistribution unit 210U is disposed on the chip 130 and the insulating layer 140 and is electrically connected to the chip 130 through the bonding pad 132. In which, in the normal direction Z of the surface 130a of the chip 130, there is a step difference ST between the surface 130a of the chip 130 and at least a portion of the upper surface 140a of the insulating layer 140. The step difference ST may range from greater than or equal to 2 microns and less than or equal to 10 microns (i.e., 2µm≤ST≤10µm). The electronic device ED may also include a plurality of bonding elements 220, which are disposed on the conductive layer 212 exposed by the insulating layer 214 in the redistribution unit 210U and electrically connected to the conductive layer 212. In some embodiments, the bonding element 220 of the electronic device ED may be further electrically connected to a circuit board (not shown), but is not limited thereto.

According to the manufacturing method of the electronic device and the manufactured electronic device, during the manufacturing process, multiple chips 130 can be aligned according to the multiple alignment marks 112 to improve the alignment accuracy. In addition, the alignment marks 112 are formed by patterning the middle layer 110 on the carrier, and the manufacturing process is simpler and can be removed more easily. The position of each alignment mark 112 can be defined more accurately, and the manufacturing cost can be reduced.

Please refer to FIG. 4, which is an enlarged cross-sectional schematic diagram of an alignment mark on a carrier according to an embodiment of the present disclosure. As shown in FIG. 4, the alignment mark 112 formed on the first carrier 100 may be a multi-layer structure including a first sub-layer 112a and a second sub-layer 112b, wherein the first sub-layer 112a and the second sub-layer 112b may include organic materials, inorganic materials, metal materials, photoresist materials or other suitable materials, and the materials of the first sub-layer 112a and the second sub-layer 112b may be the same or different. The first sub-layer 112a is located between the second sub-layer 112b and the first carrier 100, which can improve the adhesion between the second sub-layer 112b and the first carrier 100. The first sub-layer 112a can also serve as a buffer layer. In other embodiments, the first sub-layer 112a may be formed entirely on the first carrier 100, but is not limited thereto.

Other embodiments of the method for manufacturing an electronic device disclosed herein and the electronic devices manufactured thereby will be described in detail below. To simplify the description, the same reference numerals are used below to label the same elements. The differences between the different embodiments will be mainly described in detail below, and the same features will not be repeated.

Please refer to FIG. 5A to FIG. 5B and FIG. 1. FIG. 5A to FIG. 5B are process diagrams of the manufacturing method of the electronic device of the second embodiment of the present disclosure. According to the manufacturing method of the electronic device of the second embodiment of the present disclosure, as shown in FIG. 5A, the step S110 of forming the release layer 120 on the first carrier 100 can be performed before the step of forming the intermediate layer 110. That is, the release layer 120 is first formed on the first carrier 100, and then the intermediate layer 110 is formed on the release layer 120 and the intermediate layer 110 is patterned to form a plurality of alignment marks 112. In the direction Z, the height H1 of each alignment mark 112 is greater than or equal to one third of the height H2 of at least one chip 130 to be subsequently arranged and less than or equal to one fourth of the height H2 of at least one chip 130 (i.e., H2*1/3 ≤ H1 ≤ H2*5/4). For example, when the heights of the chips 130 are different, the chip 130 with the smallest height can be used as a reference or design basis, but it is not limited to this. Then, step S120 is performed to arrange multiple chips 130 on the release layer 120, wherein each chip 130 is arranged between two adjacent alignment marks 112. Through the height design of the alignment mark 112, the chip 130 can be limited to reduce the position deviation of the chip 130. Then, step S130 is performed to form an insulating layer 140 on the release layer 120. The insulating layer 140 surrounds the plurality of chips 130 and the plurality of alignment marks 112 to form a package structure PS. When the insulating layer 140 is formed, each chip 130 is subjected to pressure due to the packaging process, so that a portion of each chip 130 sinks into the release layer 120 to form a plurality of step differences ST as shown in FIG. 5B .

Next, as shown in FIG. 5B , step S140 is performed to transfer the package structure PS to the second carrier 200, for example, the second carrier 200 is attached to one side of the package structure PS through the release layer 202 and the first carrier 100 and the release layer 120 are removed. In the normal direction Z of the surface 130a of the chip 130, a step ST is formed between the surface 130a of each chip 130 and at least a portion of the upper surface 140a of the insulating layer 140. Then, step S150 is performed to form a redistribution wiring layer 210 including at least one conductive layer 212 and at least one insulating layer 214 on the package structure PS, and to form a plurality of bonding elements 220 on the redistribution wiring layer 210, so that the bonding elements 220 can be electrically connected to the bonding pads 132 of each chip 130 through one of the redistribution wiring units 210U of the redistribution wiring layer 210. Then, the package structure PS can be cut along the cutting line CL, and then the second carrier 200 and the release layer 202 are removed, so that the electronic device ED including the chip 130 as shown in FIG. 3 can be obtained.

Please refer to FIG. 6A to FIG. 6C in conjunction with FIG. 1. FIG. 6A to FIG. 6C are schematic diagrams of the manufacturing process of the electronic device manufacturing method of the third embodiment of the present disclosure. According to the manufacturing method of the electronic device of the third embodiment of the present disclosure, as shown in FIG. 6A, the step S110 of forming the release layer 120 on the first carrier 100 can be performed after the step of forming a plurality of alignment marks 112. That is, the intermediate layer 110 is first formed on the first carrier 100 and the intermediate layer 110 is patterned to form a plurality of alignment marks 112, and then the release layer 120 is formed on the first carrier 100 and the plurality of alignment marks 112, so that the release layer 120 covers the alignment marks 112 in a stepped manner as the height of the alignment marks 112 rises and falls. Next, step S120 is performed to place a plurality of chips 130 on the release layer 120, wherein each chip 130 is placed on one of the alignment marks 130. In the normal direction Z of the surface 130a of the chip 130, the chips 130 can overlap the alignment marks 130 one by one. Then, step S130 is performed to form an insulating layer 140 on the release layer 120, and the insulating layer 140 surrounds the plurality of chips 130 to form a package structure PS.

Next, as shown in example (I) or example (II) of FIG. 6B , step S140 is performed to transfer the package structure PS to the second carrier 200. For example, the second carrier 200 can be attached to one side of the package structure PS through the release layer 202 and the first carrier 100, the release layer 120 and the plurality of alignment marks 112 are removed. The upper surface 140a of the insulating layer 140 can have a plurality of recesses 140G, and a protrusion 140P is provided on one side of the recess 140G and/or between two adjacent recesses 140G, so that a step ST1 is formed between the surface 130a of each chip 130 and a portion of the upper surface 140a of the insulating layer 140 (such as the surface of the protrusion 140P) in the direction Z. For example, after removing the plurality of alignment marks 112, a plurality of recesses 140G are formed on the upper surface 140a of the insulating layer 140. The recesses 140G and the protrusions 140P can further serve as alignment marks, so that subsequent processes performed on the package structure PS can be aligned according to the recesses 140G and/or the protrusions 140P. In detail, as shown in example (I) or example (II) of FIG. 6B , in direction Z, a first distance is provided between the surface 130a of the chip 130 and a lower surface 140b of the insulating layer 140 opposite to the upper surface 140a, and a second distance is provided between a portion of the upper surface 140a of the insulating layer 140 corresponding to the protrusion 140P and the lower surface 140b, and the difference between the first distance and the second distance can be defined as a step difference ST1, wherein the second distance is greater than the first distance. In some embodiments, as shown in example (I) of FIG. 6B , a portion of the upper surface 140a of the insulating layer 140 corresponding to the recess 140G can be coplanar with the surface 130a of the chip 130. In some embodiments, as shown in example (II) of FIG6B , a step ST2 may be formed between the surface 130a of each chip 130 and the portion of the upper surface 140a of the insulating layer 140 corresponding to the recessed portion 140G. When the insulating layer 140 is formed, each chip 130 is subjected to pressure due to the packaging process, so that a portion of each chip 130 sinks into the release layer 120 (shown in FIG6A ), thereby forming the step ST2.

After the process shown in FIG. 6B , as shown in FIG. 6C , step S150 is performed to form a redistribution layer 210 including at least one conductive layer 212 and at least one insulating layer 214 on the package structure PS, and to form a plurality of bonding elements 220 on the redistribution layer 210, so that the bonding elements 220 can be electrically connected to the bonding pads 132 of each chip 130 through one of the redistribution units 210U of the redistribution layer 210. Then, the package structure PS can be cut along the cutting line CL, and then the second carrier 200 and the release layer 202 are removed, so that the electronic device ED including the chip 130 as shown in FIG. 7 can be obtained.

Please refer to FIG. 7, which is a cross-sectional schematic diagram of an electronic device of another embodiment of the present disclosure. As shown in FIG. 7, the electronic device ED manufactured by the method of the third embodiment includes a chip 130, an insulating layer 140, and a redistribution unit 210U, and its detailed structure and the materials included can refer to the aforementioned embodiments, and will not be repeated here. In the normal direction Z of the surface 130a of the chip 130, there is a step difference ST1 between the surface 130a of the chip 130 and at least a portion of the upper surface 140a of the insulating layer 140 (such as the surface of the protrusion 140P). The upper surface 140a of the insulating layer 140 has a recessed portion 140G adjacent to the chip 130, and the portion of the upper surface 140a of the insulating layer 140 corresponding to the recessed portion 140G may be coplanar with the surface 130a of the chip 130. The electronic device ED may further include a plurality of bonding elements 220 disposed on the conductive layer 212 exposed by the insulating layer 214 in the redistribution unit 210U and electrically connected to the conductive layer 212. One difference between FIG. 7 and FIG. 3 is that a surface of the conductive layer 212 shown in FIG. 7 exposed by the insulating layer 214 may be lower than the surface of the insulating layer 214, wherein the surface of the conductive layer 212 may be a concave surface, a curved concave surface, or a curved rough concave surface. Specifically, the surface of the conductive layer 212 exposed by the insulating layer 214 may be a rough concave surface lower than the insulating layer 214 through surface treatment, such as acid etching, alkaline etching, laser, plasma, other suitable methods or a combination thereof. The above design can enhance the bonding strength between the conductive layer 212 and the bonding element 220, but is not limited thereto.

Please refer to FIG. 8A to FIG. 8D in conjunction with FIG. 1. FIG. 8A to FIG. 8D are schematic diagrams of the manufacturing process of the electronic device manufacturing method of the fourth embodiment of the present disclosure. According to the manufacturing method of the electronic device of the fourth embodiment of the present disclosure, as shown in FIG. 8A, the step S110 of forming the release layer 120 on the first carrier 100 can be performed after the step of forming a plurality of alignment marks 112. That is, the intermediate layer 110 is first formed on the first carrier 100 and the intermediate layer 110 is patterned to form a plurality of alignment marks 112, and then the release layer 120 is formed on the first carrier 100 and the plurality of alignment marks 112, so that the release layer 120 covers the alignment marks 112 in a stepped manner as the height of the alignment marks 112 rises and falls. Next, step S120 is performed to place a plurality of chips 130 on the release layer 120, wherein each chip 130 is placed between two adjacent alignment marks 112. Then, step S130 is performed to form an insulating layer 140 on the release layer 120, and the insulating layer 140 surrounds the plurality of chips 130 to form a package structure PS. In some embodiments, after step S130, a grinding process may be selectively performed by a grinding device GR as shown in FIG. 8A to remove a portion of the insulating layer 140 higher than the chip 130 to expose a surface 130b of each chip 130 away from the bonding pad 132, but the present invention is not limited thereto.

After the process shown in FIG. 8A , as shown in FIG. 8B , step S140 is performed to transfer the package structure PS to the second carrier 200. For example, the second carrier 200 can be attached to one side of the package structure PS through the release layer 202 and the first carrier 100, the release layer 120 and the plurality of alignment marks 112 are removed. After the plurality of alignment marks 112 are removed, a plurality of recesses 140G are formed on the upper surface 140a of the insulating layer 140, so that in the direction Z, a step ST3 is formed between the surface 130a of each chip 130 and a portion of the upper surface 140a of the insulating layer 140 (such as the surface of the recess 140G). The recessed portion 140G can further serve as an alignment mark, so that the subsequent process performed on the package structure PS can be aligned according to the recessed portion 140G. In detail, as shown in FIG8B , in the direction Z, there is a first distance between the surface 130a of the chip 130 and the lower surface 140b of the insulating layer 140 opposite to the upper surface 140a, and there is a second distance between the portion of the upper surface 140a of the insulating layer 140 corresponding to the recessed portion 140G and the lower surface 140b. The difference between the first distance and the second distance can be defined as a step difference ST3, wherein the first distance is greater than the second distance. In some embodiments, as shown in FIG8B , a step ST4 may be formed between the surface 130a of each chip 130 and a portion of the upper surface 140a of the insulating layer 140. When the insulating layer 140 is formed, each chip 130 is subjected to pressure due to the packaging process, so that a portion of each chip 130 sinks into the release layer 120 (shown in FIG8A ), thereby forming the step ST4.

Then, step S150 is performed to form a redistribution layer 210 including at least one conductive layer 212 and at least one insulating layer 214 on the package structure PS, and the conductive layer 212 of the redistribution layer 210 is electrically connected to each chip 130 through the bonding pad 132. The redistribution layer 210 may include a plurality of redistribution units 210U, and each redistribution unit 210U may be electrically connected to two adjacent chips 130. The step difference ST4 between the surface 130a of the chip 130 and the upper surface 140a of the insulating layer 140 can achieve a locking and/or fixing effect at the junction of the conductive layer 212, the insulating layer 134 and the insulating layer 140, thereby improving the adhesion between the film layers. As shown in FIG8B, when forming the redistribution layer 210, one or more through-hole structures TH are also formed. Each through-hole structure TH is located between two adjacent chips 130 and extends through the insulating layer 140, and each through-hole structure TH is connected to one of the conductive layers 212 in the redistribution unit 210U, so that each through-hole structure TH is electrically connected to the two adjacent chips 130. For example, a through hole THa may be formed in a portion between adjacent chips 130 in the insulating layer 140, and the position of the through hole THa may correspond to the position of one of the recessed portions 140G formed after the alignment mark 112 is removed, and a conductive material is filled into the through hole THa to form a through-hole structure TH, wherein the conductive material may include, for example, copper, tin, nickel, gold, titanium, other suitable conductive materials, or a combination of the above materials, but is not limited thereto. The conductive material filled into the through hole THa may be the same as the material of the conductive layer 212, or may be composed of the same material as the conductive layer 212. According to some embodiments, the through-hole structure TH may be hourglass-shaped, rectangular, trapezoidal, inverted trapezoidal, or other suitable shapes. According to some embodiments, the angle θ between the sidewall THb of the through hole structure TH and one of the surfaces of the insulating layer 214 may be greater than or equal to 95° and less than or equal to 150°, or the angle θ may be greater than or equal to 105° and less than or equal to 135°. In addition, the roughness of the sidewall THb of the through hole structure TH may be greater than the roughness of the surface of the insulating layer 214, as shown in FIG9 . Through the above design, the bonding degree between the conductive material in the through hole structure TH and the insulating layer 214 can be improved, the risk of cracking can be reduced, and the reliability can be improved, but it is not limited thereto.

Then, as shown in FIG. 8C , the package structure PS and the redistribution wiring layer 210 may be transferred to the third carrier 300. For example, the third carrier 300 may be attached to the insulating layer 214 of the redistribution wiring layer 210 on one side of the package structure PS through the release layer 302 and the second carrier 200 and the release layer 202 may be removed. Next, a conductive layer 310 may be formed on the side of the package structure PS opposite to the redistribution wiring layer 210, wherein the conductive layer 310 is electrically connected to the through-hole structure TH. For example, the conductive layer 310 may be formed by processes such as electroplating or chemical deposition. The conductive layer 310 may include copper or other suitable conductive materials. Before forming the conductive layer 310, a seed layer 312 may be formed on the side of the package structure PS opposite to the redistribution layer 210. The seed layer 312 may facilitate the formation of the conductive layer 310 and/or improve the adhesion between film layers. The seed layer 312 may include a single layer of material or multiple layers of material, such as titanium, copper, molybdenum, aluminum, nickel, silver, tin, other suitable conductive materials, or a combination of the above materials, but is not limited thereto. A plurality of photoresist patterns 314 may be formed on the seed layer 312. Each photoresist pattern 314 may correspond to one of the chips 130 or be located between two adjacent chips 310. Then, a conductive layer 310 may be formed on the seed layer 312. The plurality of photoresist patterns 314 may form a plurality of corresponding openings 310P in the conductive layer 310 (shown in FIG. 8D).

After the process shown in FIG. 8C , as shown in FIG. 8D , after removing the plurality of photoresist patterns 314, the conductive layer 310 may have a plurality of openings 310P, thereby reducing the area of the conductive layer 310 and reducing stress to reduce warping. Next, a bonding layer 320 may be formed on the conductive layer 310, so that the bonding layer 320 may be electrically connected to the through hole structure TH through the conductive layer 310 and electrically connected to the bonding pad 132 of each chip 130 through the through hole structure TH. The bonding layer 320 may include copper, tin, nickel, gold, lead, other suitable conductive materials, or a combination of the above materials, but is not limited thereto. According to the embodiment shown in FIG. 8D , the positions of the plurality of openings 310P in the bonding layer 320 and the seed layer 312 corresponding to the conductive layer 310 may be patterned to form a plurality of openings OP that are integrally connected from the bonding layer 320 through the conductive layer 310 to the seed layer 312. Then, the package structure PS may be cut along the cutting line CL, and then the third carrier 300 and the release layer 302 may be removed, thereby obtaining the electronic device ED including the chip 130 as shown in FIG. 9 .

Please refer to FIG. 9, which is a cross-sectional schematic diagram of an electronic device of another embodiment of the present disclosure. As shown in FIG. 9, the electronic device ED manufactured by the method of the fourth embodiment includes two chips 130, an insulating layer 140, and a redistribution unit 210U. The detailed structure and the materials included can refer to the aforementioned embodiments and will not be described in detail here. Among them, the upper surface 140a of the insulating layer 140 may have a recessed portion 140G adjacent to the chip 130. In the normal direction Z of the surface 130a of the chip 130, there may be a step difference ST3 between the portion of the upper surface 140a of the insulating layer 140 corresponding to the recessed portion 140G and the surface 130a of the chip 130. In addition, a step ST4 may be provided between the surface 130a of each chip 130 and another portion of the upper surface 140a of the insulating layer 140. The electronic device ED may further include a seed layer 312, a conductive layer 310, and a bonding layer 320, which are sequentially stacked and arranged on a side of the package structure PS opposite to the redistribution layer 210, and are electrically connected to one of the conductive layers 212 in the redistribution unit 210U through a through-hole structure TH located between two adjacent chips 130 and extending through the insulating layer 140. In some embodiments, the bonding layer 320 of the electronic device ED may be further electrically connected to a circuit board (not shown), but is not limited thereto.

In some embodiments, after performing step S140 as shown in FIG8B , that is, transferring the package structure PS to the second carrier 200 and removing the plurality of alignment marks 112 to form a plurality of recessed portions 140G, a step S150 of forming a redistribution wiring layer 210 on the package structure PS as shown in FIG2E and FIG2B may be performed, and then a plurality of bonding elements 220 are formed on the redistribution wiring layer 210 and the package structure PS is cut, thereby obtaining an electronic device ED including a chip 130 as shown in FIG10 . Please refer to FIG10 , which is a cross-sectional schematic diagram of an electronic device according to yet another embodiment of the present disclosure. As shown in FIG. 10 , the electronic device ED manufactured by the above method includes a chip 130, an insulating layer 140, and a redistribution unit 210U. The detailed structure and the materials included can refer to the above-mentioned embodiments, and will not be described in detail here. Among them, the upper surface 140a of the insulating layer 140 may have a recessed portion 140G adjacent to the chip 130. In the normal direction Z of the surface 130a of the chip 130, there may be a step difference ST3 between the portion of the upper surface 140a of the insulating layer 140 corresponding to the recessed portion 140G and the surface 130a of the chip 130. In addition, there may be a step difference ST4 between the surface 130a of the chip 130 and another portion of the upper surface 140a of the insulating layer 140.

In summary, according to the manufacturing method of the electronic device and the manufactured electronic device of the embodiment of the present disclosure, multiple chips can be aligned according to multiple alignment marks during the manufacturing process, which can improve the alignment accuracy. Moreover, the alignment marks are formed by patterning the intermediate layer on the carrier, and the process is simpler and can be easily removed, which can reduce the process cost. In addition, the step difference between the surface of the chip and the upper surface of the insulating layer can improve the adhesion between the film layers and/or can be used for alignment. According to the manufacturing method of the electronic device provided by the present disclosure, the manufactured electronic device has specific structural characteristics and can have a higher yield and/or product reliability.

The above is only an embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may be modified and varied in various ways. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

100: first carrier 102,120,302: release layer 104: transparent substrate 110: intermediate layer 112: alignment mark 112a: first sublayer 112b: second sublayer 130: chip 130a,130b: surface 132: bonding pad 134,140,214: insulating layer 140a: upper surface 140b: lower surface 140G: recessed portion 140P: raised portion 200: second carrier 210: redistribution layer 210U: redistribution unit 212,310: conductive layer 220: bonding element 300: third carrier 310P, OP: opening 312: seed layer 314: photoresist pattern 320: bonding layer CL: cutting line ED: electronic device GR: grinding equipment H1, H2: height PS: packaging structure S100, S110, S120, S130, S140, S150: step ST, ST1, ST2, ST3, ST4: step difference TH: through hole structure THa: through hole THb: side wall Z: direction θ: angle

FIG. 1 is a schematic diagram of a process of manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 2A to FIG. 2F are schematic diagrams of a process of manufacturing an electronic device according to a first embodiment of the present disclosure. FIG. 3 is a schematic diagram of a cross-section of an electronic device according to an embodiment of the present disclosure. FIG. 4 is an enlarged schematic diagram of a cross-section of an alignment mark on a carrier according to an embodiment of the present disclosure. FIG. 5A to FIG. 5B are schematic diagrams of a process of manufacturing an electronic device according to a second embodiment of the present disclosure. FIG. 6A to FIG. 6C are schematic diagrams of a process of manufacturing an electronic device according to a third embodiment of the present disclosure. FIG. 7 is a schematic diagram of a cross-section of an electronic device according to another embodiment of the present disclosure. FIG. 8A to FIG. 8D are schematic diagrams of a process of manufacturing an electronic device according to a fourth embodiment of the present disclosure. FIG. 9 is a schematic diagram of a cross-section of an electronic device according to another embodiment of the present disclosure. FIG10 is a schematic cross-sectional view of an electronic device according to another embodiment of the present disclosure.

S100,S110,S120,S130,S140,S150: Steps

Claims (10)

A method for manufacturing an electronic device, comprising: Forming an intermediate layer on a first carrier and patterning the intermediate layer to form a plurality of alignment marks; Forming a release layer on the first carrier; Placing a plurality of chips on the release layer, wherein each chip includes a bonding pad and a surface adjacent to the bonding pad; Forming an insulating layer on the release layer, the insulating layer surrounding the plurality of chips so that the insulating layer and the plurality of chips form a packaging structure; The package structure is transferred to a second carrier, so that the surface of each chip faces away from the second carrier, and an upper surface of the insulating layer exposes the surface of each chip, wherein a step is formed between the surface of each chip and at least a portion of the upper surface of the insulating layer in the normal direction of the surface of each chip; and a redistribution layer is formed on the package structure, and the redistribution layer is electrically connected to each chip through the bonding pads. A method for manufacturing an electronic device as described in claim 1, wherein the step difference range is greater than or equal to 2 microns and less than or equal to 10 microns. The method for manufacturing an electronic device as described in claim 1, wherein the step of transferring the package structure to the second carrier includes: attaching the second carrier to one side of the package structure; removing the first carrier, the release layer, and the plurality of alignment marks; and exposing the bonding pads. The method for manufacturing an electronic device as described in claim 3, wherein the upper surface of the insulating layer has a plurality of recessed portions. In the method for manufacturing an electronic device as described in claim 1, the step of forming the release layer on the first carrier is performed before the step of forming the intermediate layer. A method for manufacturing an electronic device as described in claim 5, wherein the height range of each alignment mark is greater than or equal to one third of the height of at least one chip among the multiple chips and less than or equal to one fifth of the height of the at least one chip. The manufacturing method of the electronic device as described in claim 1 further includes: forming a plurality of bonding elements on the redistribution wiring layer, wherein the plurality of bonding elements are electrically connected to the redistribution wiring layer respectively; cutting the package structure; and removing the second carrier. The method for manufacturing an electronic device as described in claim 1, wherein when forming the redistribution wiring layer, it also includes forming a through-hole structure located between two adjacent ones of the multiple chips and extending through the insulating layer, and the through-hole structure is electrically connected to the two adjacent ones of the multiple chips. An electronic device, comprising: a chip, comprising a bonding pad and a surface adjacent to the bonding pad; an insulating layer, surrounding the chip, and an upper surface of the insulating layer exposing the surface of the chip; and a redistribution unit, disposed on the chip and the insulating layer and electrically connected to the chip through the bonding pad; wherein, in a normal direction of the surface of the chip, there is a step difference between the surface of the chip and at least a portion of the upper surface of the insulating layer, and the step difference range is greater than or equal to 2 microns and less than or equal to 10 microns. An electronic device as described in claim 9, wherein the upper surface of the insulating layer has a recessed portion adjacent to the chip.

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