TW202429831A - Σ△ ad converter, sound signal processing system, ad convert method - Google Patents

Abstract

The [Sigma][Delta]AD converter of the present invention includes a first subtraction circuit that outputs a first subtraction signal obtained by subtracting a feedback signal from an input analog signal; an addition circuit that outputs the addition signal obtained by adding an integration signal obtained by integrating the first subtraction signal and a correction signal; a quantization circuit that outputs an output signal obtained by quantizing the addition signal; a DA conversion circuit that converts the quantized output signal of the quantization circuit into an analog discrete signal and supplies it to the first subtraction circuit; a second subtraction circuit that subtracts the analog discrete signal from the addition signal and outputs it as a second subtraction signal; and a delay circuit that supplies a delay signal of the filtered signal obtained by filtering the second subtraction signal to the addition circuit as a correction signal.

Description

Σ△AD converter, sound signal processing system and AD conversion method

The present invention relates to a Σ△ (delta-sigma) AD converter, a sound signal processing system and an AD conversion processing method.

In the prior art, there is a known Σ△AD converter having one or more integrators that converts an analog signal into a digital signal (see, for example, Patent Document 1, Japanese Patent Publication No. 2005-72632). It is known that the Σ△AD converter can further improve the S/N characteristics by increasing the order of the integration circuit (the number of integrators).

As mentioned above, the Σ△AD converter converts the output of the integration circuit into a digital signal by a quantization circuit. However, during the quantization process of the quantization circuit, quantization noise is generated, so a circuit is needed to reduce the noise of the output signal of the Σ△AD converter.

Therefore, the present invention is developed based on the above points, and its purpose is to reduce the quantization noise of the Σ△AD converter.

In the first aspect of the present invention, a Σ△AD converter is provided, which comprises: a first subtraction circuit, which subtracts a feedback signal from a rear section from an analog signal input from an input section and outputs the first subtraction signal; an integration circuit, which integrates the first subtraction signal and outputs the integrated signal; an addition circuit, which adds the integrated signal and a correction signal output from a rear section and outputs the added signal; a quantization circuit, which quantizes the added signal and outputs the quantized output signal from an output section to the outside; and a DA conversion circuit, which converts the output signal quantized by the quantization circuit into an analog discrete signal. , the converted analog discrete signal is supplied to the first subtraction circuit as the feedback signal; the second subtraction circuit subtracts the analog discrete signal output by the DA conversion circuit from the addition signal and outputs it as the second subtraction signal; the filter circuit filters the second subtraction signal and outputs it as the filter signal; and the delay circuit delays the filter signal and supplies the delayed signal as the correction signal to the addition circuit.

Alternatively, the filter circuit may be configured to function as a low pass filter for the quantization noise generated in the quantization circuit.

Alternatively, when quantization noise generated by the quantization circuit is _Nq and the delay of the delay circuit is Z ^-1 using a transfer function of a Z transform, the filter coefficient W of the filter circuit is set so as to subtract W×Z ^-1 × _Nq from the integrated signal output by the integration circuit.

Alternatively, when the analog signal input from the input unit is set to X, the output signal quantized by the quantization circuit is set to Y, and the integration coefficient of the integration circuit is set to V, the integration circuit outputs the integration signal (XY)V, and the addition circuit outputs the addition signal Y _A represented by the following equation: the integration signal (XY)V output by the integration circuit plus -W×Z ^-1 ×N _q .

Y _A =( X - Y ) V - WZ ^-1 N _q (1)

Alternatively, when the analog signal input from the input unit is set to X, the output signal quantized by the quantization circuit is set to Y, and the integration coefficient of the integration circuit is set to V, the output signal Y is calculated as follows.

In the second aspect of the present invention, a sound signal processing system is provided, which comprises: a sound input unit, which converts the input sound into an analog sound signal; a Σ△AD converter of the first aspect, which converts the analog sound signal converted by the sound input unit into a digital signal; and a DA conversion circuit, which converts the digital signal converted by the Σ△AD converter into an analog signal.

Alternatively, the aforementioned Σ△AD converter and the aforementioned DA conversion circuit may be integrated into one circuit device.

In the third aspect of the present invention, an AD conversion processing method is provided, which includes the following steps: a first subtraction circuit subtracts a feedback signal fed back from a rear section from an analog signal input from an input section and outputs the subtraction signal as a subtraction signal; a step of integrating the subtraction signal and outputting the subtraction signal as an integration signal; a step of adding the integration signal and a correction signal output from a rear section and outputting the addition signal as an addition signal; a step of quantizing the addition signal and outputting the quantized output signal from a The output unit outputs to the outside; the quantized output signal is converted into an analog discrete signal, and the converted analog discrete signal is supplied to the first subtraction circuit as the feedback signal; the analog discrete signal is subtracted from the addition signal to output the second subtraction signal; the second subtraction signal is filtered and output as a filtered signal; and the filtered signal is delayed, and the delayed signal is supplied to the addition circuit as the correction signal.

According to the present invention, the effect of reducing the quantization noise of the Σ△AD converter is achieved.

10: Sound input unit

20:Σ△AD converter

30:DA conversion circuit

40: Amplifier circuit

50: Sound output unit

200:Σ△AD converter

201: Input Department

202: Output department

203: 1st subtraction circuit

204: Integration circuit

205:Quantization circuit

206:DA conversion circuit

301: Addition circuit

302: Second subtraction circuit

303:Filter circuit

304: Delay circuit

S: Sound signal processing system

FIG1 shows an example of the structure of the sound signal processing system S of this embodiment.

FIG2 shows an example of the structure of a Σ△AD converter 200 of the prior art.

FIG3 shows an example of the configuration of the ΣΔ AD converter 20 of this embodiment.

FIG4(A) shows the first example of the simulation result of the digital signal output by the known Σ△AD converter 200.

FIG4(B) shows the first example of the simulation result of the digital signal output by the Σ△AD converter 20 of this embodiment.

FIG5(A) is a second example showing the simulation result of the digital signal output by the known Σ△AD converter 200.

FIG5(B) shows the second example of the simulation result of the digital signal output by the Σ△AD converter 20 of this embodiment.

FIG6(A) is a third example showing the simulation result of the digital signal output by the known Σ△AD converter 200.

FIG6(B) shows the third example of the simulation result of the digital signal output by the Σ△AD converter 20 of this embodiment.

<Configuration example of sound signal processing system S>

FIG1 shows an example of the configuration of the sound signal processing system S of this embodiment. The sound signal processing system S converts the input sound into a digital signal, converts the converted digital signal into an analog signal, and outputs it in the form of sound. The sound signal processing system S has: a sound input unit 10, a Σ△AD converter 20, a DA conversion circuit 30, an amplifier circuit 40, and a sound output unit 50.

The sound input unit 10 converts the input sound into an analog sound signal. The sound input unit 10 converts the sound transmitted in the form of air vibration into an electrical signal. The sound input unit 10 is, for example, a microphone.

The Σ△AD converter 20 converts the analog sound signal converted by the sound input unit 10 into a digital signal. The Σ△AD converter 20 outputs the converted digital signal to the DA conversion circuit 30.

The DA conversion circuit 30 converts the digital signal converted by the Σ△AD converter 20 into an analog signal, and outputs the converted analog signal to the amplifier circuit 40. The amplifier circuit 40 amplifies the analog signal converted by the DA conversion circuit 30, and outputs the amplified analog signal to the sound output unit 50.

The sound output unit 50 converts the analog signal amplified by the amplifier circuit 40 into sound and outputs it. The sound output unit 50 converts the analog signal into sound transmitted in the form of air vibration and outputs it. The sound output unit 50 is, for example, a speaker, earphone, etc.

The above-mentioned sound signal processing system S can also be equipped with a circuit for performing signal processing on the digital signal converted by the Σ△AD converter 20. The circuit for performing signal processing is, for example, a circuit for performing noise reduction, data compression, frequency characteristic change (equalizing), etc. The above-mentioned sound signal processing system S can be used for sound processing of microphones, headphones, earphones, speakers, conference systems, etc.

In addition, the ΣΔAD converter 20 of this embodiment reduces quantization noise as described later. Therefore, the sound signal processing system S does not need circuits, modules, etc. for reducing quantization noise, so the ΣΔAD converter 20 and the DA conversion circuit 30 can be integrated to reduce the cost. In order to explain the ΣΔAD converter 20 as described above, first, the ΣΔAD converter 200 of the prior art is explained.

<Configuration example of Σ△AD converter 200 of known technology>

FIG2 shows a configuration example of a known Σ△AD converter 200. In addition, for the known Σ△AD converter 200, since it is a known technology such as the aforementioned patent document 1, the detailed operation description is omitted here. The Σ△AD converter 200 has: an input unit 201, an output unit 202, a first subtraction circuit 203, an integration circuit 204, a quantization circuit 205 and a DA conversion circuit 206.

The input section 201 inputs an analog signal. In addition, the output section 202 outputs a digital signal obtained by converting the input analog signal by the Σ△AD converter 200. Here, the analog signal input from the input section 201 is set as X, and the digital signal output from the output section 202 is set as Y. The input section 201 and the output section 202 are, for example, terminals, pads, lead frames, bumps, connectors, wiring, etc. for inputting and outputting electrical signals.

The first subtraction circuit 203 subtracts the feedback signal fed back from the latter stage from the analog signal X input from the input unit 201. The feedback signal is an analog signal Y obtained by DA-converting the digital signal Y converted by the Σ△AD converter 200 as described later. The first subtraction circuit 203 is, for example, a differential amplifier circuit that amplifies the difference of the input voltage. The first subtraction circuit 203 outputs the subtracted signal as the first subtraction signal to the integration circuit 204. Here, the first subtraction signal is assumed to be X-Y.

The integration circuit 204 integrates the first subtraction signal and outputs it as an integrated signal to the quantization circuit 205. The integration circuit 204 has one or more integrators and amplifiers connected to the integrators. When the integration circuit 204 has a plurality of integrators, it further has an adder that adds the outputs of the amplifiers connected to the plurality of integrators. The integration circuit 204 shown in FIG. 2 shows an example of a three-stage integration circuit having three integrators.

Here, assuming that the outputs of the three integrators are Σ ₁ , Σ ₂ , and Σ ₃ , and the amplification levels of the amplifiers at the subsequent stages of the integrators are a ₁ , a ₂ , and a ₃ , the output of the integrator circuit 204 is (XY)V, V=a ₁ Σ ₁ +a ₂ Σ ₂ +a ₃ Σ ₃ . In addition, V is the integration coefficient of the integrator circuit 204 .

The quantization circuit 205 quantizes the integrated signal (X-Y)V output by the integration circuit 204. The quantization circuit 205 outputs a digital value representing 0 or 1, for example, based on the comparison result between the integrated signal (X-Y)V and the reference signal. The quantization circuit 205 outputs the quantized output signal as a digital signal Y from the output unit 202 to the outside.

The quantization circuit 205 generates quantization noise when performing quantization processing. Here, the quantization noise generated by the quantization circuit is set to N _q , and the digital signal Y is expressed as follows.

[Formula 1] Y = ( X - Y ) V + N _q

By transforming equation 1, the digital signal Y can be expressed as follows. The quantization circuit 205 also outputs such a digital signal Y to the DA conversion circuit 206.

The DA conversion circuit 206 converts the output signal quantized by the quantization circuit 205 into an analog discrete signal, and supplies the converted analog discrete signal as a feedback signal to the first subtraction circuit 203. The DA conversion circuit 206 is, for example, a 1-bit DA converter, and specifically indicates the feedback signal supplied to the first subtraction circuit 203. The feedback signal is, for example, +V _ref if the digital signal Y is "1", and -V _ref if the digital signal Y is "0". Here, V _ref is a predetermined reference signal.

The above Σ△AD converter 200 can shift the quantization noise to a higher frequency by increasing the number (order) of integrators in the integration circuit 204, thereby improving the conversion accuracy. However, since sound signals have a wide bandwidth, even if the Σ△AD converter 200 of the conventional technology is used, quantization noise still occurs in the audible frequency band.

Therefore, the known sound signal processing system S is further equipped with other circuits, modules, etc. for reducing the quantization noise generated in the Σ△AD converter 200. At this time, since other circuits or modules are connected between the Σ△AD converter 200 and the DA conversion circuit 30, the Σ△AD converter 200 and the DA conversion circuit 30 cannot be integrated. Therefore, the Σ△AD converter 20 of this embodiment reduces the generation of the quantization noise as described above. The following is an explanation of such a Σ△AD converter 20.

<Configuration example of Σ△AD converter 20>

FIG3 shows an example of the configuration of the Σ△AD converter 20 of the present embodiment. In the Σ△AD converter 20 shown in FIG3, the components that operate substantially the same as the Σ△AD converter 200 of the prior art shown in FIG2 are labeled with the same component symbols and repeated descriptions are omitted. The Σ△AD converter 20 is further equipped with: an addition circuit 301, a second subtraction circuit 302, a filter circuit 303, and a delay circuit 304.

The adding circuit 301 is provided between the integrating circuit 204 and the quantizing circuit 205, and adds the integrated signal outputted from the integrating circuit 204 and the correction signal outputted from the latter stage. The adding circuit 301 is, for example, an amplifier circuit that amplifies the sum of a plurality of input voltages. The adding circuit 301 outputs the addition result of the integrating signal and the correction signal as an addition signal to the quantizing circuit 205.

The second subtraction circuit 302 is connected to the output of the addition circuit 301 and the output of the DA conversion circuit 206. The second subtraction circuit 302 subtracts the analog discrete signal output by the DA conversion circuit 206 from the addition signal output by the addition circuit 301 and outputs the result as the second subtraction signal. The second subtraction circuit 302 has the same structure as the first subtraction circuit 203, for example.

The second subtraction circuit 302 subtracts the signal output from the quantization circuit 205 from the signal input to the quantization circuit 205. The absolute value of the second subtraction signal output from the second subtraction circuit 302 is almost equal to the quantization noise generated in the quantization circuit 205. Therefore, the second subtraction signal is set to _-Nq .

The filter circuit 303 is connected to the output of the second subtraction circuit 302, and filters the second subtraction signal and outputs it as a filter signal. Assuming that the filter coefficient of the filter circuit 303 is W, the filter signal is -W× _Nq . The filter circuit 303 is, for example, a digital filter that performs filtering by digitally processing the value of a discrete analog signal.

The delay circuit 304 is provided between the filter circuit 303 and the adding circuit 301. The delay circuit 304 delays the filter signal outputted from the filter circuit 303 and supplies the delayed signal to the adding circuit 301 as a correction signal. The delay circuit 304 is, for example, a circuit that delays by 1 clock.

When the delay of the delay circuit 304 is set to Z ^-1 using the transfer function of the Z transform, the addition circuit 301 subtracts W×Z ^-1 × _Nq from the integrated signal (XY)V output by the integration circuit 204 (in other words, adds -W×Z ^-1 × _Nq ). Thus, the quantization circuit 205 quantizes the added signal _YA represented by the following equation.

[Formula 3] Y _A =( X - Y ) V - WZ ^-1 N _q

The quantization circuit 205 quantizes the addition signal _YA of equation 3 while generating quantization noise, so the output signal Y is calculated as follows.

[Formula 4 _] Y = ( X _- Y ) V - WZ ^-1 Nq + Nq

In addition, the output signal Y is sorted to obtain the following formula.

As described above, the ΣΔ AD converter 20 of this embodiment calculates the quantization noise component generated in the quantization circuit 205 by subtracting the signal quantized by the quantization circuit 205 from the signal input to the quantization circuit 205. In addition, the ΣΔ AD converter 20 subtracts the calculated quantization noise component from the next signal to be input to the quantization circuit 205, thereby reducing the next quantization noise component generated in the quantization circuit 205.

As described above, the Σ△AD converter 20 feeds back a correction signal based on the component of the quantization noise previously generated in the quantization circuit 205 to the input signal of the quantization circuit 205. Here, the filter circuit 303 performs filtering processing in a manner to avoid excessive influence of feedback by the correction signal. For example, the filter circuit 303 is configured to function as a low-pass filter for the quantization noise generated in the quantization circuit 205, and the frequency characteristics of the low-pass filter are set by the filter coefficient W.

Comparing the digital signal output by the prior art ΣΔAD converter 200 represented by equation 2 with the digital signal output by the ΣΔAD converter 20 of the present embodiment represented by equation 5, it can be seen that the quantization noise _Nq is reduced by W×Z ^-1 /(1+V). Next, the result of calculating the frequency characteristics of the digital signal output by the above-mentioned ΣΔAD converter 20 by simulation is described.

<Simulation results of Σ△AD converter 20>

FIG4(A) is a first example of the simulation result of the digital signal output by the known Σ△AD converter 200. FIG4(B) is a first example of the simulation result of the digital signal output by the Σ△AD converter 20 of the present embodiment. FIG4(A) and FIG4(B) are simulation results when the frequency of the input analog signal of the sine wave is set to 1kHz and the signal strength is set to -72dB.

FIG4(A) and FIG4(B) show that the horizontal axis represents the frequency of the digital signal and the vertical axis represents the signal strength of the digital signal. By comparing FIG4(A) and FIG4(B), it can be seen that the quantization noise that can be confirmed in the digital signal output by the Σ△AD converter 200 of the prior art is reduced in the digital signal output by the Σ△AD converter 20.

FIG5(A) is a second example showing the simulation result of the digital signal output by the ΣΔAD converter 200 of the prior art. FIG5(B) is a second example showing the simulation result of the digital signal output by the ΣΔAD converter 20 of the present embodiment.

The simulation results of the second example shown in FIG. 5(A) and FIG. 5(B) show an example in which the signal strength of the input analog signal of the simulation results of the first example shown in FIG. 4(A) and FIG. 4(B) is increased to -55dB. In the simulation results of the second example, similarly, the quantization noise that can be confirmed in the digital signal output by the Σ△AD converter 200 of the prior art is reduced in the digital signal output by the Σ△AD converter 20.

FIG6(A) shows the third example of the simulation result of the digital signal output by the ΣΔAD converter 200 of the prior art. FIG6(B) shows the third example of the simulation result of the digital signal output by the ΣΔAD converter 20 of the present embodiment.

The simulation results of the third example shown in FIG. 6(A) and FIG. 6(B) show an example in which the signal strength of the input analog signal of the simulation results of the first example shown in FIG. 4(A) and FIG. 4(B) is increased to -31dB. In the simulation results of the third example, similarly, the quantization noise that can be confirmed in the digital signal output by the Σ△AD converter 200 of the prior art is reduced in the digital signal output by the Σ△AD converter 20.

As described above, according to the ΣΔAD converter 20 of this embodiment, the quantization noise generated by the quantization circuit 205 can be reduced. Thus, for example, in a system using the ΣΔAD converter 20, circuits and modules for reducing quantization noise are not required, so the ΣΔAD converter 20 can be integrated with other circuits, which can reduce costs and reduce the circuit scale.

The present invention has been described above using the implementation form, but the technical scope of the present invention is not limited to the scope described in the above implementation form, and various modifications and changes can be made within the scope of the main idea of the present invention. For example, all or part of the device can be functionally or physically dispersed and integrated in any unit. In addition, a new implementation form generated by any combination of multiple implementation forms is also included in the implementation form of the present invention. The effect of the new implementation form generated by the combination is the effect of the original implementation form.

20:Σ△AD converter

201: Input Department

202: Output department

203: 1st subtraction circuit

204: Integration circuit

205:Quantization circuit

206:DA conversion circuit

301: Addition circuit

302: Second subtraction circuit

303:Filter circuit

304: Delay circuit

Claims (8)

A Σ△AD converter having: The first subtraction circuit subtracts the feedback signal fed back from the rear section from the analog signal input from the input section and outputs the first subtraction signal; The integration circuit integrates the aforementioned first subtraction signal and outputs it as an integrated signal; The adding circuit adds the aforementioned integral signal and the correction signal output from the latter stage and outputs the added signal; The quantization circuit quantizes the aforementioned added signal and outputs the quantized output signal from the output unit to the outside; The DA conversion circuit converts the output signal quantized by the aforementioned quantization circuit into an analog discrete signal, and supplies the converted analog discrete signal as the aforementioned feedback signal to the aforementioned first subtraction circuit; The second subtraction circuit subtracts the aforementioned analog discrete signal output by the aforementioned DA conversion circuit from the aforementioned addition signal and outputs the signal as the second subtraction signal; The filter circuit filters the aforementioned second subtraction signal and outputs it as a filtered signal; and The delay circuit delays the aforementioned filter signal and supplies the delayed signal as the aforementioned correction signal to the aforementioned addition circuit. The Σ△AD converter as described in claim 1, wherein the filter circuit is constructed in such a way as to function as a low-pass filter for the quantization noise generated in the quantization circuit. A ΣΔAD converter as described in claim 2, wherein when the quantization noise generated by the quantization circuit is set to N _q and the delay of the delay circuit is set to Z ^-1 using a transfer function of a Z transform, the filter coefficient W of the filter circuit is set in such a manner that W×Z ^-1 ×N _q is subtracted from the integrated signal output by the integration circuit. The Σ△AD converter as described in claim 3, wherein when the analog signal input from the input unit is set to X, the output signal quantized by the quantization circuit is set to Y, and the integration coefficient of the integration circuit is set to V, The aforementioned integration circuit outputs the aforementioned integration signal (X-Y)V; The adding circuit ^outputs the added signal Y _A expressed by the following equation _: Y _A =( XY ) V - WZ ^-1 N _q (1). The Σ△AD converter as described in claim 3, wherein when the analog signal input from the input unit is set to X, the output signal quantized by the quantization circuit is set to Y, and the integration coefficient of the integration circuit is set to V, the output signal Y is calculated as follows,

A sound signal processing system comprises: The sound input part converts the input sound into an analog sound signal; The Σ△AD converter described in any one of claim items 1 to 5 converts the analog sound signal converted by the sound input unit into a digital signal; and The DA conversion circuit converts the digital signal converted by the aforementioned Σ△AD converter into an analog signal. The sound signal processing system as described in claim 6, wherein the aforementioned Σ△AD converter and the aforementioned DA conversion circuit are integrated into one circuit device. An AD conversion processing method includes the following steps: The first subtraction circuit subtracts the feedback signal fed back from the rear section from the analog signal input from the input section and outputs the subtraction signal as a subtraction signal; The step of integrating the aforementioned subtraction signal and outputting it as an integrated signal; The adding circuit adds the aforementioned integral signal and the correction signal output from the latter stage and outputs the added signal; The step of quantizing the aforementioned added signal and outputting the quantized output signal from the output unit to the outside; The step of converting the quantized output signal into an analog discrete signal, and supplying the converted analog discrete signal as the feedback signal to the first subtraction circuit; The step of subtracting the aforementioned analog discrete signal from the aforementioned addition signal and outputting the signal as the second subtraction signal; The step of filtering the aforementioned second subtraction signal and outputting it as a filtered signal; and The step of delaying the aforementioned filtering signal and supplying the delayed signal as the aforementioned correction signal to the aforementioned adding circuit.

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