TW202422868A - Display panel - Google Patents

Abstract

A display panel includes a bottom substrate, a LED and an upper substrate. The bottom substrate includes a dielectric layer, a first electrode pad and a second electrode pad. The first electrode pad is on the dielectric layer. The second electrode pad is on the dielectric layer and adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used to provide different electrical potentials. The LED includes a first electrode and a second electrode on opposite sides of the LED. The first electrode is electrically connected to the first electrode pad. The upper substrate includes a carrier, upper bank structures and a transparent conductive layer. The carrier has a surface facing the bottom substrate. The upper bank structures are disposed at the surface. The transparent conductive layer covers the surface of the carrier and the upper bank structures. The transparent conductive layer electrically connects the second electrode pad and the second electrode.

Description

Display Panel

Some embodiments of the present disclosure relate to a display panel.

LED displays are one of the most common displays today. Generally speaking, when manufacturing LED displays, a large number of LED chips need to be transferred to a specific substrate through a mass transfer process. Then, a transparent conductive layer is formed on the LED chip and the substrate to electrically connect the electrodes of the LED chip with the electrodes on the substrate. When the electrodes of the LED chip and the electrodes on the substrate cannot be effectively connected, the LED chip is likely to fail.

Some embodiments of the present disclosure provide a display panel, including a lower substrate, a light-emitting diode chip and an upper substrate. The lower substrate includes a dielectric layer, a first electrode pad and a second electrode pad. The first electrode pad is located on the dielectric layer. The second electrode pad is located on the dielectric layer, adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used to provide different potentials. The light-emitting diode chip includes a first electrode and a second electrode located on opposite sides, and the first electrode is electrically connected to the first electrode pad. The upper substrate is on the lower substrate and the light-emitting diode chip, and the upper substrate includes a carrier, an upper bank structure and a transparent conductive layer. The carrier has a surface facing the lower substrate. The upper bank structure is arranged on the surface. The transparent conductive layer covers the surface of the carrier and the upper bank structure, and the transparent conductive layer is electrically connected to the second electrode and the second electrode pad.

In some embodiments, a side surface of any one of the upper bank structures forms an angle with a surface of the carrier plate, and the angle is less than or equal to 50 degrees.

In some embodiments, the lower substrate further includes a plurality of lower bank structures arranged on the dielectric layer, wherein the lower bank structures are below the upper bank structures.

In some embodiments, the display panel further includes a conductive material, the vertical projection of the conductive material on the lower substrate overlaps with a plurality of vertical projections of the upper bank structure on the lower substrate, and electrically connects the transparent conductive layer and the second electrode pad.

In some embodiments, the conductive material is metal or conductive glue.

In some embodiments, the height of the conductive material is approximately equal to the height of the lower bank structure.

In some embodiments, the upper bank structure is a light absorbing material.

In some embodiments, the lower bank structure is a reflective material.

In some embodiments, the display panel further includes a reflective layer located between the upper bank structure and the transparent conductive layer.

In some embodiments, one of the upper bank structures includes an upper portion and a lower portion, the lower portion of one of the upper bank structures is adjacent to the lower bank structure, a vertical projection of the upper portion on the lower substrate overlaps with a vertical projection of the lower portion on the lower substrate, and a vertical projection of the lower portion on the lower substrate overlaps with a vertical projection of the second electrode pad on the lower substrate.

In some embodiments, one of the upper bank structures includes an upper portion and a lower portion, and a second bank structure of the upper bank structure is adjacent to the lower bank structure.

In summary, some embodiments of the present disclosure can be used to reduce the risk of a transparent conductive layer break in a display panel. Specifically, the slope of the transparent conductive layer can be reduced to reduce the risk of a transparent conductive layer break. In this way, the probability of a LED chip failing due to a transparent conductive layer break can be reduced.

In order to enable a person skilled in the art who is familiar with the technical field to which the present disclosure belongs to further understand the present disclosure, the following specifically lists the preferred embodiments of the present disclosure, and with the accompanying drawings, describes in detail the structure and intended effects of the present disclosure.

Some embodiments of the present disclosure can be used to reduce the risk of a transparent conductive layer break in a display panel. Specifically, the slope of the transparent conductive layer can be reduced to reduce the risk of a transparent conductive layer break. In this way, the probability of a light-emitting diode chip failing due to a transparent conductive layer break can be reduced.

FIG. 1 shows a cross-sectional view of a display panel 10 according to some embodiments of the present disclosure. The display panel 10 includes a lower substrate 100, a light-emitting diode chip 200, and an upper substrate 300. The lower substrate 100 includes a dielectric layer 110, a first electrode pad 120, and a second electrode pad 130. The upper substrate 300 is on the lower substrate 100 and the light-emitting diode chip 200, and includes a carrier 310 and a transparent conductive layer 330.

The lower substrate 100 may be a panel including a driving element. The lower substrate 100 includes a plurality of dielectric layers 110 stacked from bottom to top, and the dielectric layers 110 may be formed on a substrate 140. In some embodiments, as shown in FIG. 1 , the lower substrate 100 may include an active element 150, such as a thin film transistor (TFT). In other embodiments, the lower substrate 100 may also include other driving elements such as a micro chip, or the active element may not be located at the position shown in FIG. 1 , for example, the active element may be located below the substrate 140 and drive the display panel 10 in a double-sided routing manner. The first electrode pad 120 is located on the dielectric layer 110. The second electrode pad 130 is located on the dielectric layer 110, adjacent to the first electrode pad 120, and the first electrode pad 120 and the second electrode pad 130 are used to provide different potentials. In some embodiments, the lower substrate 100 includes a dielectric layer 112 between the dielectric layers 110, and the dielectric layer 112 can be made of silicon nitride. The lower substrate 100 further includes a plurality of lower bank structures 160 arranged on the dielectric layer 110.

The LED chip 200 includes a first electrode 210 and a second electrode 220 located at opposite sides, the first electrode 210 is electrically connected to the first electrode pad 120, and the first electrode 210 and the second electrode 220 have an epitaxial layer 230. Specifically, the lower substrate 100 may further include a first through-hole component 170 and a second through-hole component 180. The first through-hole component 170 and the second through-hole component 180 are located in the dielectric layer 110. The first through-hole component 170 electrically connects the active element 150 and the first electrode 210 of the LED chip 200. The second through-hole component 180 electrically connects the ground electrode (not shown) and the second electrode 220 of the LED chip 200A. It should be noted that although FIG. 1 shows that the second via members 180 on different dielectric layers 110 are not interconnected, in a cross-section different from that shown in FIG. 1 , the second via members 180 on different dielectric layers 110 are still connected to each other.

The upper substrate 300 may be a substrate that electrically connects the second electrode 220 of the LED chip 200 and the second electrode pad 130 of the lower substrate 100. The upper substrate 300 includes a carrier 310, and the carrier 310 has a surface 310S facing the lower substrate 100. A plurality of upper bank structures 320 are disposed on the surface 310S. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structures 320, and the transparent conductive layer 330 is electrically connected to the second electrode 220, and is electrically connected to the second electrode 220 through the conductive material 400. In other words, the transparent conductive layer 330 electrically connects the second electrode 220 and the second electrode pad 130.

The lower bank structure 160 of the lower substrate 100 is below the upper bank structure 320. In some embodiments, the vertical projection of the lower bank structure 160 on the lower substrate 100 overlaps the vertical projection of the upper bank structure 320 on the lower substrate 100. More specifically, the upper bank structure 320 includes a first bank structure 322 and a second bank structure 324. The vertical projection of the first bank structure 322 on the lower substrate 100 overlaps with a plurality of vertical projections of the lower bank structure 160 on the lower substrate 100, and the vertical projection of the second bank structure 324 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. The height H1 of the first bank structure 322 is the same as the height H2 of the second bank structure 324. The height H4 of the LED chip 200 is equal to the distance between the transparent conductive layer 330 and the first electrode pad 120 on the carrier 310 to ensure that the LED chip 200 can be electrically connected to the transparent conductive layer 330 and the first electrode pad 120 at the same time.

The display panel 10 further includes a conductive material 400, the vertical projection of the conductive material 400 on the lower substrate 100 overlaps with the vertical projection of the upper bank structure 320 on the lower substrate 100, and electrically connects the transparent conductive layer 330 and the second electrode pad 130. The height H5 of the conductive material 400 is equal to the distance between the transparent conductive layer 330 on the upper bank structure 320 and the second electrode pad 130, so as to ensure that the conductive material 400 can electrically connect the transparent conductive layer 330 and the second electrode pad 130 at the same time. In some embodiments, the conductive material 400 is metal or conductive glue. For example, in FIG. 1, the conductive material 400 is conductive glue, and the conductive material 400 is composed of a sealant 402 and a conductive ball 404. The conductive balls 404 are uniformly dispersed in the sealant 402. The sealant 402 may be acrylic-epoxy resin, photoinitiator, thermosetting agent, coupling agent, filler, combination thereof or the like. The conductive balls 404 may be spherical objects with a nickel layer and a gold layer sequentially coated on the surface, and may be used to electrically connect the second electrode pad 130 and the transparent conductive layer 330.

Because the height H4 of the LED chip 200 is substantially equal to the distance between the transparent conductive layer 330 and the first electrode pad 120 on the carrier 310, and the transparent conductive layer 330 is only formed on the surface of the upper bank structure 320, the slope formed by the transparent conductive layer 330 is relatively small. The electrical connection between the upper bank structure 320 and the second electrode pad 130 is through the conductive material 400, so that the transparent conductive layer 330 is less likely to break due to a too steep slope, thereby causing the LED chip 200 to fail. In some embodiments, the side surface 320S of any one of the upper bank structures 320 forms an angle a1 with the surface 310S of the carrier 310, and the angle a1 is less than or equal to 50 degrees. When the angle a1 is less than or equal to 50 degrees, the slope of the transparent conductive layer 330 is smaller, so it is less likely to break. On the contrary, when the angle a1 is greater than 50 degrees, the probability of the transparent conductive layer 330 breaking will increase.

In some embodiments, the upper bank structure 320 and the lower bank structure 160 may be made of suitable materials, and the shapes of the upper bank structure 320 and the lower bank structure 160 are designed to enhance the visual experience of the display panel 10. In some embodiments, the upper bank structure 320 and the lower bank structure 160 may be made of different materials. For example, the lower bank structure 160 may be a reflective material to reflect the light emitted to the side by the LED chip 200 upward to improve the upward light output efficiency of the display panel 10. The upper bank structure 320 may be a light-absorbing material to absorb the ambient light incident from the outside of the display panel 10 to reduce the interference caused by the ambient light to the display panel 10. In addition, the upper bank structure 320 may be an inverted trapezoid, and the lower bank structure 160 may be a regular trapezoid. For example, the width of the upper bank structure 320 gradually decreases toward the lower substrate 100, while the width of the lower bank structure 160 gradually increases toward the lower substrate 100. Therefore, the inclined side surface of the regular trapezoid of the lower bank structure 160 helps to reflect the light emitted to the side of the LED chip 200 upward. The inverted trapezoid of the upper bank structure 320 has a larger upper surface and can also more effectively absorb the ambient light incident from the outside of the display panel 10. In some embodiments, the upper bank structure 320 may be formed of a black organic material, and the optical density is not less than 1.0, for example, the optical density may be 2.0. The lower bank structure 160 may be formed of a white organic material, and the reflectivity may be not less than 50%. For example, the reflectivity may be greater than or equal to 70%. The upper bank structure 320 and the lower bank structure 160 may also be made of a compressible material. In some embodiments, the compression rate of the materials of the upper bank structure 320 and the lower bank structure 160 is between 80% and 90%. Therefore, before the upper substrate 300 and the lower substrate 100 are assembled together, the sum of the thickness of the upper bank structure 320 and the thickness of the lower bank structure 160 is greater. When the upper substrate 300 and the lower substrate 100 are assembled together, the thickness of the upper bank structure 320 and the thickness of the lower bank structure 160 are compressed, so that the transparent conductive layer 330 of the upper substrate 300 can reliably contact the conductive material 400.

The display panel 10 further includes an adhesive layer 500. The adhesive layer 500 is between the upper substrate 300 and the lower substrate 100 to bond the upper substrate 300 and the lower substrate 100 and provide support. In some embodiments, the adhesive layer 500 may be made of a sealant doped with a small amount of a support. The sealant of the adhesive layer 500 may be an acrylic-epoxy resin, a photoinitiator, a thermosetting agent, a coupling agent, a filler, a combination thereof, or the like to bond the upper substrate 300 and the lower substrate 100. The support may be an object such as fiber or a silicon ball that can provide support, and the size of the support may be selected according to the target height between the upper substrate 300 and the lower substrate 100.

FIG. 2 shows a cross-sectional view of the LED chip 200 of FIG. 1. The LED chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230, and an insulating layer 240. The first electrode 210 includes a first layer 212 and a second layer 214, and the second layer 214 is between the first layer 212 and the epitaxial layer 230. The first layer 212 and the second layer 214 of the first electrode 210 can be made of a conductor. In some embodiments, the first layer 212 can be made of nickel, tin, gold, or a combination thereof. The second layer 214 can be made of aluminum. The second electrode 220 may be made of a transparent conductive layer, such as indium tin oxide (ITO), so that when the LED chip 200 emits light upward (i.e., toward the second electrode 220 in FIG. 1 and FIG. 2), light can still penetrate the second electrode 220. The epitaxial layer 230 is between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 may become wider as it gets closer to the second electrode 220, that is, the epitaxial layer 230 may be a positive trapezoid. The epitaxial layer 230 may include an N-type semiconductor layer 232, a multiple-quantum well (MQW) layer 234, and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. The insulating layer 240 is on the sidewall of the epitaxial layer 230 and covers a portion of the second electrode 220. In some embodiments, the insulating layer 240 may be an oxide layer.

FIG. 3A shows a bottom view of the upper substrate 300 of FIG. 1. FIG. 3B shows a top view of the lower substrate 100 of FIG. 1. In FIG. 3A, the upper bank structure 320 of the upper substrate 300 is arranged on the surface 310S of the carrier 310 along the first direction D1. A plurality of upper bank structures 320 (for example but not limited to 3) can be formed into a unit, and there is a larger space between each unit of upper bank structures 320. The larger space is used to accommodate the LED chip 200. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structure 320.

In FIG. 3B , the lower bank structures 160 of the lower substrate 100 are arranged on the dielectric layer 110 along the first direction D1, and the distance between each lower bank structure 160 is substantially the same. Each lower bank structure 160 may correspond to one of the upper bank structures 320. The LED chip 200 may be located between two adjacent lower bank structures 160, and the LED chip 200 may be accommodated in the space between the upper bank structures 320. In some embodiments, the LED chip 200 may include LED chips 200R, 200B, and 200G that emit light of different colors. The LED chips 200R, 200B, and 200G may also be arranged along the first direction D1 and each located between two adjacent lower bank structures 160. The conductive material 400 may also be located between two adjacent lower bank structures 160, and the conductive material 400 corresponds to one of the upper bank structures 320. The adhesive layer 500 is located on the periphery of the lower substrate 100, and thus can be used to bond the lower substrate 100 and the upper substrate 300.

4 to 7 are cross-sectional views showing the process of manufacturing the display panel 10. In FIG. 4 , a lower substrate 100 ′ is provided.

In FIG. 5 , a lower bank structure 160 is formed on the lower substrate 100′ to form the lower substrate 100, and the lower bank structure 160 does not cover the first electrode pad 120 and the second electrode pad 130. The relevant details of the lower substrate 100 are as described in FIG. 1 , and thus will not be repeated here.

In FIG. 6 , the LED chip 200 is transferred onto the first electrode pad 120 , so that the first electrode pad 120 of the lower substrate 100 is connected to the first electrode 210 of the LED chip 200 .

In FIG. 7 , a conductive material 400 is formed on the second electrode pad 130 of the lower substrate 100 and an adhesive layer 500 is formed on the periphery of the lower substrate 100 , and then the upper substrate 300 is placed on the lower substrate 100 , so that the second electrode pad 130 of the lower substrate 100 is connected to the second electrode 220 of the LED chip 200 through the conductive material 400 and the transparent conductive layer 330 to form a display panel 10 . Since the transparent conductive layer 330 has been formed on the upper substrate 300 in advance, when the upper substrate 300 is directly placed on the lower substrate 100, the second electrode pad 130 and the second electrode 220 can be connected at the same time without forming additional materials for electrical connection around the LED chip 200 to avoid the LED chip 200 falling off due to the formation of additional materials.

FIG. 8 shows a cross-sectional view of a display panel 10A of other embodiments of the present disclosure. The display panel 10A is similar to the display panel 10 of FIG. 1, and the difference between the two is that the structure of the LED chip 200 of the display panel 10A is different from the structure of the LED chip 200 of the display panel 10, the position of the transparent conductive layer 330 is different from the position of the conductive material 400. Specifically, the first electrode 210 of the LED chip 200 of the display panel 10A of FIG. 8 is electrically connected to the first electrode pad 120 through the transparent conductive layer 330, and the second electrode 220 of the LED chip 200 of the display panel 10A directly contacts and is electrically connected to the second electrode pad 130. The first electrode 210 of the LED chip 200 of the display panel 10 of FIG. 1 directly contacts and is electrically connected to the first electrode pad 120, and the second electrode 220 of the LED chip 200 of the display panel 10A is electrically connected to the second electrode pad 130 via the transparent conductive layer 330. In addition, the vertical projection of the second bank structure 324 of the upper bank structure 320 of the display panel 10A of FIG. 8 on the lower substrate 100 overlaps with the vertical projection of the first electrode pad 120 on the lower substrate 100, and the vertical projection of the second bank structure 324 of the upper bank structure 320 of the display panel 10 of FIG. 1 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. In some embodiments, at least one upper bank structure 320 and a lower bank structure 160 are in direct contact.

FIG. 9 shows a cross-sectional view of the LED chip 200 of FIG. 8. The LED chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230, and an insulating layer 240. The first electrode 210 can be made of a transparent conductive layer, such as indium tin oxide (ITO), so that when the LED chip 200 emits light upward (i.e., toward the direction of the first electrode 210 in FIG. 8 and FIG. 9), light can still penetrate the first electrode 210. The second electrode 220 includes a first layer 222 and a second layer 224, and the second layer 224 is between the first layer 222 and the epitaxial layer 230. The first layer 222 and the second layer 224 of the second electrode 220 may be made of a conductor. In some embodiments, the first layer 222 may be made of nickel, tin, gold or a combination thereof. The second layer 224 may be made of aluminum. The epitaxial layer 230 is between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 may be wider as it is closer to the first electrode 210, that is, the epitaxial layer 230 may be an inverted trapezoid. The epitaxial layer 230 may include an N-type semiconductor layer 232, a Multiple-Quantum Well (MQW) layer 234 and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. The insulating layer 240 is on the sidewall of the epitaxial layer 230 and covers a portion of the first electrode 210. In some embodiments, the insulating layer 240 may be an oxide layer.

FIG. 10A is a bottom view of the upper substrate 300 of FIG. 8 . FIG. 10B is a top view of the lower substrate 100 of FIG. 8 . In FIG. 10A , the upper bank structure 320 of the upper substrate 300 is arranged on the surface 310S of the carrier 310 along the first direction D1. A plurality of upper bank structures 320 (for example but not limited to 3) can be formed into a unit, and there is a larger space between each unit of upper bank structures 320. The larger space is used to accommodate the LED chip 200. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structure 320. Different from the upper substrate 300 in FIG. 3A , the transparent conductive layer 330 of the upper substrate 300 in FIG. 3A is responsible for connecting the second electrode 220 of the LED chip 200 to the second electrode pad 130 (ie, the ground electrode), so the transparent conductive layer 330 can cover the entire upper bank structure 320 . On the other hand, the transparent conductive layer 330 of the upper substrate 300 of FIG. 10A is responsible for connecting the first electrode 210 of the LED chip 200 to the first electrode pad 120 and the active element 150, so the upper substrate 300 includes a plurality of transparent conductive layers 330, each of which covers a portion of the upper bank structure 320 and the space for accommodating the LED chip 200. The transparent conductive layer 330 may not cover a portion of the upper bank structure 320.

In FIG. 10B , the lower bank structures 160 of the lower substrate 100 are arranged on the dielectric layer 110 along the first direction D1, and the distance between each lower bank structure 160 is substantially the same. Each lower bank structure 160 may correspond to one of the upper bank structures 320. The LED chip 200 may be located between two adjacent lower bank structures 160, and the LED chip 200 may be accommodated in the space between the upper bank structures 320 and contact the transparent conductive layer 330. In some embodiments, the LED chip 200 may include LED chips 200R, 200B, and 200G that emit light of different colors. The LED chips 200R, 200B, and 200G may also be arranged along the first direction D1 and each located between two adjacent lower bank structures 160. The conductive material 400 may also be located between two adjacent lower bank structures 160, and the conductive material 400 corresponds to one of the upper bank structures 320. The adhesive layer 500 is located on the periphery of the lower substrate 100, and thus can be used to bond the lower substrate 100 and the upper substrate 300.

FIG. 11 shows a cross-sectional view of a display panel 10B according to another embodiment of the present disclosure. The display panel 10B is similar to the display panel 10 of FIG. 1 , and the difference between the two is that the conductive material 400 of the display panel 10B of FIG. 11 is metal, while the conductive material 400 of the display panel 10 of FIG. 1 is conductive glue.

FIG. 12 shows a cross-sectional view of a display panel 10C according to another embodiment of the present disclosure. The display panel 10C is similar to the display panel 10 of FIG. 1 , and the difference between the two is that one of the upper bank structures 320 of the display panel 10B of FIG. 11 includes an upper portion 326 and a lower portion 328, and the lower portion 328 of the upper bank structure 320 is adjacent to the lower bank structure 160. The vertical projection of the upper portion 326 on the lower substrate 100 overlaps with the vertical projection of the lower portion 328 on the lower substrate 100, and the vertical projection of the lower portion 328 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. The side surface 326S of the upper portion 326 of the upper bank structure 320 and the side surface 328S of the lower portion 328 of the upper bank structure 320 are not connected to each other, and the transparent conductive layer 330 covers the upper portion 326 and the lower portion 328 of the upper bank structure 320. The side surface 326S of the upper portion 326 of the upper bank structure 320 and the surface 310S of the carrier 310 form an angle a2, and the side surface 328S of the lower portion 328 of the upper bank structure 320 and the surface 310S of the carrier 310 form an angle a3, and the angles a2 and a3 are less than or equal to 50 degrees. In some embodiments, a height H6 of the lower surface of the lower portion 328 relative to the lower substrate 100 is less than a height H7 of the lower surface of the upper portion 326 relative to the lower substrate 100, so that the lower portion 328 can be closer to the second electrode pad 130, so that the electrical connection between the transparent conductive layer 330 and the second electrode pad 130 can be completed without providing the conductive material 400.

FIG. 13 shows a cross-sectional view of a display panel 10D according to other embodiments of the present disclosure. The display panel 10D is similar to the display panel 10 of FIG. 1 , and the difference between the two is that the display panel 10D further includes a reflective layer 340 located between the upper bank structure 320 and the transparent conductive layer 330. The reflective layer 340 can be used to reflect the light emitted to the side by the LED chip 200 upward, further improving the upward light extraction efficiency of the display panel 10. In some embodiments, the reflective layer 340 can be made of metal.

In summary, some embodiments of the present disclosure can reduce the risk of a transparent conductive layer breaking in a display panel. For example, the display panel may include an upper substrate and a lower substrate. The transparent conductive layer may be formed only on the upper bank structure of the upper substrate and electrically connected to the lower substrate through an additional conductive material. Therefore, the angle between the side wall of the upper bank structure of the upper substrate and the carrier surface of the upper substrate can be designed to be smaller to reduce the risk of a transparent conductive layer breaking. In this way, the light-emitting diode chip in the display panel is not easily caused to fail due to a transparent conductive layer breaking.

Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person having ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

10: Display panel 10A: Display panel 10B: Display panel 10C: Display panel 100: Lower substrate 100’: Lower substrate 110: Dielectric layer 112: Dielectric layer 120: First electrode pad 130: Second electrode pad 140: Substrate 150: Active element 160: Lower bank structure 170: First through-hole component 180: Second through-hole component 200: LED chip 200B: LED chip 200G: LED chip 200R: LED chip 210: First electrode 212: First layer 214: Second layer 220: Second electrode 222: First layer 224: Second layer 230: Epitaxial layer 232: N-type semiconductor layer 234: Multiple quantum well layer 236: P-type semiconductor layer 240: Insulating layer 300: Upper substrate 310: Carrier 310S: Surface 320: Upper bank structure 320S: Side surface 322: First bank structure 324: Second bank structure 326: Upper part 326S: Side surface 328: Lower part 328S: Side surface 330: Transparent conductive layer 340: Reflective layer 400: Conductive material 402: Sealant 404: Conductive ball 500: Adhesive layer a1: Angle a2: Angle a3: Angle D1: First direction H1: Height H2: Height H4: Height H5: Height H6: Height H7: Height

FIG. 1 shows a cross-sectional view of a display panel of some embodiments of the present disclosure. FIG. 2 shows a cross-sectional view of a light-emitting diode crystal of FIG. 1. FIG. 3A shows a bottom view of an upper substrate of FIG. 1. FIG. 3B shows a top view of a lower substrate of FIG. 1. FIG. 4 to FIG. 7 show cross-sectional views of a process for manufacturing a display panel. FIG. 8 shows a cross-sectional view of a display panel of other embodiments of the present disclosure. FIG. 9 shows a cross-sectional view of a light-emitting diode crystal of FIG. 8. FIG. 10A shows a bottom view of an upper substrate of FIG. 8. FIG. 10B shows a top view of a lower substrate of FIG. 8. FIG. 11 shows a cross-sectional view of a display panel of other embodiments of the present disclosure. FIG. 12 shows a cross-sectional view of a display panel of other embodiments of the present disclosure. FIG. 13 shows a cross-sectional view of a display panel of other embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

10: Display panel

100: Lower substrate

110: Dielectric layer

112: Dielectric layer

120: first electrode pad

130: Second electrode pad

140: Substrate

150: Active components

160: Lower embankment structure

170: First through-hole component

180: Second through-hole component

200: LED chip

210: First electrode

220: Second electrode

230: Epitaxial layer

300: Upper substrate

310: Carrier board

310S: Surface

320: Upper embankment structure

322: First embankment structure

324: Second embankment structure

320S: Side

330: Transparent conductive layer

400: Conductive material

402: Sealant

404: Conductive ball

500: Adhesive layer

a1: Angle

D1: First direction

H1: Height

H2: Height

H4: Height

H5: Height

Claims (10)

A display panel comprises: A lower substrate, the lower substrate comprises: A dielectric layer; A first electrode pad, located on the dielectric layer; and A second electrode pad, located on the dielectric layer, adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used to provide different potentials; A light-emitting diode chip, the light-emitting diode chip comprises a first electrode and a second electrode located on opposite sides, the first electrode is electrically connected to the first electrode pad; and An upper substrate, on the lower substrate and the light-emitting diode chip, the upper substrate comprises: A carrier having a surface facing the lower substrate; A plurality of upper bank structures, arranged on the surface; and A transparent conductive layer covers the surface of the carrier and the upper bank structures, and the transparent conductive layer electrically connects the second electrode and the second electrode pad. A display panel as described in claim 1, wherein a side surface of any one of the upper bank structures forms an angle with the surface of the carrier, and the angle is less than or equal to 50 degrees. The display panel as described in claim 1 further includes a conductive material, a vertical projection of the conductive material on the lower substrate overlaps with multiple vertical projections of the upper bank structures on the lower substrate, and electrically connects the transparent conductive layer and the second electrode pad. A display panel as described in claim 3, wherein the conductive material is metal or conductive glue. A display panel as described in claim 3, wherein the lower substrate further comprises a plurality of lower bank structures arranged on the dielectric layer, the lower bank structures being below the upper bank structures. A display panel as described in claim 5, wherein a height of the conductive material is approximately equal to a plurality of heights of the lower bank structures. A display panel as described in claim 5, wherein the lower embankment structures are made of reflective material. A display panel as described in claim 5, wherein one of the upper bank structures comprises an upper portion and a lower portion, the lower portion of one of the upper bank structures is adjacent to the lower bank structures, a vertical projection of the upper portion on the lower substrate overlaps with a vertical projection of the lower portion on the lower substrate, and the vertical projection of the lower portion on the lower substrate overlaps with a vertical projection of the second electrode pad on the lower substrate. A display panel as described in claim 1, wherein the upper bank structures are light-absorbing materials. The display panel as described in claim 1 further includes a reflective layer located between the upper bank structures and the transparent conductive layer.

Images