TW202333248A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Description

Semiconductor packaging and manufacturing method thereof

The present invention relates to semiconductor packages and methods of manufacturing the same. Cross-Reference / Incorporation by Reference of Related Applications

This application is a continuation-in-part of U.S. Patent Application No. 15/871,617 titled "SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF" filed on January 15, 2018. U.S. Patent Application No. 15/871,617 was filed on May 8, 2016. A continuation-in-part of U.S. Patent Application No. 15/149,144 titled "SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF," which is now U.S. Patent No. 9,935,083, was filed by reference and claimed in November 2015 The priority of Korean patent application No. 10-2015-0159059, titled "SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME", submitted on the 12th, and claiming the rights and interests of the Korean patent application, the entire content of which is incorporated herein by reference.

Current semiconductor packages and methods of forming semiconductor packages are inadequate, resulting in, for example, excessive costs, reduced reliability, inappropriate shielding, too large package sizes, etc. Other limitations and disadvantages of known and conventional methods will become apparent to those skilled in the art by comparing them with the present disclosure as set forth in the remainder of this application with reference to the accompanying drawings.

Various aspects of the present disclosure provide semiconductor packages and methods of manufacturing semiconductor packages. By way of non-limiting example, aspects of the present disclosure provide semiconductor packages and methods of fabrication that include shielding on multiple sides thereof.

The following discussion presents various aspects of the invention by providing examples. Such examples are non-limiting, and therefore the scope of various aspects of the present disclosure should not necessarily be limited by any specific characteristics of the examples provided. In the following discussion, the terms "for example," "for example," and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "for example and without limitation" and the like.

As used herein, "and/or" refers to any one or more items in a list connected by "and/or". As an example, "x and/or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y and/or z" refers to the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), Any element in (x, y, z)}. In other words, "x, y and/or z" means "one or more of x, y and z".

The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprises," "having," and/or "having," when used in this specification, designate the presence of stated features, integers, steps, operations, elements, and/or elements , but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component, element, region, layer and/or section from another. Thus, for example, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the present disclosure. Similarly, spatial terms such as "upper," "below," "side," and the like may be used to distinguish one element from another element in a relative fashion. However, it should be understood that the components may be oriented differently, for example the semiconductor device may be rotated sideways such that its "top" surface faces horizontally and its "side" surfaces face vertically, without departing from the teachings of the present disclosure.

In the drawings, the thickness of layers, regions and/or features may be exaggerated for clarity. Therefore, the scope of the present disclosure should not be limited by this thickness or size. Additionally, in the drawings, like reference numerals refer to like elements herein. A component with an apostrophe (') component symbol may be similar to the component with the corresponding component symbol without the apostrophe.

It will also be understood that when element A is referred to as being "connected to" or "coupled to" element B, element A can be directly connected to element B or indirectly connected to element B (e.g., intervening element C (and/or other element) can be between element A and element B).

Certain embodiments of the present disclosure relate to semiconductor packages and methods of fabricating the same.

Various electronic devices for exchanging signals and multiple semiconductor packages manufactured in various structures are integrated in various electronic systems, so electromagnetic interference (EMI) is inevitably generated when the semiconductor packages and electronic devices are electrically operated.

EMI can generally be defined as the combined radiation of electric and magnetic fields. EMI can be generated by electric fields created by current flowing in conductive materials and magnetic fields.

If EMI is generated from semiconductor packages and electronic devices densely packed on the motherboard, other adjacent semiconductor packages may be directly or indirectly affected by EMI and may be damaged.

Aspects of the present disclosure provide a semiconductor package and a manufacturing method thereof that can prevent warpage by forming molds on both surfaces of a substrate and can prevent EMI shielding by forming an EMI shielding layer covering the mold and the substrate. Shielded from electromagnetic interference (EMI).

According to aspects of the present disclosure, a semiconductor package is provided, which includes: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; a first molding formed on the first surface to cover the first electronic device; a second molding formed to cover the second surface; a plurality of first conductive bumps formed on the second on the surface and electrically connected to the substrate and through the second molding; an electromagnetic interference (EMI) shielding layer formed around the surface of the substrate, the first molding, and the second molding to communicate with the first conductive bump spaced apart; a plurality of second conductive bumps are formed on one surface of the second molded object to be electrically connected to the plurality of first conductive bumps respectively.

According to another aspect of the present disclosure, a method of manufacturing a semiconductor package is provided. The semiconductor package includes: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface. on a surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate. The method includes: forming a first molding on the first surface to cover the first The electronic device forms a second molded object on the second surface to cover the first conductive bumps, grinds the second molded object to expose the plurality of first conductive bumps to the outside, and forms a plurality of second conductive bumps, They are electrically connected to the exposed plurality of first conductive bumps respectively, a clamp is placed under the second molding to surround the plurality of second conductive bumps, and an EMI shielding layer is formed to cover the substrate, the first molding and the third The surface of the second molded object is exposed to the outside via the clamp.

According to another aspect of the present disclosure, a method of manufacturing a semiconductor package is provided. The semiconductor package includes: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface. on a surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate. The method includes: forming a first molding on the first surface to cover the first electronic device and forming a second molded object on the second surface to cover the first conductive bumps, grinding the second molded object to expose the plurality of first conductive bumps to the outside, forming an EMI shielding layer to completely cover the substrate, On the surfaces of the first molded object and the second molded object, a plurality of exposure holes are formed in the EMI shielding layer to expose a plurality of first conductive bumps to the outside, and a plurality of second conductive bumps are formed through which the The plurality of exposed holes are electrically connected to the exposed plurality of first conductive bumps.

In one example, a manufacturing method may include providing a substrate, including: a substrate top surface having a substrate top first liner and a substrate top second liner; a substrate bottom surface having a substrate bottom first liner and the substrate a bottom second pad; and a substrate lateral surface. The method may also include attaching a first electronic device to a top surface of the substrate, the first electronic device being coupled to a first pad on top of the substrate and including: a first device first surface facing the top surface of the substrate; a lateral surface; and a first device second surface facing away from the substrate top surface. The method may also include coupling the first passive member to a second pad on top of the substrate, and applying a first encapsulant to encapsulate the top surface of the substrate, the first passive member, and the first electronic device, wherein the first encapsulant There is a first capsule top surface and a first capsule lateral surface. The method may also include attaching a second electronic device to the substrate bottom surface, the second electronic device being coupled to the substrate bottom first pad and including: a second device first surface facing the substrate bottom surface; a second device a lateral surface; and a second device second surface facing away from the substrate bottom surface. The method may also include providing a first external interconnect coupled to a second pad on the bottom of the substrate, and applying a second encapsulant to encapsulate the bottom surface of the substrate and the second electronic device, the second encapsulation comprising a second Transverse surface of the capsule. In one example, the method may further include a first electromagnetic interference (EMI) shield as a stack surrounding at least: a first encapsulation top surface, a first encapsulation lateral surface, and a substrate lateral surface, wherein the An EMI shield is separated from external interconnections. In the same or another example, the method may also include applying electromagnetic interference (EMI) shielding around the perimeter of the second device, in contact with the second encapsulation, and excluding sheet metal.

In one example, a semiconductor package may include a substrate having: a top surface of the substrate having a first pad on the top of the substrate and a second pad on the top of the substrate; and a bottom surface of the substrate having a first pad on the bottom of the substrate and a third pad on the bottom of the substrate. two pads; and the lateral surface of the substrate. The package may also include a first electronic device on a top surface of the substrate and coupled to a first pad on the top of the substrate, the first electronic device including: a first device first surface facing the top surface of the substrate; the first device laterally surface; and a second surface of the first device facing away from the top surface of the substrate. The package may also include a first passive member coupled to a second pad on top of the substrate and a first encapsulant encapsulating a top surface of the substrate, the passive member, and the first electronic device, the first encapsulation having a first encapsulant the top surface and the first encapsulation lateral surface. The package may also include a second electronic device on the substrate bottom surface and coupled to the substrate bottom first pad, the second electronic device including: a second device first surface facing the substrate bottom surface; the second device laterally surface; and a second device second surface facing away from the substrate bottom surface. The package may also include a first external interconnect coupled to a second pad on the bottom of the substrate and including a first external interconnect height and a second encapsulate encapsulating the bottom surface of the substrate and the second electronic device, the second encapsulation Included is a second capsule lateral surface and a second capsule height, wherein the first external interconnection height projects further than the second capsule height. The package may also include a first electromagnetic interference (EMI) shield surrounding at least: a first encapsulation top surface, a first encapsulation lateral surface, and a substrate lateral surface, wherein the first EMI shield is spaced from external interconnects.

In one example, a manufacturing method may include: providing a substrate having: a top surface of the substrate including a first liner on top of the substrate and a second liner on top of the substrate; a bottom surface of the substrate including a third liner on top of the substrate; an interconnect pad; and a substrate lateral side; providing a first device on a top surface of the substrate and coupled to the top first pad of the substrate, the first device comprising: a first device bottom surface facing the top of the substrate surface; a first device lateral surface; and a first device top surface facing away from the substrate top surface; providing a second device member coupled to a second pad on top of the substrate; providing a first encapsulation that encapsulates the top of the substrate a surface, a first device and a second device, the first capsule having a first capsule top surface and a first capsule lateral surface; attaching a third device to a third liner of the substrate on the bottom surface of the substrate, The third device includes: a third device top surface facing the substrate bottom surface; a third device lateral surface; and a third device bottom surface facing away from the substrate bottom surface; providing a first interconnect on the substrate bottom surface on and coupled to the substrate interconnect pad, a first interconnect including an interconnect protruding section and providing an external interface to the semiconductor package; applying a second encapsulant that encapsulates the substrate bottom surface, at least a portion of the third device, and the An interconnection, the second capsule includes a second capsule bottom surface and a second capsule lateral surface; the interconnection protruding section protrudes through the second capsule bottom surface; the first device, the second device, or the third device At least one of the three devices is an electronic device; and at least one of the first device, the second device, or the third device is a passive component.

In an example, a semiconductor package may include: a substrate including: a top surface of the substrate including a first pad on the top of the substrate and a second pad on the top of the substrate; a bottom surface of the substrate including a third pad on the top of the substrate; an interconnect pad; and a substrate lateral surface; a first device on a top side of the substrate and coupled to the substrate top first pad, the first device including: a first device bottom surface facing the substrate top surface; a device lateral side; and a first device top surface facing away from the substrate top surface; a second device member coupled to a second pad on top of the substrate; a first encapsulation encapsulating the substrate top surface, the first device and a second device, a first capsule having a first capsule top surface and a first capsule lateral surface; a third device on a bottom surface of the substrate and coupled to a third pad of the substrate, the third device Comprising: a third device top surface facing the substrate bottom surface; a third device lateral surface; and a third device bottom surface facing away from the substrate bottom surface; a first interconnect on the substrate bottom surface and coupled to the substrate an interconnect pad, a first interconnect including an interconnect protruding section and providing an external interface to the semiconductor package; a second encapsulant encapsulating a substrate bottom surface, at least a portion of the third device, and the first interconnect, the second encapsulation The capsule includes a second capsule bottom surface and a second capsule lateral surface; a first electromagnetic interference (EMI) shield surrounding at least the first capsule top surface, the first capsule lateral surface and the substrate lateral surface ; wherein the third device bottom surface is exposed from the second encapsulation; the interconnection protruding section protrudes through the second encapsulation bottom surface; and at least one of the first device, the second device, or the third device is an electronic device; and at least one of the first device, the second device, or the third device is a passive component.

In one example, a method may include providing an upper device attached to a substrate, the substrate having a top side of the substrate to which the upper device is attached, a lateral surface of the substrate, and a bottom side of the substrate opposite the top side of the substrate; the upper device having an attachment to the upper device bottom side of the substrate top side, the upper device lateral surface, and the upper device top side opposite the upper device bottom side; providing a first encapsulation that encapsulates the substrate top side and the upper device top side; providing attachment to an underlying device on a bottom side of a substrate, the underlying device including an underlying device top side having a bump coupled to a bottom surface of the substrate, an underlying device lateral surface, and an underlying device bottom side opposite the bottom side of the substrate; providing a first interconnect attached to the underside of the substrate and laterally displaced from the underlying device; providing a second encapsulation encapsulating the underside of the substrate, the underlying device, and the first interconnect; and providing a first electromagnetic interference (EMI) shield surrounding the first encapsulation at least a portion of the top surface of the object and a portion of the lateral surface of the first enclosure, wherein the bottom surface of the lower device is exposed from the second enclosure; the lateral surface of the upper device is vertically larger than the lateral surface of the lower device; the upper device or the lower device At least one is an electronic device; and at least one of the upper device or the lower device is a passive component.

As described above, in the semiconductor package and its manufacturing method according to the present disclosure, warpage can be prevented by forming moldings on both surfaces of the substrate, and the EMI shielding layer can be formed to cover the moldings and the substrate EMI shielding layer to shield electromagnetic interference (EMI).

Other embodiments, features, and advantages of the present disclosure, as well as the structure and operation of various embodiments of the present disclosure, are described in detail below with reference to the accompanying drawings.

Referring to FIG. 1 , a cross-sectional view is shown illustrating a semiconductor package in accordance with an embodiment of the present disclosure.

As shown in FIG. 1 , the semiconductor package 100 includes a substrate 110 , a first electronic device 120 , a second electronic device 130 , a first molding 140 , a second molding 150 , a first conductive bump 160 , a second conductive bump 160 . Bumps 170 and electromagnetic interference (EMI) shielding 180 .

The substrate 110 is formed from a panel having a first surface 110a and a second surface 110b opposite the first surface 110a. Here, the first surface 110a of the substrate 110 may be a top surface, and the second surface 110b may be a bottom surface, or vice versa. The substrate 110 includes a plurality of first line patterns 111 formed on the first surface 110a and a plurality of second line patterns 112 formed on the second surface 110b. In addition, the substrate 110 may further include a plurality of conductive patterns 113 that electrically connect the first line pattern 111 formed on the first surface 110a of the substrate 110 and the second line pattern 112 formed on the second surface 110b. The conductive pattern 113 may be configured to penetrate between the first surface 110 a and the second surface 110 b of the substrate 110 or partially penetrate to connect a plurality of line patterns formed from a plurality of layers. That is, in the case where the substrate 110 is a single layer, the conductive pattern 113 may directly connect the first line pattern 111 and the second line pattern 112, or an additional line pattern may be used to connect the first line pattern 111 and the second line pattern 112. Pattern 112 connection. That is to say, the first line pattern 111 , the second line pattern 112 and the conductive pattern 113 of the substrate 110 may be implemented in various structures and types, but aspects of the present disclosure are not limited thereto.

The first electronic device 120 is mounted on the first surface 110 a of the substrate 110 to be electrically connected to the first line pattern 111 of the substrate 110 . The first electronic device 120 may include a semiconductor die 121 and a passive member 122, and may be modified in various ways according to the type of the semiconductor package 100, but aspects of the present disclosure are not limited thereto. In the following description, the first electronic device 120 including two semiconductor dies 121 and two passive members 122 will be described by way of example. In addition, the semiconductor die 121 is formed in a flip-chip type, and may be mounted such that the conductive bumps of the semiconductor die 121 are soldered to the first line patterns 111 of the substrate 110 . The semiconductor die 121 may include bonding pads and may be connected to the first line pattern 111 through wire bonding. However, the present disclosure does not limit the connection relationship between the semiconductor die 121 and the first line pattern 111 to the connection relationship disclosed herein.

The second electronic device 130 is mounted on the second surface 110 b of the substrate 110 to be electrically connected to the second line pattern 112 formed on the substrate 110 . A second electronic device 130 composed of a single semiconductor die is illustrated. However, the second electronic device 130 may be composed of a plurality of semiconductor dies, or may further include passive components, but aspects of the present disclosure are not limited thereto.

The first molding 140 may be formed on the first surface 110 a of the substrate 110 to cover the first electronic device 120 mounted on the first surface 110 a of the substrate 110 . The first molded object 140 may be made of a general molding compound resin, such as epoxy resin, but the scope of the present disclosure is not limited thereto. The first molding 140 can protect the first electronic device 120 from the external environment.

The second molding 150 may be formed on the second surface 110b of the substrate 110 to cover the second electronic device 130 mounted on the second surface 110b of the substrate 110. The second molding 150 exposes the first conductive bump 160 formed on the second surface 110 b of the substrate 110 to the outside while completely covering the second electronic device 130 . The second molding 150 and the first conductive bump 160 may have the same height. The second molded object 150 and the first molded object 140 may be made of the same material. The second molding 150 can protect the second electronic device 130 from the external environment.

The first conductive bumps 160 may include a plurality of first conductive bumps formed on the second surface 110 b of the substrate 110 to be electrically connected to the second line pattern 112 formed on the substrate 110 . The first conductive bump 160 is configured such that its side portion is surrounded by the second molding 150 and a portion of its bottom surface is exposed to the outside through the second molding 150 . The exposed first conductive bump 160 is electrically connected to the second conductive bump 170 . That is, the first conductive bump 160 electrically connects the second conductive bump 170 and the second line pattern 112 formed on the substrate 110 . The first conductive bump 160 may include conductive pillars, copper pillars, conductive balls, or copper balls, but aspects of the present disclosure are not limited thereto.

The second conductive bump 170 may be formed on the bottom surface of the second molded object 150 to be electrically connected to the first conductive bump 160 exposed to the outside through the second molded object 150 . In the case where the semiconductor package 100 is mounted on an external device such as a motherboard, the second conductive bump 170 may be used to electrically connect the semiconductor package 100 to the external device.

The EMI shielding layer 180 may be formed to a predetermined thickness sufficient to completely cover the semiconductor package 100 except for the bottom surface of the second molded object 150 . That is, the EMI shielding layer 180 is formed to cover the top surface and four side surfaces of all the semiconductor packages 100 . In addition, the EMI shielding layer 180 may be made of a conductive material and may be electrically connected to a ground of the semiconductor package 100 or an external ground. The EMI shielding layer 180 may shield EMI induced to (or generated by) the semiconductor package 100 . Furthermore, the semiconductor package 100 may include first and second moldings 140 and 150 to cover both the first and second surfaces 110a and 110b of the substrate 110, thereby preventing the semiconductor package 100 from warping, which may occur only in This occurs when a molded object is formed on one surface of the substrate 110 .

Referring to FIG. 2 , a flow chart illustrating a method of manufacturing the semiconductor package shown in FIG. 1 is shown. As shown in FIG. 2 , the method of manufacturing the semiconductor package 100 ( S10 ) includes forming a molded object ( S11 ), grinding a second molded object ( S12 ), forming a second conductive bump ( S13 ), and placing a jig ( S14 ). and forming an EMI shielding layer (S15).

Referring to FIGS. 3A-3E , cross-sectional views of various steps of a method for manufacturing the semiconductor package shown in FIG. 2 are shown.

First, before forming the molded object (S11), the first electronic device 120 is mounted on the first surface 110a of the substrate 110 to be electrically connected to the first line pattern 111, and the second electronic device 130 is mounted on the first surface 110a of the substrate 110. The second surface 110 b is electrically connected to the second line pattern 112 , and a plurality of first conductive bumps 160 are then formed on the second surface 110 b of the substrate 110 to be electrically connected to the second line pattern 112 .

As shown in FIG. 3A , in the formation of the molded object (S11), the first molded object 140 is formed to cover the first surface 110a of the substrate 110 and the first electronic device 120, and the second molded object 150 is formed to cover the first surface 110a of the substrate 110 and the first electronic device 120. The second surface 110 b of the substrate 110 , the second electronic device 130 and the plurality of first conductive bumps 160 . The first molded object 140 and the second molded object 150 may be formed simultaneously. For example, a mold is placed to surround the substrate 110 including the first electronic device 120, the second electronic device 130, and the first conductive bump 160, and molding resin is injected into the space in the mold, thereby simultaneously forming the first molded object 140 and the first conductive bump 160. Second molding 150 . Here, the molding resin is injected into the mold in a state where the first electronic device 120, the second electronic device 130, the first conductive bump 160, and the substrate 110 are spaced apart from the inner surface of the mold so as not to contact the inner surface of the mold. , thereby forming the first molded part 140 and the second molded part 150 . That is, the first molding 140 is formed to completely cover the first surface 110 a of the substrate 110 and the first electronic device 120 , and the second molding 150 is formed to completely cover the second surface 110 b of the substrate 110 , the second electronic device 120 . device 130 and first conductive bump 160.

As shown in FIG. 3B , in the grinding of the second molded object ( S12 ), the bottom surface of the second molded object 150 is ground to expose the first conductive bump 160 to the outside of the second molded object 150 . That is, in the grinding of the second molded object 150 ( S12 ), the second molded object 150 is ground to expose the first conductive bump 160 to the outside. At this time, the bottom of the first conductive bump 160 may also be partially ground. The bottom surface of the first conductive bump 160 and the bottom surface of the second molding 150 may be coplanar. In addition, the second electronic device 130 may be located within the second molding 150, and the second electronic device 130 may not be exposed to the outside, for example. Grinding may be performed using, for example, a diamond grinder and equivalents thereof, but aspects of the present disclosure are not limited thereto.

As shown in FIG. 3C , when forming the second conductive bumps ( S13 ), the plurality of second conductive bumps 170 are formed to be electrically connected to the plurality of second conductive bumps 170 that were respectively exposed to the outside in the grinding of the second molded article ( S12 ). First conductive bump 160 . The second conductive bump 170 may be formed using one of ball drop, screen printing, electroplating, vacuum evaporation, plating, and equivalents thereof, but aspects of the present disclosure are not limited thereto. In addition, the second conductive bump 170 may be made of a metallic material, such as lead/tin (Pb/Sn) or lead-free Sn, and their equivalents, but aspects of the present disclosure are not limited thereto.

As shown in FIG. 3D , when placing the jig ( S14 ), the jig 10 is loaded and placed so as to cover the bottom surface 150 b of the second molded object 150 . The clamp 10 is shaped in a generally rectangular frame and may have an interior space 11 having a predetermined depth in a top-to-bottom direction and a planar portion 12 extending outwardly along the outer circumference for a predetermined length. The planar portion 12 may be in contact with the outer circumference of the bottom surface 150b of the second molded object 150 and then fixed, and the second conductive bump 170 formed on the bottom surface 150b of the second molded object 150 may be inserted into the inner space 11 . That is, when placing the jig ( S14 ), the jig 10 is placed so as to cover the bottom surface 150 b of the second molded object 150 , and the first molded object 140 , the side surface of the substrate 110 and the second molded object 150 The side surfaces are exposed to the outside.

As shown in FIG. 3E , when the EMI shielding layer is formed ( S15 ), the side surface of the first molded object 140 , the substrate 110 and the second molded object 150 are exposed to the outside when the jig is placed ( S14 ). EMI shielding layer 180 is formed. The EMI shielding layer 180 is formed to completely cover all of the first molded object 140 , the side surface of the substrate 110 and the side surface of the second molded object 150 , except for the bottom surface 150 b of the second molded object 150 covered by the clamp 10 . That is, the EMI shielding layer 180 is formed to completely cover the four side surfaces and the top surface of the semiconductor package 100 except for the bottom surface of the semiconductor package 100 . The EMI shielding layer 180 may be formed to a predetermined thickness through plasma deposition or spraying, but aspects of the present disclosure are not limited thereto. In addition, after forming the EMI shielding layer ( S15 ), further cleaning may be performed in order to remove metal residue generated in the formation of the EMI shielding layer 180 made of conductive material. In addition, after the EMI shielding layer 180 is formed and cleaning is performed, the jig 10 located under the second molded object 150 is separated to complete the semiconductor package 100 having the EMI shielding layer 180 . In FIGS. 3A to 3E , although a single semiconductor package 100 is manufactured, multiple semiconductor packages may be formed on the substrate 110 and then divided into discrete semiconductor packages 100 through a single process.

Referring to FIG. 4 , a cross-sectional view of a semiconductor package is shown according to another embodiment of the present disclosure.

As shown in FIG. 4 , the semiconductor package 200 includes a substrate 110 , a first electronic device 120 , a second electronic device 130 , a first molded object 140 , a second molded object 150 , a first conductive bump 160 , a second conductive bump block 170 and EMI shielding 280. The semiconductor package 200 including the substrate 110, the first electronic device 120, the second electronic device 130, the first molding 140, the second molding 150, the first conductive bump 160 and the second conductive bump 170 has the same configuration as shown in FIG. The semiconductor package 100 shown in 1 has the same construction. Accordingly, the following description of semiconductor package 200 will focus on EMI shielding layer 280 , which is a different feature than semiconductor package 100 shown in FIG. 1 .

The EMI shielding layer 280 is formed to cover the top surface, four side surfaces, and the bottom surface of the semiconductor package 200 to a predetermined thickness, and may expose the second conductive bump 170 to the outside. That is, the EMI shielding layer 280 may be formed to completely cover the semiconductor package 200 except for the second conductive bump 170 . Additionally, the EMI shielding layer 280 may be made of a conductive material and may be electrically connected to a ground of the semiconductor package 200 or an external ground.

EMI shielding layer 280 may include a plurality of exposed holes 280a. The second conductive bump 170 may be exposed to the outside of the EMI shielding layer 280 through the exposure hole 280a. That is, the exposed hole 280a of the EMI shielding layer 280 may be positioned to correspond to the second conductive bump 170.

In addition, the exposure hole 280a may have a width larger than the diameter of the second conductive bump 170. That is, the EMI shielding layer 280 may be separated from the second conductive bump 170 by a predetermined distance (d) by exposing the hole 280a, and may be electrically disconnected from the second conductive bump 170 made of a conductive material. Here, a portion surrounding the second conductive bump 170 in the second molding 150 may be exposed to the outside of the exposure hole 280 a of the EMI shielding layer 280 .

The EMI shielding layer 280 is formed to cover all surfaces of the semiconductor package 200 except for the second conductive bump 170 as an external terminal, thereby shielding EMI caused by (or induced on) the semiconductor package 200 .

The semiconductor package 200 shown in FIG. 4 is manufactured by the semiconductor package manufacturing method shown in FIG. 2 . Referring to FIGS. 5A and 5B , cross-sectional views of various steps in a method of manufacturing the semiconductor package shown in FIG. 4 by the semiconductor package manufacturing method shown in FIG. 2 are shown. Hereinafter, a method of manufacturing the semiconductor package 200 will be described with reference to FIGS. 2, 5A, and 5B.

As shown in FIG. 2 , the method of manufacturing the semiconductor package 200 ( S10 ) includes forming a molded object ( S11 ), grinding the second molded object ( S12 ), forming a second conductive bump ( S13 ), placing a jig ( S14 ), and Form the EMI shielding layer (S15). Here, the formation of the molded object (S11), the grinding of the second molded object (S12), and the formation of the second conductive bump (S13) are the same as those in the manufacturing method of the semiconductor package 100 shown in FIGS. 3A to 3C. The corresponding steps are the same. Therefore, the following description of the manufacturing method (S10) of the semiconductor package 200 will focus on the placement of the jig (S14) and the formation of the EMI shielding layer (S15), which are shown in FIGS. 3A to 3C with reference to FIGS. 5A and 5B Methods of manufacturing semiconductor packages have different characteristics.

As shown in FIG. 5A , when placing the jig ( S14 ), the jig 20 is loaded and placed to cover the bottom of the second molded object 150 . As shown in FIG. 6 , the clamp 20 is shaped in a substantially rectangular frame and may have a plurality of grooves 21 having a depth in a top-to-bottom direction. The clamp 20 may include a plurality of grooves 21 corresponding to the second conductive bumps 170 of the semiconductor package 200, and the second conductive bumps 170 may be respectively inserted into the plurality of grooves 21. That is, the second conductive bump 170 may be surrounded by the clamp 20 . Here, in order to allow the second conductive bumps 170 to enter the plurality of grooves 21 of the clamp 20 , the plurality of grooves 21 preferably have a larger diameter than the second conductive bumps 170 .

In addition, the clamp 20 is shaped as a rectangular ring, the central portion of which is opened by a hole 22 formed in the center. That is, the central portion of the bottom surface 150 b of the second molding 150 that is not adjacent to the second conductive bump 170 (or is not immediately adjacent to the second conductive bump 170 ) is exposed to the outside through the hole 22 of the clamp 20 . The EMI shielding layer 280 may also be formed on the bottom surface of the semiconductor package 200 through the hole 22 of the clamp 20 .

When placing the clamp ( S14 ), the clamp 20 is placed under the second molded object 150 to cover the second conductive bump 170 and expose the first molded object 140 , the substrate 110 and the second molded object 150 to the outside. .

As shown in FIG. 5B , when the EMI shielding layer is formed ( S15 ), the EMI shielding layer 280 is formed on the first molded object 140 , the substrate 110 and the second molded object 150 that are exposed to the outside when the jig is placed ( S14 ). . That is, when forming the EMI shielding layer (S15), using the jig 20 as a mask, the EMI shielding layer 280 is formed to cover the top surface, four side surfaces and bottom surface. The EMI shielding layer 280 may be formed to a predetermined thickness through plasma deposition or spraying, but aspects of the present disclosure are not limited thereto. In addition, after forming the EMI shielding layer ( S15 ), further cleaning may be performed in order to remove metal residues generated in the formation of the EMI shielding layer 280 made of conductive material. In addition, after the EMI shielding layer 280 is formed and cleaning is performed, the jig 20 located under the second molded object 150 is separated to complete the semiconductor package 200 having the EMI shielding layer 280 . Furthermore, once the clamp 20 is separated, since the EMI shielding layer 280 is not formed on the second conductive bump 170 surrounded by the clamp 20 and on the portion surrounding the second conductive bump 170 , the exposure of the second conductive bump 170 is exposed. Hole 280a is provided in EMI shielding layer 280. Then, the EMI shielding layer 280 may be electrically disconnected from the second conductive bump 170 through the exposure hole 280a, and may be separated from the second conductive bump 170 by a predetermined distance (d).

Referring to FIG. 7 , a flowchart of a method for manufacturing the semiconductor package shown in FIG. 4 is shown according to another embodiment of the present disclosure. As shown in FIG. 7 , the method (S20) of manufacturing the semiconductor package 200 includes forming a molded object (S11), grinding the second molded object (S12), forming an EMI shielding layer (S23), forming an exposure hole (S24), and forming The second conductive bump (S25). Here, the formation of the molded object (S11) shown in FIG. 7 and the grinding of the second molded object (S12) are the same as the corresponding steps in the manufacturing method of the semiconductor package 100 shown in FIGS. 2, 3A, and 3B.

Referring to FIGS. 8A to 8C , cross-sectional views of the steps of forming the EMI shielding layer ( S23 ), forming the exposure hole ( S24 ), and forming the second conductive bump ( S25 ) shown in FIG. 7 are shown. Therefore, the method ( S20 ) of manufacturing the semiconductor package 200 will be described with reference to FIGS. 7 and 8A to 8C.

As shown in FIG. 8A , when forming the EMI shielding layer ( S23 ), the EMI shielding layer 280 is formed to completely cover the substrate 110 , the first molded object 140 and the second molded object 150 . The EMI shielding layer 280 may be formed to a predetermined thickness by plasma deposition or spraying, but the present disclosure is not limited thereto.

As shown in FIG. 8B , when forming the exposure hole ( S24 ), the EMI shielding layer 280 may be partially removed to expose the first conductive bump 160 to the outside. That is, by forming a plurality of exposure holes 280a in the EMI shielding layer 280, the first conductive bumps 160 are exposed to the outside. The plurality of exposed holes 280a of the EMI shielding layer 280 are formed by etching or laser removing a portion of the EMI shielding layer 280. Additionally, forming the exposure holes 280a may be performed by any process known in the art, so long as the EMI shielding material can be patterned in a desired pattern, but is not limited to etching or laser as disclosed herein. As shown in FIG. 8B , the width (d1) of each exposure hole 280a is preferably larger than the diameter (d2) of each first conductive bump 160. In order to electrically disconnect the first conductive bump 160 and the second conductive bump 170 to be described later, the exposure hole 280 a is preferably formed with a sufficiently large width (ie, d1 ). In addition, after forming the exposure hole 280a, a cleaning process for removing metal residues may be further performed.

As shown in FIG. 8C , when forming the second conductive bump (S25), the second conductive bump 170 is formed to be electrically connected to the first conductive bump 160 exposed to the outside through the exposure hole 280a. The second conductive bump 170 is preferably formed to have a larger diameter (d3) than the width (d1) of the exposure hole 280a. That is, the second conductive bump 170 may be spaced apart from the EMI shielding layer 280 by a predetermined distance to be electrically disconnected from the EMI shielding layer 280 .

Figure 9A shows a cross-sectional view of a semiconductor package 900 according to one example. Figure 9B shows an enlarged portion of the semiconductor package 900 of Figure 9A. Semiconductor package 900 and its components may be similar to any one or more other semiconductor packages or corresponding components thereof described herein, and the characteristics of semiconductor package 900 are further described below.

Semiconductor package 900 includes a substrate 910 having a substrate top surface 911, a substrate bottom surface 912, and a substrate lateral surface 913 therebetween. The substrate 910 also includes a substrate top first pad 9111 at the substrate top surface 911 and a substrate bottom first pad 9121 at the substrate bottom surface 912 . Substrate 910 may be similar to any substrate described herein, such as substrate 110 . In the same or other examples, substrate 910 may include a redistribution structure (RDS) having one or more dielectric layers of dielectric material and one or more dielectric layers between and through the dielectric layers. conductive layer. Such conductive layers may define pads, traces, and vias through which electrical signals or voltages may be distributed across the RDS in both horizontal and vertical directions.

Semiconductor package 900 also includes electronics 920 attached to substrate top surface 911 and coupled to substrate top first pad 9111 . Electronic device 920 may include one or more transistors, and may include microcontroller devices, radio frequency (RF) devices, wireless (WiFi, WLAN, etc.) switches, power amplifier devices, low noise amplifier (LNA) devices, and the like. There may also be examples of electronic devices 920 that may include MEMS (microelectromechanical systems) devices, where the MEMS devices may include one or more transducers. Electronic device 920 includes a device surface 921 facing a substrate top surface 911, a device surface 922 facing away from the substrate top surface 911, and a device lateral surface 923 therebetween. In this example, electronic device 920 includes a semiconductor die with bumps at device surface 921 and is flip-chip mounted onto substrate top surface 911 such that one of the bumps contacts first pad 9111 on top of the substrate. The term "bump" may refer to a ball-shaped bump (such as a solder bump or a solder-coated copper core bump) and/or may refer to a metal rod-shaped bump (such as a copper pillar with or without a solder tip). ). In other examples, electronic device 920 may include a semiconductor die having an inactive surface facing substrate top surface 911 and having one or more wire bonds extending from its active surface to one or more pads at substrate top surface 911 . There may also be examples of an electronic device 920 that may include a packaged device having one or more semiconductor dies, and optionally having another substrate coupling such one or more semiconductor dies together. , where such a package device may be coupled to one or more pads at the top surface 911 of the substrate.

In this example, semiconductor package 900 also includes one or more passive components coupled to substrate top surface 911 , such as passive component 931 coupled to second pad 9112 on top of the substrate. In some examples, such one or more passive components may include capacitors, inductors, and/or resistors. Although in this example, the passive member 931 is presented as a surface mount technology (SMT) device coupled to the second pad 9112 on top of the substrate via an SMT connector, other examples may exist where the passive member 931 may be packaged or mounted differently. , such as via wire bonds or bumps.

Several configurations of different devices and components may be coupled to substrate top surface 911. For example, in addition to electronic device 920 and passive member 931 , FIG. 9 shows electronic device 9201 , electronic device 9202 and passive member 932 coupled to substrate 910 at substrate top surface 911 . Electronic device 9201 and/or electronic device 9202 may be similar to one or more of the different device options described with reference to electronic device 920 . As an example, the electronic device 920 may include a microcontroller device, and the electronic device 9201 may include a MEMS device such as a gyroscope, a microphone, a pressure sensor, or a gas sensor. Although electronic device 9201 is shown bonded to substrate top surface 910 via bumps, there may be other embodiments in which electronic device 9201 may be wire bonded. Additionally, as an option, electronic device 9202 is shown coupled to substrate top surface 910 via wire bonds while stacked on top of electronic device 920. Passive member 932 may be similar to passive member 931 and is shown coupled to substrate top surface 911 between electronic device 920 and electronic device 9201 .

Encapsulation 940 is shown in FIG. 9 encapsulating substrate top surface 911 and all components coupled thereto, including electronic devices 920, 9201 and 9202 and passive components 931 and 932. Although this example shows an encapsulation 940 that covers the lateral and top surfaces of these devices and components, there may be examples in which the top surface of one or more of these devices or components may be exposed through the encapsulation 940 .

9 also shows an electronic device 970 attached to the substrate bottom surface 912 and coupled to the substrate bottom first pad 9121. Electronic device 970 may be similar to one or more of the different device options described with reference to electronic device 920 and include a device surface 971 facing substrate bottom surface 912, a device surface 972 facing away from substrate bottom surface 912, and a device lateral surface 973 therebetween. . In this example, electronic device 970 includes a semiconductor die with bumps at device surface 971 and is flip-chip mounted onto substrate bottom surface 912 such that one of the bumps contacts first pad 9121 on the bottom of the substrate. In other examples, electronic device 970 may include a semiconductor die with an inactive surface facing substrate bottom surface 912 and having one or more lines extending from its active surface to one or more pads at substrate bottom surface 912 Engagement. There may also be examples in which electronic device 970 includes a packaged device having one or more semiconductor dies therein, and optionally having another device coupling such one or more semiconductor dies together. A substrate wherein such packaging devices may be coupled to one or more pads at a bottom surface 912 of the substrate.

Semiconductor package 900 also includes external interconnects (eg, external interconnect 980 ) configured to interface or attach semiconductor package 900 to an external device, such as to an external substrate or board portion of a larger electronic device. External interconnect 980 is coupled to substrate bottom second pad 9122 of substrate 910 and projects further from substrate bottom surface 912 than device surface 972 of electronic device 970 . External interconnect 980 is shown to include an interconnect interior portion 981 adjacent substrate bottom surface 912 and an interconnect distal portion 982 disposed away from substrate bottom surface 912 . Although in this example the interconnect inner portion 981 and the interconnect distal portion 982 are both presented as stacked conductive solder balls, it is possible that one or both of them may be, for example, solder-encapsulated copper or metal core balls, or conductive Other examples of rods being plated, wire bonded, or otherwise attached to the substrate bottom surface 912. As another option, the external interconnect 980 may be a single conductive structure rather than stacked conductive structures, such as a single solder ball, or a single conductive rod or post.

Encapsulation 950 is shown in Figure 9 and encapsulates substrate bottom surface 912 and any components coupled thereto, including electronics 970 and passive components 933. Although this example shows an encapsulation 950 covering the lateral and bottom surfaces of such devices and components, there may be examples in which the bottom surface of one or more such devices or components may remain exposed through the encapsulation 950 . Encapsulation 950 confines external interconnect 980 while leaving the distal ends of external interconnect 980 exposed and protruding from capsule bottom surface 952 . In some examples, the material of capsule 950 may be similar to one or more materials described for capsule 940 . For example, encapsulant 940 may include a layer of molding material, and encapsulant 940 may include a layer of the same molding material, whether applied simultaneously with or integrally with the layer of encapsulant 940 or not. .

FIG. 9B includes an enlarged view showing details of external interconnect 980 relative to encapsulation 950 . As seen in the enlarged view, encapsulation 950 includes through-holes 955 that reveal different portions of external interconnect 980 . For example, interconnect encapsulation portion 985 is attached to substrate bottom surface 912 and bounded by and in contact with encapsulation 950 . The interconnect exposed portion 986 is pressed into the through-hole 955 and bounded by but separated from the encapsulation 950 . The interconnection protrusions 987 are not only exposed to the encapsulation 950 but also protrude further than the bottom surface 952 of the encapsulation.

FIG. 9 also shows an electromagnetic interference (EMI) shield 960 covering the capsule top surface 942 and the capsule lateral surface 943 of the capsule 940 and the substrate lateral surface 913 of the substrate 910 . In this example, EMI shield 960 also covers capsule lateral surface 953 of capsule 950 . And leaving at least a portion of the encapsulation bottom surface 952 exposed such that the EMI shield 960 remains spaced apart from external interconnects 980 . In this example, EMI shielding 960 includes a continuous conformal coating that conforms to the respective contours, including at the capsule top surface 942 , the capsule lateral surface 943 , the substrate lateral surface 913 and the capsule lateral surface 913 . 953 any surface irregularities or roughness and/or any surface irregularities or roughness in between.

Semiconductor package 900, in this example, also includes a compartment shield 990, which may be an EMI shield configured to provide EMI protection within a compartment area surrounding one or more components, such as electronic device 970. The compartment shield 990 includes a compartment lateral barrier 991 defining a device lateral surface 973 along the perimeter of the electronic device 970 and also includes a compartment bottom barrier 992 defining a device surface 972 .

In some examples, compartment lateral barrier 991 may be a plurality of conductive rods, such as posts or wires, whether plated, wire bonded, soldered, or otherwise coupled, arranged with the perimeter of electronic device 970 One or more columns that are at least partially adjacent. The compartment bottom barrier 992 covers the area below the device surface 972 and contacts the compartment lateral barrier 991 . The compartment bottom barrier 992 may be a metal plate or a conformal coating similar to the conformal coating of the EMI shield 960 . In some examples, the compartment bottom barrier 992 may be part of the conformal coating of the EMI shield 960 , although there may be other examples in which the compartment bottom barrier 992 may be formed independently of and/or in sequence to the EMI shield 960 . The conductive rods of the compartment transverse barrier 991 are exposed at the capsule bottom surface 952 to allow contact with the compartment bottom barrier 992 and, as seen in this example, may protrude through the capsule bottom surface 952 such that this The protruding lateral portion of the conductive rod may be covered by the material of the compartment bottom barrier 992.

Examples may also exist where the compartment lateral barrier 991 and the compartment bottom partition 992 of the compartment shield 990 may comprise a single continuous piece of material (such as a metal cylinder or covering), or one or more wires such as wire bonded to the substrate bottom surface 912 from one side of the electronic device 970 to the other as a wireframe. Some examples may also include a compartment shield similar to the compartment shield 990 shield, or with the electronics 970 removed or a device or component in addition to the electronics 970 .

10A-10C illustrate various initial stages of assembly of a semiconductor package similar to one or more of those described herein, such as semiconductor package 900 (Figs. 9, 11), semiconductor package 1200 (Figs. 12-13 ), semiconductor package 1400 (Figs. 14 to 15), semiconductor package 1600 (Figs. 16 to 17), and/or semiconductor package 1800 (Fig. 18). FIG. 10A presents substrate 910 prior to singulation, including multiple portions defining adjacent portions that may subsequently be singulated into separate packages, such as unit portion 1011 and unit portion 1012 .

In some examples, substrate 910 may be pre-prepared and may include a laminate substrate, such as a printed circuit board, and may be in strip or panel form. In the same or other examples, substrate 910 may include a core layer, such as fiberglass or other rigid non-conductive material, between its dielectric layers of RDS to increase structural stiffness. However, other examples may exist in which the substrate 910 may be a build-up substrate rather than prefabricated, and/or may be coreless. In such an example, the different dielectric and conductive layers of the RDS of substrate 910 may be constructed by layering and patterning each other while being supported by a removable carrier beneath the bottom surface 912 of the substrate. Such a carrier may be a wafer or panel including semiconductor, glass or metallic materials.

Cell portion 1011 of substrate 910 includes electronic devices 920 , 9201 , 9202 and passive members 931 and 932 coupled to substrate top surface 911 . Accordingly, unit portion 1012 of substrate 910 includes electronic devices 920', 9201', 9202' and passive members 931' and 932' coupled to substrate top surface 911.

Figure 10B presents a subsequent stage of the assembly in which encapsulation 940 is applied to encapsulate all devices and components coupled to the substrate top surface 911 across and between unit portions 1011 and 1012 . Encapsulation 940 includes a single layer of non-conductive material such as resin, polymer composite, polymer with fillers, epoxy, epoxy, epoxy acrylate with fillers such as silicon dioxide or other inorganic materials , molding compounds, silicone and/or resin-impregnated B-stage prepregs, etc. In examples where encapsulant 940 includes a molding compound, this material may be applied in any of several ways, such as by compression molding, injection molding, or film-assisted molding.

Figure 10C illustrates a subsequent stage of assembly where components are added to the substrate bottom surface 912. For example, electronics 970 and passive member 933 are coupled to substrate bottom surface 912 at cell portion 1011 of substrate 910 . Accordingly, electronic device 970' and passive member 933' are coupled to substrate bottom surface 912 at cell portion 1012 of substrate 910.

Figures 11A-11E illustrate various subsequent stages of assembly following Figures 10A-10C and leading to semiconductor package 900 (Figure 9). 11A illustrates an interconnection internal portion 981 of an external interconnect 980 attached to the substrate bottom surface 912 at cell portion 1011 and presents an external interconnect 980' attached to the substrate bottom surface 912 at cell portion 1012. Interconnect internal portion 981'. In some examples, interconnect internal portions 981 and 981' may be applied using a solder drop or ball drop process, a screen printing process, or a plating process. In the same or other examples, interconnect internal portions 981 and 981' may be at least partially resoldered once attached.

11A also shows the application of encapsulant 950 across and between cell portions 1011 and 1012 to encapsulate substrate bottom surface 912 and all components coupled thereto, including electronic devices 970 and 970', passive members 933 and 933' and interconnect interiors 981 and 981'. In this example, encapsulant 950 is applied such that encapsulant bottom surface 952 completely encapsulates interconnect interior portion 981 , electronics 970 , and passive component 933 , but it is possible to apply encapsulant 950 and retain one of these elements or Multiple bottom exposed examples.

Figure 11A further illustrates compartment shields 990 and 990', which shield electronic devices 970 and 970' at unit portions 1011 and 1012, respectively. In some embodiments, the compartment lateral barriers 991 and 991' may be attached to the substrate bottom surface 912 adjacent the perimeter of the respective electronic device and at least partially encapsulated by the encapsulant 950. Compartment bottom barriers 992 and 992' may be applied over the enclosure 950 to attach to the compartment lateral barriers 991 and 991' respectively.

Figure 11B presents a subsequent stage of assembly in which corresponding portions of encapsulation 950 are removed to expose interconnect interior portions 981 and 981'. Such removal of encapsulation 950 may correspond to through-holes 955 , thereby defining corresponding portions of interconnection encapsulation portion 985 and interconnection exposed portion 986 . In some examples, through-holes 955 may be formed in encapsulation 950 by laser ablation, by mechanical ablation, and/or by etching material through encapsulation 950 .

11C presents a subsequent stage of assembly in which interconnected distal portion 982 is coupled to interconnected inner portion 981 exposed in through-holes 955 such that interconnected distal portion 982 protrudes further than capsule bottom surface 952. In some examples, interconnect distal portion 982 may be applied using a solder drop or ball drop process, a screen printing process, or a plating process. In the same or other examples, interconnect distal portion 982 may be at least partially resoldered once attached.

Figure 11D presents the subsequent stage of the assembly with the main strap 1190 attached. Primary tape 1190 includes primary adhesive across its top surface such that primary tape portion 1191 adheres under unit portion 1011 and primary tape portion 1192 adheres under unit portion 1012 . Thus, the primary adhesive is sealed to the encapsulation bottom surface 952 and the external interconnect 980 , with the interconnect distal portion 982 protruding into and/or being encapsulated by the thickness of the primary band 1190 in this example. seal up. The primary tape 1190 may also include a base layer that carries the primary adhesive.

After attaching the main strip 1190, unit portions 1011 and 1012 can be separated from each other by encapsulation 940, through the substrate 910 and through the main strip 1190 along the dotted line singulation shown in Figure 11D. Singularization defines the capsule peripheral edge 954 of the cell portion 1011 at the juncture of the capsule bottom surface 952 and the capsule lateral surface 953 . The main tape portion 1191 remains attached to the unit portion 1011 after singulation, with its main adhesive still hermetically sealed to the bottom of the capsule bottom surface 952 and the capsule peripheral edge 954 . Similarly, after singulation, the primary tape portion 1192 remains attached to the unit portion 1012 with its primary adhesive still hermetically sealed to the bottom of the capsule bottom surface 952 and the capsule peripheral edge 954'.

FIG. 11E presents a subsequent stage of the assembly, with unit portions 1011 and 1012 attached to the secondary adhesive of secondary strip 1195 . Secondary belt 1195 may be supported by a carrier structure, and unit portions 1011 and 1012 , along with corresponding primary belt portions 1191 and 1192 , may be picked and placed adjacent one another on secondary belt 1195 such that each primary belt portion 1191 and 1192 The bottom of the secondary tape is sealed with 1195 secondary adhesive. The secondary belt 1195 is exposed at a gap that separates the primary belt portions 1191 and 1192 and the unit portions 1011 and 1012 . The secondary tape 1195 may also include a base layer having a secondary adhesive thereon. In some examples, the base layer of primary band 1190 or secondary band 1195 may include polyethylene terephthalate and/or polyimide materials.

With the pick and place operation complete, EMI shielding layer 1160 is applied. In this example, EMI shielding layer 1160 is applied as a continuous coating that includes EMI shielding 960 , EMI shielding 960 ′, and remaining EMI shielding 1163 . EMI shield 960 covers unit portion 1011 and includes capsule top surface 942, capsule lateral surface 943, substrate lateral surface 913, and capsule lateral surface 953. EMI shield 960' covers corresponding components of unit portion 1012. The remaining EMI shielding 1163 covers the sidewalls of the primary strap portion 1191 , the sidewalls of the primary strap portion 1192 and portions of the secondary strap 1195 . In this example, wherever secondary strap 1195 may be exposed on primary strap portions 1191 or 1192, secondary strap 1195 is covered by remaining EMI shielding 1163, which is included in the gap that separates primary strap portions 1191 and 1192.

Because the sidewalls of the main strap portion 1191 are coplanar with the capsule lateral surface 953, the EMI shielding layer 1160 does not curve at the capsule peripheral edge 954, but rather in a substantially straight line from the capsule lateral surface 953 to the sidewalls of the main strap. Continuous in a straight plane. There is no bending that would normally occur if the interface between the primary strip 1190 and the encapsulant lateral surface 953 were changed to a right angle, so the EMI shielding layer 1160 does not accumulate or protrude from the adjacent encapsulation peripheral edge 954. Accordingly, the thickness of EMI shielding layer 1160 remains substantially constant at the encapsulation peripheral edge 954 and across the primary adhesive interface with primary strap portion 1191 .

In some examples, EMI shielding layer 1160 (including EMI shielding 960 , EMI shielding 960 ′, and remaining EMI shielding 1163 ) may include one or more conductive material layers or alloys, such as copper (Cu), nickel (Ni), gold ( Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten ( W), rhenium (Re) or graphite. In some examples, EMI shielding layer 1160 may include a bonding agent to allow internal metal particles to bond to each other and to encapsulation 140 , substrate 910 , and/or encapsulation 150 . In other examples, EMI shielding layer 1160 may include a conductive polymer doped with a metal or metal oxide, such as polyacetylene, polyaniline, polypyrrole, polythiophene, or polysulfide nitride. In other examples, EMI shielding layer 1160 may include conductive ink prepared by mixing conductive materials such as carbon black, graphite, or silver. Exemplary procedures for forming EMI shielding layer 1160 may include using spin coating, spray coating, electrolytic plating, electroless plating, or sputtering. The thickness of EMI shielding layer 1160 may range from about 3 micrometers (µm) to about 7 microns.

Using EMI shielding layer 1160 as shown in Figure 11E, cell portion 1011 can be pulled from main tape portion 1191, exposing encapsulation bottom surface 952 and interconnect distal portion 982, with EMI shielding 960 along to create a semiconductor package 900 (Figure 9). During this removal, primary tape portion 1191 remains attached to secondary tape 1195 and EMI shielding layer 1160 breaks precisely along its interface with the primary adhesive of primary tape portion 1191 , thereby separating EMI shielding 960 from the remaining EMI shielding. 1163 separated. Cell portion 1012 can similarly be pulled from primary tape portion 1192 such that remaining EMI shielding 1163 remains connected to primary tape portions 1191 and 1192 and to secondary tape 1195 .

The adhesive strength of the secondary adhesive of the secondary tape 1195 sealed to the base of the primary tape portion 1191 may be greater than the adhesive strength of the primary adhesive sealed to the primary tape portion 1191 of the unit portion 1011 . Therefore, the secondary adhesive can prevent the primary tape portion 1191 from separating from the secondary tape 1195. This may allow controlled rupture of the interface between the primary adhesive along the capsule lateral surface 953 and the primary tape portion 1191 across the entire capsule peripheral edge 954 by a substantially fixed thickness EMI shielding layer 1160 to define EMI shielded 960. This fixed thickness and controlled breakdown of EMI shielding can allow for increased and consistent coverage of the capsule lateral surface 953 such that EMI is measured vertically from the capsule bottom surface 952 and along the capsule lateral surface 953 Shield 960 is exposed to an exposure height not exceeding 0 to 50 µm. This avoids problems such as EMI shielding layer 1160 rupturing through encapsulation perimeter edge 954 leaving overhanging portions of EMI shielding 960, and also avoids EMI shielding layer 1160 excessively rupturing above encapsulation perimeter edge 954 leaving EMI shielding 1160 overhanging. Shield 960 issues with over-exposed encapsulation lateral surface 953.

Figure 12A shows a cross-sectional view of a semiconductor package 1200 according to one example. Figure 12B shows an enlarged portion of the semiconductor package 1200 of Figure 12A. Semiconductor package 1200 and its components may be similar to any one or more other semiconductor packages or corresponding components thereof described herein, and the characteristics of semiconductor package 1200 are further described below. For example, semiconductor package 1200 may be related to semiconductor package 900 described above, including substrate 910 , electronic devices 920 , 9201 , 9202 and 970 , passive components 931 , 932 and 933 and encapsulation 940 and each corresponding portions and components as well as the above. Other corresponding features or components related to semiconductor package 900. There may be different combinations of these elements that the semiconductor package 1200 may include.

Semiconductor package 1200 also includes an external interconnect 1280 having an interconnect internal portion 1281 and an interconnect distal portion 1282, which may be correspondingly similar to external interconnect 980, interconnect internal portion 981, and interconnect distal portion 982 described above. Additionally, semiconductor package 1200 includes encapsulation 1250, which may be similar to encapsulation 950 and its corresponding components and portions described above.

Encapsulation 1250 is shown in Figure 12 and encapsulates substrate bottom surface 912 and any components coupled thereto, including electronics 970 and passive components 933. Although this example shows an encapsulation 1250 covering the lateral and bottom surfaces of such devices and components, there may be one or more bottom surfaces of such devices or components that may remain exposed by the encapsulation 1250 example. Additionally, capsule 1250 defines external interconnects 1280 while leaving the distal ends of external interconnects 1280 exposed and protruding from capsule bottom surface 1252 .

FIG. 12B includes an enlarged view showing details of external interconnect 1280 relative to encapsulation 1250 . In this example, capsule bottom surface 1252 is coplanar with the bottom of interconnected interior portion 1281 , and the top perimeter of interconnected distal portion 1282 rests against that portion of capsule bottom surface 1252 , wherein the capsule Bottom surface 1252 defines the bottom of interconnect interior 1281 .

Figure 12 also shows an electromagnetic interference (EMI) shield 1260, which is similar to the EMI shield 960 described above. EMI shield 1260 covers the capsule top surface 942 and capsule lateral surface 943 of capsule 940 and the substrate lateral surface 913 of substrate 910 . In this example, EMI shield 1260 also covers capsule lateral surface 1253 of capsule 1250 and leaves at least a portion of capsule bottom surface 1252 exposed such that EMI shield 1260 remains spaced apart from external interconnects 1280 .

In this example, the semiconductor package 1200 also includes a compartment shield 990 having a compartment lateral barrier 991 and a compartment bottom barrier 992 as described above, which may be an EMI shield configured to contain one or more components such as electronics. EMI protection is provided within the compartment area of the device 970).

Semiconductor package 1200 may be assembled through various stages of assembly, including the initial stages of assembly shown in Figures 10A-10C. Figures 13A-13E illustrate various subsequent assembly stages following Figures 10A-10C and leading to semiconductor package 1200 (Figure 12).

Figure 13A depicts stages of assembly similar to those of Figure 11A, but for semiconductor package 1200 (Figure 12). The interconnect interior 1281 of the external interconnect 1280 is attached to the substrate bottom surface 912 at the cell portion 1011, and the interconnect interior 1281' is attached to the substrate bottom surface 912 at the cell portion 1012. Figure 13A also shows an encapsulant 1250 that is applied across and between unit portion 1011 and unit portion 1012 to encapsulate substrate bottom surface 912 and all components coupled to substrate bottom surface 912, including Electronics 970 and 970', passive components 933 and 933', and interconnect interiors 1281 and 1281'. In this example, encapsulation 1250 is used to completely encapsulate interconnect interior 1281, electronics 970, and passive components 933, but other situations are possible, such as encapsulation 1250 being used to leave these components intact. One or more of the bottoms are exposed. Figure 13A further presents compartment sidewalls 991 and 991' attached to the substrate bottom surface 912 adjacent the periphery of the individual electronic devices 970 and 970' and at least partially encapsulated 1250 Encapsulated.

Figure 13B depicts the stages of the assembly that are similar to those of Figure 11B, but for semiconductor package 1200 (Figure 12). Encapsulation 1250 is partially removed or thinned to expose the bottom of interconnect interiors 1281 and 1281'. The thinning or planarization process reduces the thickness of encapsulation 1250 until interconnect exposed portions 1286 and 1286' of interconnect interiors 1281 and 1281' are exposed, which in this example are removed from the encapsulation. Encapsulation bottom surface 1252 is exposed and coplanar with capsule bottom surface 1252 . In some embodiments, the planarization may involve a mechanical grinding process and/or one or more etching stages. In this example, the planarization also exposes the bottoms of compartment side walls 991 and 991'. Compartment bottom barriers 992 and 992' may be applied after this planarization process, which compartment bottom barriers 992 and 992' respectively cover the area below the electronic devices 970 and 970' and respectively contact the compartment side walls 991 and 991' exposed bottom.

Figure 13C presents subsequent stages of assembly that are similar to those of Figure 11C, but for semiconductor package 1200 (Figure 12). The interconnect distal portions 1282 and 1282' are coupled to the interconnect interiors 1281 and 1281' exposed by the planarization process of Figure 13B and are therefore more protruding than the encapsulation bottom surface 1252. In some examples, interconnect distal portions 1282 and 1282' may be applied using a solder drop or ball drop process, a screen printing process, or a plating process. In the same or other examples, interconnect distal portions 1282 and 1282' may be at least partially resoldered once attached.

Figure 13D presents subsequent stages of assembly that are similar to those of Figure 11D, but for semiconductor package 1200 (Figure 12). Primary tape 1190 contains primary adhesive across its top surface such that primary tape portion 1191 is bonded beneath unit portion 1011 and primary tape portion 1192 is bonded beneath unit portion 1012 . Thus, the primary adhesive is sealed to the capsule bottom surface 1252 and to the external interconnect 1280 , with the interconnect distal portion 1282 in this example protruding into the thickness of the primary strip 1190 and/or formed by the primary strip 1190 Encapsulated by thickness.

After attachment of the primary strip 1190 , unit portions 1011 and 1012 can be separated from each other along the dotted line singulated through the encapsulation 940 shown in FIG. 13D , through the substrate 910 and through the primary strip 1190 open. The singulation defines a capsule peripheral edge 1254 of the unit portion 1011 at the juncture of the capsule bottom surface 1252 and the capsule lateral surface 1253 . After singulation, the primary tape portion 1191 remains attached to the unit portion 1011 with its primary adhesive still hermetically sealed to the bottom of the capsule bottom surface 1252 and to the capsule peripheral edge 1254.

Figure 13E presents subsequent stages of assembly that are similar to those of Figure 11E, but for semiconductor package 1200 (Figure 12). Unit portion 1011 and unit portion 1012 are attached to secondary adhesive of secondary tape 1195 . The secondary belt 1195 can be supported by the carrier structure, and the unit portions 1011 and 1012 along with the corresponding primary belt portions 1191 and 1192 can be picked and placed adjacent to each other on the secondary belt 1195 such that each primary belt portion 1191 And the bottom of 1192 is sealed to the secondary tape 1195 of the secondary adhesive. The secondary strip 1195 is exposed to a gap that separates the primary strip portions 1191 and 1192 and separates the unit portions 1011 and 1012 from each other.

When the pick and place operation is completed, EMI shielding layer 1160 is applied. In this example, EMI shielding layer 1160 is applied as a continuous coating, which includes EMI shielding 1260, EMI shielding 1260' and remaining EMI shielding 1163. EMI shield 1260 covers unit portion 1011, including capsule top surface 942, capsule lateral surface 943, substrate lateral surface 913, and capsule lateral surface 1253. EMI shield 1260' covers corresponding components of unit portion 1012. The remaining EMI shielding 1163 covers the sidewalls of the primary strap portion 1191 , the sidewalls of the primary strap portion 1192 , and the secondary strap 1195 . In this example, secondary strap 1195 is covered by remaining EMI shielding 1163 where it is exposed by primary strap portion 1191 or 1192 , including over the gap that separates primary strap portion 1191 from primary strap portion 1192 .

Such a configuration provides advantages similar to those described above with respect to FIG. 11E , such that the thickness of the EMI shielding layer 1160 does not bulge, but is instead maintained at the periphery edge 1254 of the encapsulant and across the main adhesive portion of the main strap portion 1191 . The interface remains essentially unchanged.

As shown in Figure 13E with EMI shielding layer 1160 applied, cell portion 1011 can be pulled from main strap portion 1191, leaving encapsulation bottom surface 1252 and interconnect distal portion 1282, and taking EMI shielding 1260 with them Semiconductor package 1200 is produced (Figure 12). During this removal, primary tape portion 1191 remains attached to secondary tape 1195 and EMI shielding layer 1160 breaks precisely along its interface with the primary adhesive of primary tape portion 1191 , thereby separating EMI shielding 1260 from the remaining EMI. Shield 1163 apart. Cell portion 1012 may similarly be pulled from primary tape portion 1192 such that remaining EMI shielding 1163 remains attached to primary tape portions 1191 and 1192 and to secondary tape 1195 .

The characteristics of the primary band 1190 and the secondary band 1195 remain as shown above with respect to Figure 11E to achieve a fixed thickness and controlled rupture of the EMI shielding layer 1160, thereby allowing increased and consistent coverage of the encapsulation lateral surface 1253. Therefore, an exposure height of no more than 0 to 50 μm measured from the capsule bottom surface 1252 and along the capsule lateral surface 1253 is exposure from the EMI shield 1260 . This avoids the problem of the EMI shielding layer 1160 rupturing past the encapsulant peripheral edge 1254, leaving an overhanging portion of the EMI shielding 1260, and also avoids the problem of the EMI shielding layer 1160 breaking excessively above the encapsulant peripheral edge 1254, leaving the capsule laterally. Surface 1253 shields 1260 from EMI issues being over-exposed.

Figure 14A illustrates a cross-sectional view of a semiconductor package 1400 according to one example. Figure 14B illustrates an enlarged portion of the semiconductor package 1400 from Figure 14A. Semiconductor package 1400 and its elements may be similar to any one or more of the other semiconductor packages or their corresponding elements described herein, and the characteristics of semiconductor package 1400 are further described below. For example, semiconductor package 1400 may be related to semiconductor package 900 described above, which includes substrate 910, electronic devices 920, 9201, 9202, and 970, passive components 931, 932, and 933, and encapsulation 940, and each corresponding parts and components, as well as other corresponding features or elements described above with respect to semiconductor package 900 . There may be embodiments in which the semiconductor package 1400 may include different combinations of these elements.

Semiconductor package 1400 may also include external interconnects 1480 that are similar to external interconnects 980 (Figures 9, 11). However, the external interconnect 1480 of this example is shown as a single bump rather than a configuration with dual stacked bumps. There may also be examples where external interconnect 1480 may include different configurations, such as dual stacked bumps.

Semiconductor package 1400 also includes an encapsulant 1450, which may be similar to encapsulant 950 (Figs. 9, 11) and its individual components and portions described above. Encapsulation 1450, shown in Figure 14, encapsulates substrate bottom surface 912 and any components coupled to the substrate bottom surface 912, including electronics 970 and passive components 933. Although this example shows the encapsulation 1450 covering both the lateral and bottom surfaces of the device and components, there may be examples where the bottom surface of one or more of the devices and components may be left exposed by the encapsulant 1450 . Again, the encapsulation 1450 surrounds the outer interconnect 1480 while leaving the ends of the outer interconnect 1480 exposed and protruding from the encapsulant bottom surface 1452 .

FIG. 14 includes an enlarged view showing details of external interconnect 1480 relative to encapsulation 1450 . In this example, encapsulation 1450 covers a majority of external interconnect 1480 such that encapsulation bottom surface 1452 extends from substrate bottom surface 912 through the maximum width 1489 of external interconnect 1480 . In other examples, encapsulation 1450 may cover a small portion of external interconnect 1480 such that the bottom surface of the encapsulant extends from substrate bottom surface 912 but does not reach the maximum width 1489 of external interconnect 1480 . Encapsulation 1450 also exhibits a skirt 1459 that is a protrusion from the bottom surface 1452 of the encapsulation that surrounds the exposed ends of external interconnects 1480 .

Figure 14 further shows an electromagnetic interference (EMI) shield 1460, which is similar to EMI shield 960 as described above. EMI shield 1460 covers capsule top surface 942 and capsule lateral surface 943 of capsule 940 and substrate lateral surface 913 of substrate 910 . In this example, EMI shield 1460 also covers capsule lateral surface 1453 of capsule 1450 and leaves at least a portion of capsule bottom surface 1452 exposed so that EMI shield 1460 remains spaced apart from external interconnects 1480 .

In this example, the semiconductor package 1400 also includes a compartment shield 990 having compartment sidewalls 991 and a compartment bottom barrier 992, which may be an EMI shield as described above, constructed to surround a or EMI protection is provided in the compartment area of multiple components, such as the electronic device 970 .

Semiconductor package 1400 may be assembled through various stages of assembly, including initial stages of assembly as shown in FIGS. 10A through 10C. Figures 15A-15D illustrate various backend stages that continue the assembly of Figures 10A-10C and ultimately form semiconductor package 1400 (Figure 14).

Figure 15A depicts the later stages of assembly for semiconductor package 1400 (Figure 14). Compartment sidewalls 991 and 991' are attached to substrate bottom surface 912 adjacent individual electronic devices 970 and 970'. External interconnects 1480 are also attached, including an interior portion 1481 of the interconnect closest to the substrate 910 and a distal portion 1482 of the interconnect remote from the substrate 910 . Film 1590 is applied or suspended below substrate bottom surface 912 , covering interconnect distal portions 1482 , leaving interconnect interiors 1481 uncovered, and defining a gap 1550 between film 1590 and substrate bottom surface 912 . In certain embodiments, when film 1590 is applied, film 1590 also contacts device surface 972 of electronic device 970 . In some examples, film 1590 may include a layer or film configured to enable film-assisted molding.

Figure 15B depicts subsequent stages of assembly for semiconductor package 1400 (Figure 14). In the film-assisted molding process, an encapsulant 1450 is applied to fill the gap 1550 between the film 1590 and the bottom surface 912 of the substrate. Encapsulation 1450 extends across and between unit portion 1011 and unit portion 1012 to encapsulate substrate bottom surface 912 and all components coupled thereto, including electronic devices 970 and 970', passive components 933 and 933', and interconnects 1481 and 1481' internally, but leaving protruding interconnect distal portions 1482 and 1482'. Therefore, the maximum thickness of encapsulation 1450 remains less than the height of interconnect 1480 when measured from substrate bottom surface 912 . In this example, the encapsulant 1450 is applied to completely encapsulate the electronic device 970 and the passive component 933, but there are also examples where the encapsulant 1450 can be applied leaving one or more of the bottom portions of such components untouched. exposed. For example, in the example where membrane 1590 contacts electronic device 970 , device surface 972 is left exposed from encapsulation 1450 . Figure 15B further presents compartment sidewalls 991 and 991' attached to substrate bottom surface 912 and encapsulated by encapsulation 1450.

Figure 15C depicts subsequent stages of assembly that are similar to those of Figure 11D, but for semiconductor package 1400 (Figure 14). Membrane 1590 is removed, and compartment bottom barriers 992 and 992' can be applied to cover the area beneath electronic devices 970 and 970', respectively, and to contact the exposed ends of compartment sidewalls 991 and 991', respectively. The primary strip 1190 is shown attached, with the primary adhesive of the primary strip 1190 being sealed to the capsule bottom surface 1452 of the capsule 1450 and to the interconnecting distal portions 1482 and 1482'. The main tape 1190 includes a main tape portion 1191 that is bonded to the underside of the unit portion 1011 and a main tape portion 1192 that is bonded to the underside of the unit portion 1012 . Accordingly, the primary adhesive is sealed to the capsule bottom surface 1452 and to the external interconnect 1480 , which in this example, the interconnect distal portion 1482 protrudes into the thickness of the primary strip 1190 and/or is formed by the primary strip 1190 Encapsulated by thickness.

After attachment of the main strip 1190, unitization along the dashed line shown in Figure 15C through the encapsulation 940, through the substrate 910 and through the main strip 1190 can separate the unit portion 1011 and the unit portion 1012 from each other. separated. The singulation defines a capsule peripheral edge 1454 of the unit portion 1011 at the juncture of the capsule bottom surface 1452 and the capsule lateral surface 1453 . After singulation, the primary tape portion 1191 remains attached to the unit portion 1011 with its primary adhesive still hermetically sealed to the bottom of the capsule bottom surface 1452 and to the capsule peripheral edge 1454.

Although FIG. 15C shows primary strip 1190 being different from membrane 1590, there may be examples where membrane 1590 may include primary strip 1190 or be the same as primary strip 1190. In such an example, membrane 1590 does not need to be removed and replaced with main strip 1190 since both are identical.

Figure 15D depicts subsequent stages of assembly that are similar to those of Figure 11E, but for semiconductor package 1400 (Figure 14). Unit portion 1011 and unit portion 1012 are attached to secondary adhesive of secondary tape 1195 . The secondary belt 1195 can be supported by the carrier structure, and the unit portions 1011 and 1012 and the corresponding primary belt portions 1191 and 1192 can be picked and placed adjacent to each other on the secondary belt 1195 such that each primary belt portion 1191 And the bottom of 1192 is sealed to the secondary tape 1195 of the secondary adhesive. The secondary strip 1195 is exposed to a gap that separates the primary strip portions 1191 and 1192 and separates the unit portions 1011 and 1012 from each other.

When the pick and place operation is completed, EMI shielding layer 1160 is applied. In this example, EMI shielding layer 1160 is applied as a continuous coating that includes EMI shielding 1460, EMI shielding 1460', and remaining EMI shielding 1163. EMI shield 1460 covers unit portion 1011, including capsule top surface 942, capsule lateral surface 943, substrate lateral surface 913, and capsule lateral surface 1453. EMI shield 1460' covers corresponding components of unit portion 1012. The remaining EMI shielding 1163 covers the sidewalls of the primary strap portion 1191 , the sidewalls of the primary strap portion 1192 , and the secondary strap 1195 . In this example, secondary strap 1195 is covered by remaining EMI shielding 1163 where it is exposed by primary strap portion 1191 or 1192 , including over the gap that separates primary strap portion 1191 from primary strap portion 1192 .

Such a configuration provides advantages similar to those described above with respect to FIG. 11E , such that the thickness of the EMI shielding layer 1160 does not bulge, but is instead maintained at the edge 1454 of the encapsulation and across the main adhesive of the main strap portion 1191 . The interface remains essentially unchanged.

As shown in Figure 15D with EMI shielding layer 1160 applied, cell portion 1011 can be pulled from main strap portion 1191, leaving encapsulation bottom surface 1452 and interconnect distal portion 1482, and taking EMI shielding 1460 with them Semiconductor package 1400 is produced (Figure 14). During this removal, primary tape portion 1191 remains attached to secondary tape 1195 and EMI shielding layer 1160 breaks precisely along its interface with the primary adhesive of primary tape portion 1191 , thereby separating EMI shielding 1460 from the remaining EMI. Shield 1163 apart. Cell portion 1012 can similarly be pulled from primary tape portion 1192 such that remaining EMI shielding 1163 remains attached to primary tape portions 1191 and 1192 and to secondary tape 1195 .

The characteristics of the primary band 1190 and the secondary band 1195 remain as shown above with respect to Figure 11E to achieve a fixed thickness and controlled rupture of the EMI shielding layer 1160, thereby allowing increased and consistent coverage of the encapsulation lateral surface 1453. Therefore, an exposure height of no more than 0 to 50 μm measured from the capsule bottom surface 1452 and along the capsule lateral surface 1453 is exposure from the EMI shield 1460 . This avoids the problem of the EMI shielding layer 1160 breaking through the encapsulation peripheral edge 1454, leaving an overhanging portion of the EMI shielding 1460, and also avoids the EMI shielding layer 1160 from excessively breaking above the encapsulant peripheral edge 1454, leaving the capsule laterally. Surface 1453 shields 1460 from EMI issues that are overexposed.

Figure 16 illustrates a cross-sectional view of a semiconductor package 1600 according to one example. Semiconductor package 1600 and its elements may be similar to any one or more of the other semiconductor packages or their corresponding elements described herein, and the characteristics of semiconductor package 1600 are further described below. For example, semiconductor package 1600 may be related to semiconductor package 900 described above, which includes substrate 910, electronic devices 920, 9201, 9202, and 970, passive components 931, 932, and 933, and encapsulation 940, and each corresponding parts and components, as well as other corresponding features or elements described above with respect to semiconductor package 900 . There may be embodiments in which the semiconductor package 1600 may include different combinations of these elements.

Semiconductor package 1600 may also include external interconnects 1480, as described above with respect to Figures 14-15. Although external interconnect 1480 is shown as a single bump, embodiments may include different configurations, such as dual stacked bumps.

Semiconductor package 1600 may also include an encapsulation 1650, which in this example is similar in some respects to encapsulation 950 (Figs. 9, 11) described above, as well as its individual components and portions. However, the difference of the encapsulation 1650 of this embodiment is that it encapsulates the gap between the bottom surface 912 of the substrate and the device surface 971 of the electronic device 970 as well as the bumps of the electronic device 970, unlike separated by 1480 external interconnects. In this example, the encapsulant 1650 also extends partially along the device lateral surface 973 , and there may be examples where the encapsulant 1650 may further completely cover the device lateral surface 973 and/or the device surface 972 of the electronic device 970 .

Encapsulation 1650 may include one or more materials, such as epoxy, thermoplastic materials, heat curable materials, polyimide, polyurethane, polymeric materials and/or related encapsulation materials 950 of one or more of the materials described above. In some examples, the encapsulation 1650 may be referred to as an underfill, such as a capillary underfill, where flow is due to capillary action, or a molded underfill, which occurs during the molding process. injected or otherwise applied. There are also other examples where the encapsulation 1650 can be a pre-applied underfill, such as a non-conductive paste (NCP) or a non-conductive film (NCF), which can be applied before coupling to the electronic device 970 Application (e.g., printing, spraying, gluing).

Figure 16 further shows an electromagnetic interference (EMI) shield 1660, which is similar to EMI shield 960 as described above. EMI shield 1660 covers capsule top surface 942 and capsule lateral surface 943 of capsule 940 and substrate lateral surface 913 of substrate 910 .

In this example, the semiconductor package 1600 also includes a compartment shield 1690, which is similar to the compartment shield 990 described above, which may be an EMI shield constructed to provide EMI in the compartment area surrounding one or more components. Protection, the one or more components are, for example, electronic device 970 . The compartment shield 1690 is defined by the compartment side walls 1691 and the compartment bottom barrier 1692. In this example, the compartment shield 1690 consists of a continuous piece of material that surrounds both the device surface 972 and the device surface 973 of the electronic device 970. In some examples, compartment shield 1690 may include a metal can or cover. In other examples, such as where encapsulation 1650 completely covers device lateral surface 973 and device surface 972 of electronic device 970 , compartment shield 1690 may be one or more wires that run from one side of electronic device 970 to a different side. It is wire bonded to the substrate bottom surface 912 as a wire cage. However, examples may exist where compartment shield 1690 may be similar to compartment shield 990 with compartment sidewalls 991 and compartment bottom barrier 992 of different or discontinuous materials.

Semiconductor package 1600 may be assembled through various stages of assembly, including initial stages of assembly as shown in FIGS. 10A through 10C. Figures 17A-17C illustrate various backend stages that continue the assembly of Figures 10A-10C and ultimately form semiconductor package 1600 (Figure 16).

Figure 17A depicts the later stages of assembly for semiconductor package 1600 (Figure 16). External interconnect 1480 is coupled and includes an interconnect interior 1481 proximate to substrate 910 and an interconnect distal portion 1482 remote from substrate 910 . The compartment shield 1690 is also shown coupled to the substrate bottom surface 912 surrounding the electronic device 970, but there may be embodiments in which the compartment shield 1690 may be attached at a later stage, if desired.

Figure 17B depicts subsequent stages of assembly, which are similar to the stages of Figure 11D, but for semiconductor package 1600 (Figure 16). Primary tape 1190 is shown attached, with the primary adhesive of primary tape 1190 being sealed to substrate bottom surface 912 of substrate 910 , and to external interconnects 1480 . The main tape 1190 includes a main tape part 1191 adhered under the unit part 1011 and a main tape part 1192 adhered under the unit part 1012 . External interconnect 1480 and electronics 970 protrude into primary strip 1190 such that both are completely buried within the primary adhesive of primary strip 1190 .

After attachment of the primary strip 1190 , the unit portion 1011 and the unit portion 1012 can be separated from each other along the dotted line singulated through the encapsulation 940 shown in FIG. 17B , through the substrate 910 and through the primary band 1190 open. The singulation defines an encapsulation peripheral edge 914 of the cell portion 1011 at the juncture of the substrate bottom surface 912 and the substrate lateral surface 913 . After singulation, the primary tape portion 1191 remains attached to the unit portion 1011 with its primary adhesive still hermetically sealed to the bottom of the capsule bottom surface 1452 and to the capsule peripheral edge 1454.

Figure 17C presents subsequent stages of assembly that are similar to those of Figure 11E, but for semiconductor package 1600 (Figure 16). Unit portion 1011 and unit portion 1012 are attached to secondary adhesive of secondary tape 1195 . The secondary belt 1195 can be supported by the carrier structure, and the unit portions 1011 and 1012 along with the corresponding primary belt portions 1191 and 1192 can be picked and placed adjacent to each other on the secondary belt 1195 such that each primary belt portion 1191 And the bottom of 1192 is sealed to the secondary tape 1195 of the secondary adhesive. The secondary strip 1195 is exposed to a gap that separates the primary strip portions 1191 and 1192 and separates the unit portions 1011 and 1012 from each other.

When the pick and place operation is completed, EMI shielding layer 1160 is applied. In this example, EMI shielding layer 1160 is applied as a continuous coating, which includes EMI shielding 1660, EMI shielding 1660' and remaining EMI shielding 1163. EMI shield 1660 covers unit portion 1011, including encapsulation top surface 942, encapsulation lateral surface 943, and substrate lateral surface 913. EMI shield 1660' covers corresponding components of unit portion 1012. The remaining EMI shielding 1163 covers the sidewalls of the primary strap portion 1191 , the sidewalls of the primary strap portion 1192 , and the secondary strap 1195 . In this example, secondary strap 1195 is covered by remaining EMI shielding 1163 where it is exposed by primary strap portion 1191 or 1192 , including over the gap that separates primary strap portion 1191 from primary strap portion 1192 .

Such a configuration provides advantages similar to those described above with respect to FIG. 11E such that the thickness of the EMI shielding layer 1160 does not bulge, but rather at the interface of the primary adhesive at the peripheral edge 914 of the substrate and across the primary tape portion 1191 Remain substantially unchanged.

In particular, because the sidewalls of the main strap portion 1191 are coplanar with the substrate lateral surface 913, the EMI shielding layer 1160 does not curve at the substrate peripheral edge 914, but is substantially continuous from the substrate lateral surface 913 to the sidewalls of the main strap portion 1191. Straight plane. Without such bending, which typically occurs if the interface between primary strip 1190 and substrate lateral surface 913 is instead at a right angle, EMI shielding layer 1160 does not accumulate or bulge adjacent substrate peripheral edge 914 . Therefore, the thickness of the EMI shielding layer 1160 remains substantially constant at the substrate peripheral edge 914 and at the interface of the primary adhesive across the primary tape portion 1191 .

With EMI shielding layer 1160 applied as shown in FIG. 17C , cell portion 1011 can be pulled from main tape portion 1191 , leaving substrate bottom surface 912 and external interconnects 1480 , and taking EMI shielding 1660 with it to create semiconductor package 1600 (Figure 16). During this removal, primary tape portion 1191 remains attached to secondary tape 1195 and EMI shielding layer 1160 breaks precisely along its interface with the primary adhesive of primary tape portion 1191 , thereby separating EMI shielding 1660 from the remaining EMI. Shield 1163 apart. Unit portion 1012 may similarly be pulled from primary strap portion 1192 such that remaining EMI shielding 1163 remains attached to primary strap portions 1191 and 1192 and to secondary strap 1195 . In certain embodiments, compartment shielding 1690 may be applied after removal of unit portion 1011 from main belt portion 1191 .

The characteristics of the primary strip 1190 and the secondary strip 1195 remain as shown above with respect to FIG. 11E to achieve a fixed thickness and controlled rupture of the EMI shielding layer 1160 , thereby allowing increased and consistent coverage of the substrate lateral surface 913 . Therefore, an exposure height of no more than 0 to 50 μm measured from the substrate bottom surface 912 and along the substrate lateral surface 913 is exposure from the EMI shield 1660 . This avoids the problem of the EMI shield 1160 breaking through the substrate peripheral edge 914 , leaving an overhanging portion of the EMI shield 1660 , and also avoids the problem of the EMI shield 1160 breaking excessively over the substrate peripheral edge 914 , leaving the substrate lateral surface 913 free from the EMI shield 1660 The problem of being overexposed.

Figure 18 illustrates a cross-sectional view of a semiconductor package 1800 according to one example. Semiconductor package 1800 and its components may be similar to any one or more of the other semiconductor packages or their corresponding components described herein, and the characteristics of semiconductor package 1800 are further described below. For example, semiconductor package 1800 may be related to semiconductor package 900 described above, which includes substrate 910, electronic devices 920, 9201, 9202, and 970, passive components 931, 932, and 933, and encapsulation 940, and each corresponding parts and components, as well as other corresponding features or elements described above with respect to semiconductor package 900 . There may be embodiments in which the semiconductor package 1800 may include different combinations of these elements. The methods used to construct the features of semiconductor package 1800 may also be similar to the methods used to construct corresponding features of one or more of the other semiconductor packages described herein.

Semiconductor package 1800 includes electronic device 1875 coupled between electronic device 970 and substrate 910 . Electronic device 1875 may be similar to electronic device 970, as shown in Figure 18, but there may also be embodiments in which electronic device 1875 may be similar to passive device 933, for example. Electronic device 1875 is coupled to device surface 971 of electronic device 970 using flip chip bumps in this example.

Semiconductor package 1800 also includes electronic device 1876 coupled between electronic device 970 and substrate 910 . Electronic device 1876 may be similar to electronic device 1875, but in this example it is coupled to substrate bottom surface 912. There are also examples where the electronic device 1875 and/or the electronic device 1876 may be omitted.

Semiconductor package 1800 may also include external interconnects 1480, which in this example appear as solder balls. As described above, external interconnect 1480 may be similar to external interconnect 980, including any of the interconnect options described for external interconnect 980 or any other external interconnect described herein. For example, semiconductor package 1800 includes external interconnect 1880 , also similar to external interconnect 980 , but in accordance with one of the interconnect options described for external interconnect 980 , external interconnect 1880 appears as a metal pillar with a solder tip. .

Semiconductor package 1800 further includes an EMI shield 1460, a compartment shield 990, and an encapsulation 1850, which may be similar to one or more of the corresponding bottom encapsulation described herein. There may be other examples in which one or more of such elements may be omitted or substituted. For example, one example may omit encapsulant 1850 and/or EMI shield 1460 may be replaced with a shield similar to EMI shield 1660 (Figures 16-17). The same or other examples may omit compartment shield 990, or may replace compartment shield 990 with a compartment shield similar to compartment shield 1690 (Figures 16-17).

Figure 19 illustrates a cross-sectional view of a semiconductor package 1900 according to one example. Semiconductor package 1900 is similar to semiconductor package 1800 (FIG. 18), but includes a substrate 1910. Substrate 1910 may be similar to substrate 910 but include substrate recesses 1919 into which one or more components may be coupled to further reduce the height of package 1900 . The substrate bottom section 1912 of the substrate 1910 defines the base of the substrate pocket 1919 and may be considered a portion of the substrate bottom surface 912 . In this example, electronic devices 970, 1875, 1876 and passive member 933 may be inserted into substrate cavity 1919, but there may be other examples in which one or more components may not be inserted therein. There may be other examples in which at least a portion of one or more of the interposed components may protrude outside of the substrate pocket 1919 . Substrate pocket 1919 is at least partially filled with encapsulation 1950 , which may be similar to encapsulation 1850 but extend only below substrate bottom surface 912 . Encapsulation 1950 at least partially encapsulates the component inserted into substrate cavity 1919, but other embodiments are possible in which encapsulation 1950 may be omitted. Semiconductor package 1900 is also shown with compartment shield 1690 within substrate cavity 1919, but other embodiments are possible in which compartment shield 1690 may be omitted or constructed with a compartment shield similar to compartment shield 990. replace.

Figure 20 illustrates a cross-sectional view of a semiconductor package 2000 according to one example. Semiconductor package 2000 is similar to semiconductor package 1800 (FIG. 18), but includes substrate 2010 coupled to substrate top surface 911 of substrate 910. Substrate 2010 may be similar to substrate 910 but includes substrate apertures 2019 that extend through the thickness of substrate 2010 and that at least partially surround a portion of one or more components of semiconductor package 2000 . For example, electronic devices 920, 9201, and 9202 may be confined within substrate aperture 2019, and thus may protrude further from substrate 910 than the bottom surface of substrate 2010. Substrate top surface 2011 of substrate 2010 may be used to couple additional components of semiconductor package 2000, such as electronic device 2020, which may be similar to electronic device 920, or passive member 2030, which may be similar to passive members 931, 932, or 933. . In this example, substrate 2010 is coupled to substrate 910 via interconnect 2080, which may be similar to interconnect 1480 or one or more of the interconnects described herein. Passive member 932 is shown between substrate 910 and substrate 2010 and, in this example, includes terminals 9321 and 9322 that each contact the top of substrate 910 and the bottom of substrate 2010 . Terminal 9321 and/or terminal 9322 of passive member 932 may be used as an interconnect similar to, combined with, and/or in place of interconnect 2080 to pass signals or voltages between substrate 910 and substrate 2010 .

Figure 21 illustrates a cross-sectional view of a semiconductor package 2100 according to one example. Semiconductor package 2100 is similar to semiconductor package 2000 ( FIG. 20 ), but includes substrate 2110 coupled to substrate top surface 911 of substrate 910 . The substrate 2110 may be similar to the substrate 910 but leaving a substrate gap 2119 open above the substrate 910 from the lateral surface of the substrate 2110 to the encapsulate lateral surface 943. Substrate gap 2119 may at least partially surround a portion of one or more components of semiconductor package 2100 . For example, electronic devices 920 and 9202 are confined within substrate gap 2119 and, therefore, may protrude further from substrate 910 than the bottom surface of substrate 2110 . The substrate top surface 2111 of the substrate 2110 may be used to couple additional components of the semiconductor package 2100, such as the electronic device 2020 or the passive component 2030. In this example, substrate 2110 is coupled to substrate 910 via interconnect 2080 . Passive member 932 is shown between substrate 910 and substrate 2110 with at least terminal ends 9321 of passive member 932 contacting the top of substrate 910 and the bottom of substrate 2010 . Accordingly, at least terminals 9321 of passive member 932 may be used as an interconnect similar to, combined with, and/or in place of interconnect 2080 to pass signals or voltages between substrate 910 and substrate 2110 .

Figure 22A illustrates a cross-sectional view of a semiconductor package 2200 according to one example. Figure 22B illustrates an enlarged portion of semiconductor package 2200 from Figure 22A. Semiconductor package 2200 and its elements may be similar to any one or more of the other semiconductor packages or their corresponding elements described herein, and the characteristics of semiconductor package 2200 are further described below. For example, semiconductor package 2200 may be related to semiconductor package 900 including substrate 910 , electronic devices 920 , 9201 , 9202 , and 970 , passive components 931 , 932 , and 933 , and encapsulation 940 , as well as corresponding portions and components of each. , as well as other corresponding features or elements described above with respect to semiconductor packages. There may be embodiments in which semiconductor package 2200 may include different combinations of these elements.

The semiconductor package 2200 also includes a second pad 9122 coupled to the bottom of the substrate, which may also be referred to as an interconnect pad. Interconnect 2280 includes interconnect internal 2281 and interconnect remote portion 2282, which may be correspondingly similar to external interconnect 980, interconnect internal 981, and interconnect remote portion 982 described above. Additionally, semiconductor package 2200 includes encapsulation 2250, which may be similar to encapsulation 950 described above and its individual components and portions. Interconnect 2280 includes interconnect protrusions 2287 that protrude through capsule bottom surface 2252.

Encapsulation 2250, shown at FIG. 22, encapsulates the substrate bottom surface 912, as well as any components coupled to the substrate bottom surface 912, including electronics 970 and passive components 933. In this example, encapsulant 2250 is shown covering the lateral surfaces of both electronic device 970 and passive member 933 as well as the bottom surface of passive member 933, leaving the bottom surface of electronic device 970 exposed. In some embodiments, the encapsulation 2250 may also leave the bottom surface of the passive member 933 exposed. Encapsulation 2250 may surround outer interconnect 2280, leaving end portions 2282 of outer interconnect 2280 exposed by encapsulation 2250, and leaving interconnect protrusions 2287 protruding from encapsulation bottom surface 2252.

Figure 22 includes an enlarged view showing details of external interconnect 2280, encapsulation 2250, and electronic device 970 relative to each other. In this example, the encapsulation bottom surface 2252 is coplanar with the device bottom surface 972 of the electronic device 970 . Encapsulation 2250 may also contain vias 2255 that limit interconnects 2280 . In this example, via 2255 includes via wall 2256 and via flange 2257, but other examples are possible where via flange 2257 may be omitted such that the inner end of via wall 2256 would contact interconnect 2280.

Figure 22 further shows an electromagnetic interference (EMI) shield 2260, which is similar to the EMI shield 960 described above. EMI shield 2260 covers capsule top surface 942 and capsule lateral surface 943 of capsule 940 , as well as substrate lateral surface 913 of substrate 910 . In this example, EMI shield 2260 also covers encapsulation lateral surface 2253 of encapsulation 2250 and leaves at least a portion of encapsulation bottom surface 2252 exposed such that EMI shield 2260 remains separated from external interconnects 2280 .

In this example, the semiconductor package 2200 also includes a compartment shield 990 having compartment sidewalls 991 and a compartment bottom barrier 992, which as previously described may be an EMI shield, configured to operate within the electronics circuit containing one or more components, such as Device 970, provides EMI protection within the compartment area. In this example, because the device bottom surface 972 of the electronic device 970 is exposed, the compartment bottom barrier 992 may be formed on and/or may contact the exposed device bottom surface 972 . In other examples, a dielectric layer other than encapsulation 2250 may be provided to the exposed device surface 972 and a compartment bottom barrier 992 may then be formed over the dielectric layer.

The semiconductor package 2200 may be assembled through various stages of assembly, including the initial stages of assembly as shown in FIGS. 10A through 10C. Figures 23A-23E illustrate various backend stages that continue the assembly of Figures 10A-10C and ultimately form semiconductor package 2200 (Figure 22).

Figure 23A depicts stages of an assembly similar to that of Figure 13A, but for semiconductor package 2200 (Figure 22). The interconnection inner portion 2281 of the external interconnect 2280 is attached to the substrate bottom surface 912 at the cell portion 1011 , and the interconnection inner portion 2281 ′ is attached to the substrate bottom surface 912 at the cell portion 1012 . Figure 23A also shows encapsulant 2250 applied across and between cell portions 1011 and 1012 to encapsulate substrate bottom surface 912 and all components coupled thereto, including electronics. Devices 970 and 970', passive members 933 and 933', and interconnecting interior portions 2281 and 2281''. 23A further illustrates compartment lateral barriers 991 and 991' attached to the substrate bottom surface 912 adjacent the perimeter of the respective electronic devices 970 and 970' and encapsulated by the encapsulant 2250.

In this example, electronic device 970 includes a device initial thickness (measured from device surface 971 to device initial bottom 2379 when initially coupled to substrate bottom surface 912 ). This initial device thickness is thicker than the final device thickness of electronic device 970, as shown in Figure 22 (measured from device surface 971 to device surface 972). As will be explained further below, this initial device thickness is later reduced to minimize the overall thickness of semiconductor package 2200. Accordingly, electronic device 970 may be more safely handled and operated with a greater and structurally more robust initial thickness of the device before and during coupling to substrate bottom surface 912 . This reduces the risk of damage, breakage, and/or yield loss that may occur if the electronic device 970 is similarly processed with a thinner and less structurally resilient device final thickness. In some examples, the initial thickness of the device or electronic device 970 may be 125 µm to 175 µm, such as about 150 µm. In some or other examples, the device initial thickness may include the thickness of the semiconductor wafer on which electronic device 970 is formed. Electronic device 970 may be coupled to substrate 910 via respective bumps, which may define a bump gap of between 30 µm and 50 µm, such as approximately 40 µm, between device surface 971 and substrate bottom surface 912 .

Encapsulation 2250 is applied to completely encapsulate interconnect 2280 , electronic device 970 , and passive component 933 . Thus, encapsulation initial bottom 2359 extends beyond interconnect initial bottom 2389 and device initial bottom 2379 and has a greater height (measured from substrate bottom surface 912) than interconnect initial bottom 2389 and device initial bottom 2379. Once attached to the substrate bottom second pad 9122, the initial height of the interconnect 2280 measured at the initial bottom of the interconnect 2389 may be between 140 µm and 170 µm, such as approximately 150 µm. The height of the device initial bottom 2379, which is defined by the bumps and the device initial thickness of the electronic device 970, may be between 165 µm and 215 µm, such as about 190 µm. Therefore, the height of device initial bottom 2379 may be greater than the height of interconnect initial bottom 2389.

Figure 23B depicts subsequent assembly stages similar to Figure 13B, but for semiconductor package 2200 (Figure 22). Encapsulation 2250 is partially removed or thinned to expose the bottom of interconnect interior portions of interconnect 2280 and the device bottom surface 972 of electronic device 970 . The thinning or planarization process reduces the thickness of encapsulation 2250, interconnects 2280, and electronic device 970 until encapsulation bottom surface 2252, interconnect mid-surface 2289, and device bottom surface 972 are exposed at the required minimum height and until they are flush with each other. In some embodiments, planarization may involve a mechanical grinding process and/or one or more etching stages. In this example, the planarization also reveals the bottom of the compartment lateral barrier 991.

Accordingly, the electronic device 970 may be thinned to its final device thickness during the thinning process while being supported by the substrate 910 and encapsulated by the encapsulant 2250, thereby allowing the height of the device bottom surface 972 to be adjusted relative to the substrate bottom surface 912. Minimization of reinforcement. In contrast, if electronic device 970 must be pre-thinned to the same extent before being processed and coupled to substrate bottom surface 912, such enhanced height minimization is not practical without unacceptable risk of damage or not possible.

In some examples, after the thinning process, the height of device bottom surface 972, encapsulation bottom surface 2252, and interconnect intermediate surface 2289 may be between 90 µm and 110 µm, such as approximately 100 µm. In the same or other examples, after the thinning process, the final device thickness of the electronic device 970 is minimized such that its device lateral surface 973 can be between 50 µm and 65 µm, such as about 60 µm. This final thickness of the device represents a thickness reduction of at least 60% and even up to 71% compared to the initial thickness of the device without compromising the integrity of the electronic device 970. This thinning process may allow the final device thickness of the electronic device 970 to be safely minimized, for example, to up to twice the height of the bump gaps defined by the bumps. In the same or other examples, this thinning process may allow electronic device 970 to be safely minimized to the extent that device lateral surface 923 of electronic device 920 may be vertically at least approximately 1.6 times larger than device lateral surface 973 of electronic device 970 . In the same or other examples, this thinning process may allow electronic device 970 to be safely minimized to the extent that substrate lateral surface 913 may be vertically at least approximately 2 times larger than device lateral surface 973 .

Figure 23C depicts subsequent assembly stages similar to Figure 11B, but for semiconductor package 2200 (Figure 22). Vias 2255 are formed into encapsulation bottom surface 2252 and extend toward substrate bottom surface 912 . In some examples, vias 2255 may be formed by laser ablation, by mechanical ablation, and/or by etching ablation into encapsulation 2250 . Accordingly, via wall 2256 is formed to extend from encapsulation bottom surface 2252 toward substrate bottom surface 912 , with via wall 2256 defining a volume of interconnect bounded section 2286 surrounding interconnect 2280 . In this example, after ablation, via wall 2256 remains separated from interconnect surrounding section 2286.

As can also be seen in this example, ablation may define the diameter of via wall opening 22561 to be larger than the diameter of via wall base 22562. Additionally, in this example, via wall 2256 does not extend all the way to substrate bottom surface 912 . In contrast, the ablation may define a via land 2257 extending from the interconnect 2280 to the via wall base 2252, wherein the via land 2257 defines a via land plane, which may be substantially parallel to the encapsulation Bottom surface 2252. Accordingly, the interconnect 2280 may include an interconnect encapsulated section 2285 that is encapsulated into contact with the encapsulation 2250 between the via land plane and the substrate bottom surface 912 .

The compartment bottom barrier 992 is shown applied after the planarization process, covering the area beneath the electronic device 970 and in contact with the exposed bottom of the compartment lateral barrier 991 . In some examples, a layer of dielectric material may also be applied between the area beneath the electronic device 970 and the compartment bottom barrier 992 . If required, the application of the barrier at the bottom of the compartment can be carried out at a later stage. In other examples, compartment shield 990 and/or compartment bottom barrier 992 may be omitted.

Figure 23D depicts subsequent assembly stages similar to Figure 13C, but for semiconductor package 2200 (Figure 22). The interconnect distal portion 2282 is coupled to the interconnect intermediate surface 2289 of the interconnect interior portion 2281 (as exposed by the process of Figures 23B-C), and thus protrudes beyond the encapsulation bottom surface 2252. In some examples, interconnect distal portion 2282 may be applied using a solder drop or ball drop process, a screen printing process, or a plating process. In the same or other examples, interconnect distal portion 2282 may be at least partially resoldered once attached.

In this example, the volume of the interconnection inner portion 2281 is greater than the volume of the interconnection distal portion 2282 such that the perimeter of the interconnection distal portion 2282 is enclosed within the area of the interconnection intermediate surface 2289 . Therefore, the material of the interconnect distal portion 2282 tends not to spill into the via 2255 such that the separation between the via wall 2256 and the interconnect surrounding section 2286 remains.

Figure 23E presents the stages of subsequent assembly for the semiconductor package 2200 (Figure 22). Interconnect inner portion 2281 and interconnect distal portion 2282 are shown reflowed to each other, with their respective volumes combining to define the final interconnect volume and height of interconnect 2280 with interconnect protruding section 2287 protruding beyond the bottom of the capsule Surface 2252 is at least 50 µm to allow for proper clearance when connecting to external substrates or devices. In particular, the interconnect distal portion 2282 implemented in Figure 23D can be configured such that when the interconnect interior portion 2281 in Figure 23E is reflowed, the final volume and/or height of the interconnect 2280 can be the same as that originally implemented in Figure 23A The initial volume and/or height of interconnect 2280 is substantially the same or similar, or within 5%.

The spacing between via wall 2256 and interconnect surrounding section 2286 allows interconnect inner portion 2281 and interconnect distal portion 2282 to be freely reflowed to each other during the reflow process. This feature reduces stiction that would otherwise deform or limit the final shape and height of interconnect 2280, and limits any "blow up" or eruption of the material of interconnect 2280 when impacted by the bottom of the encapsulation. This would tend to occur through pressure ejection) due to the constraints of otherwise narrower apertures in surface 2252). This feature also allows for closer spacing between adjacent interconnects 2280. For example, less than half of the initial height of interconnect 2280 may be thinned in Figure 23B, leaving at least half of its initial volume and height still encapsulated as via 2255 expands later in Figure 23C. Narrow capsule holes create the explosion problem. Therefore, when interconnect 2280 is applied in Figure 23A, a smaller interconnect diameter may be used initially, resulting in tighter interconnect spacing. However, if desired, a larger initial diameter interconnect 2280 may be used, and/or this interconnect may be thinned to more than half the initial height of interconnect 2280 in Figure 23B while still benefiting from the reduction in stiction.

Further stages of assembly may be performed to produce a package 2200 as shown in FIG. 22 by any process similar to, for example, that described above for any EMI shielding described herein (eg, FIGS. 11D to 1E for EMI shielding). ) to form the EMI shield 2260 during the manufacturing process.

The discussion herein includes a number of illustrative figures illustrating various portions of electronic package assemblies and methods of manufacturing them. For clarity of illustration, these figures do not show all aspects of each example component. Any example component and/or method presented herein may share any or all characteristics with any or all other example components and/or methods presented herein.

In summary, various aspects of the present disclosure provide semiconductor packages and methods of manufacturing semiconductor packages. By way of non-limiting example, aspects of the present disclosure provide semiconductor packages and methods of fabrication that include shielding on multiple sides thereof. Although certain aspects and examples have been described above, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. For example, to provide sufficient volume to encapsulate the respective protruding portions of interconnect 980 (Figs. 9, 11), interconnect 1280 (Figs. 12, 13), or interconnect 1480 (Figs. 14-21) within primary strip 1190 Within the primary adhesive, the thickness of the primary adhesive may vary as desired to be greater than the protruding interconnection portion, and is typically greater than the thickness of the base layer of the primary strip 1190 . Because the second adhesive of second strip 1195 does not encapsulate these different interconnections, its thickness does not need to change from example to example and/or can remain thinner than the thickness of the primary adhesive of primary strip 1190 .

Therefore, it is intended that this disclosure not be limited to the particular example(s) disclosed, but that this disclosure will include all examples falling within the scope of the appended claims.

10: Fixture 11:Internal space 12: Plane part 20: Fixture 21: Groove 22:hole 100:Semiconductor packaging 110:Substrate 110a: Surface 110b: Surface 111: Line pattern 112: Line pattern 113:Conduction Pattern 120: Electronic devices 121:Semiconductor grain 122: Passive component 130: Electronic devices 140:Molded objects 150:Molded objects 150b: Bottom surface 160: Conductive bump 170:Conduction bump 180: Electromagnetic interference (EMI) shielding layer 200:Semiconductor packaging 280:EMI shielding layer 280a:Exposed hole 900:Semiconductor packaging 910:Substrate 911: Top surface of substrate 912:Bottom surface of substrate 913: Lateral surface of substrate 914: Edge around substrate 920:Electronic devices 920’: Electronic devices 921:Device surface 922:Device surface 923: Transverse surface of device 931: Passive component 931’: Passive component 932: Passive component 932’: Passive component 933: Passive component 933’: Passive component 940: Encapsulation 942: Top surface of encapsulation 943: Transverse surface of encapsulation 950: Encapsulation 952: Bottom surface of encapsulation 953: Transverse surface of encapsulation 954: Peripheral edge of encapsulation 954’: Peripheral edge of capsule 955:Through perforation 960:EMI shielding 960’: EMI shielding 970:Electronic devices 970’: Electronic devices 971:Device surface 972:Device surface 973: Transverse surface of device 980:External interconnection 981:Interconnect internal parts 981’:Interconnect internal part 982: Interconnect remote part 985:Interconnect encapsulation part 986: Exposed portion of interconnect 987:Interconnect protrusion 990: Compartment shielding 990’: Compartment shielding 991: Compartment lateral barrier 991’: Compartment lateral barrier 992: Compartment bottom barrier 992’: Compartment bottom barrier 1011:Unit part 1012:Unit part 1160:EMI shielding layer 1160’: EMI shielding layer 1163:EMI shielding 1190: Main band 1191: Main belt part 1192: Main belt part 1195: Secondary zone 1200:Semiconductor packaging 1250: Encapsulation 1252: Bottom surface of encapsulation 1253: Transverse surface of encapsulation 1254: Edge around the capsule 1260:EMI shielding 1260’: EMI shielding 1280:Interconnection 1281:Interconnection internal 1281’: Inside the interconnect 1282:Interconnecting the remote part 1282’: Interconnecting the remote part 1286: Exposed portion of interconnect 1286’: Exposed portion of interconnect 1400:Semiconductor packaging 1450: Encapsulation 1452: Bottom surface of encapsulation 1453: Transverse surface of encapsulation 1454: Edge around the capsule 1459:skirt 1460:EMI shielding 1460’: EMI shielding 1480:External interconnection 1480’: External interconnection 1481:Interconnection internal 1481’: Inside the interconnect 1482:Interconnecting the remote part 1482’: Interconnecting the remote part 1550: Gap 1590:Thin film 1600:Semiconductor packaging 1650: Encapsulation 1660:EMI shielding 1690: Compartment shielding 1800:Semiconductor packaging 1850:Encapsulation 1875:Electronic devices 1876:Electronic devices 1880:External interconnection 1900:Semiconductor packaging 1950: Encapsulation 2000:Semiconductor packaging 2010:Substrate 2011:Substrate top surface 2019: Substrate holes 2020: Electronic devices 2030: Passive components 2080:Interconnection 2100:Semiconductor packaging 2110:Substrate 2111:Substrate top surface 2200:Semiconductor packaging 2250: Encapsulation 2252: Bottom surface of encapsulation 2253: Transverse surface of encapsulation 2255:Through hole 2256:Through hole wall 2257:Through hole table 2260:EMI shielding 2280:Interconnection 2280’: Interconnect 2281:Interconnect internal parts 2281’:Interconnect internal part 2282:Interconnecting the remote part 2285: Interconnect Encapsulated Segment 2286: Interconnection Surrounding Segment 2287:Interconnect protruding section 2289:Interconnection intermediate surface 2359: Initial bottom of encapsulation 2379: Initial bottom of device 2389:Interconnect initial bottom 9111: First pad on the top of the substrate 9112: Second pad on top of substrate 9121: The first pad at the bottom of the substrate 9122: Second pad at the bottom of the substrate 9201: Electronic devices 9201’: Electronic devices 9202:Electronic devices 9202’: Electronic devices 9321:Terminal 9322:Terminal 22561:Through hole wall opening 22562:Through hole wall base S10: Method of manufacturing semiconductor package S11: Steps S12: Steps S13: Steps S14: Steps S15: Steps S20: Steps S23: Steps S24: Steps S25: Steps

[Fig. 1] is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[Fig. 2] A flowchart illustrating the method of manufacturing a semiconductor package shown in Fig. 1. [Fig.

[Figs. 3A to 3E] are cross-sectional views showing respective steps for manufacturing the method of manufacturing the semiconductor package shown in Fig. 2. [Figs.

[Fig. 4] is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present disclosure.

[FIGS. 5A and 5B] are cross-sectional views illustrating various steps of manufacturing the semiconductor package shown in FIG. 4 by the semiconductor package manufacturing method shown in FIG. 2.

[Fig. 6] A plan view and a cross-sectional view illustrating the structure of the clamp shown in Fig. 5A.

[FIG. 7] is a flowchart illustrating the method of manufacturing a semiconductor package shown in FIG. 4 according to another embodiment of the present disclosure.

[ FIGS. 8A to 8C ] are cross-sectional views illustrating respective steps for manufacturing the method of manufacturing the semiconductor package shown in FIG. 7 .

[Fig. 9A] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 9B] An enlarged portion illustrating the semiconductor package of Fig. 9A.

[Figures 10A to 10C] illustrate each initial semiconductor package assembly stage.

[Figs. 11A to 11E] Illustrate semiconductor package assemblies after completing each of the semiconductor packages of Fig. 9.

[Fig. 12A] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 12B] An enlarged portion of the semiconductor package of Fig. 12A is illustrated.

[Figs. 13A to 13]E illustrates semiconductor package assemblies that complete each subsequent stage of the semiconductor package of Fig. 12.

[Fig. 14A] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 14B] An enlarged portion of the semiconductor package of Fig. 14A is illustrated.

[Figs. 15A to 15D] Illustrate semiconductor package assemblies in which each rear end of the semiconductor package of Fig. 14 is completed.

[Fig. 16] A cross-sectional view illustrating a semiconductor package according to an example.

Figures [17A to 17C] illustrate respective subsequent semiconductor package assemblies that complete the semiconductor package of Figure 16 .

[Fig. 18] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 19] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 20] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 21] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 22A] A cross-sectional view illustrating a semiconductor package according to an example.

[Fig. 22B] An enlarged portion of the semiconductor package of Fig. 22A is illustrated.

[Figs. 23A to 23E] Illustrate semiconductor package assemblies in which each rear end of the semiconductor package of Fig. 22 is completed.

100:Semiconductor packaging

110:Substrate

110a: Surface

110b: Surface

111: Line pattern

112: Line pattern

113:Conduction Pattern

120: Electronic devices

121:Semiconductor grain

122: Passive component

130: Electronic devices

140:Molded objects

150:Molded objects

150b: Bottom surface

160: Conductive bump

170:Conduction bump

180: Electromagnetic interference (EMI) shielding layer

Claims (20)

A semiconductor package including: Substrate, which includes: The top side of the substrate includes a first pad on the top of the substrate and a second pad on the top of the substrate; The bottom side of the substrate includes a first pad on the bottom of the substrate and a second pad on the bottom of the substrate; and lateral side of substrate; A first electronic device on the top side of the substrate and coupled to a first pad on top of the substrate, wherein the first electronic device includes: a first device bottom side facing the substrate top side; The top side of the first device; and The lateral side of the first device; a second electronic device on the top side of the substrate and coupled to a second pad on top of the substrate; A first encapsulation that encapsulates at least the top side of the substrate, the first electronic device, and the second electronic device, wherein the first encapsulation includes: The bottom side of the first encapsulation object faces the top side of the substrate; The top side of the first capsule; and The lateral side of the first capsule; A third electronic device on the bottom side of the substrate and coupled to the bottom first pad of the substrate, wherein the third electronic device includes: a third device top side facing the bottom side of the substrate; The bottom side of the third device; and third device lateral side; External interconnects, which are on the underside of the substrate and include: an upper interconnect terminal coupled to a second pad on the bottom of the substrate; and lower interconnect terminal; A second encapsulation that encapsulates at least the bottom side of the substrate and the third electronic device, wherein the second encapsulation includes: The top side of the second encapsulation object faces the bottom side of the substrate; The bottom side of the second capsule; and Second encapsulation lateral side. The semiconductor package of claim 1, wherein the lower interconnect end is lower than the bottom side of the second encapsulation. The semiconductor package of claim 1, further comprising an electromagnetic interference (EMI) shield that surrounds at least: The top side of the first encapsulated object; the first encapsulation lateral side; and The lateral side of the substrate, wherein said electromagnetic interference shielding is spaced apart from said external interconnection. The semiconductor package of claim 1, wherein: the substrate includes a substrate cavity, The bottom side of the substrate includes a first part and a second part, the first portion is the lowermost surface of the underside of the substrate, and The second portion defines a base of the substrate pocket. The semiconductor package of claim 4, wherein the third electronic device is on the second portion of the bottom side of the substrate. The semiconductor package of claim 4, wherein the external interconnection is on the first portion of the underside of the substrate. The semiconductor package of claim 4, wherein the second encapsulant encapsulates at least the second portion of the bottom side of the substrate. The semiconductor package of claim 1, further comprising a bottom electromagnetic interference (EMI) shield, the bottom electromagnetic interference shield including a horizontal barrier and a plurality of vertical barriers, wherein: The horizontal barrier is located on the bottom side of the second enclosure, and The plurality of vertical barriers extend through the second encapsulation from the bottom side of the substrate to the horizontal barrier. The semiconductor package of claim 1, further comprising a gap between at least a portion of the external interconnect and the second encapsulation. The semiconductor package of claim 1, wherein the external interconnection includes: an encapsulation section surrounded by and in contact with the first portion of the second encapsulation; an exposed section surrounded by and separate from the second portion of the second enclosure; and A protruding section that is lower than the bottom side of the second capsule. A semiconductor package including: Substrate, which includes: a first side of the substrate including a first pad of the substrate; a second side of the substrate including a second substrate liner and a third substrate liner; and a substrate lateral side extending between said substrate first side and said substrate second side; a first device on the first side of the substrate and coupled to the substrate first pad; A first encapsulation encapsulating at least the first side of the substrate and the first device, wherein the first encapsulation includes: A first side of the first encapsulation facing the first side of the substrate; a first enclosure second side opposite the first enclosure first side; and a first capsule lateral side extending between the first capsule first side and the first capsule second side; a second device on the second side of the substrate and coupled to the substrate second pad; a third device on the second side of the substrate coupled to a third pad of the substrate; and A second encapsulation that encapsulates at least a portion of each of the second side of the substrate, the second device, and the third device, wherein the second encapsulation includes: a first side of a second encapsulation facing the second side of the substrate; a second enclosure second side opposite the second enclosure first side; and A second capsule lateral side extending between the second capsule first side and the second capsule second side. The semiconductor package of claim 11, further comprising an interconnect on said substrate second side and coupled to a substrate interconnect pad on said substrate second side, wherein said Interconnects provide an external interface to the semiconductor package and include: a first interconnect terminal coupled to the substrate interconnect pad; and Second interconnection terminal. The semiconductor package of claim 12, further comprising a gap between at least a portion of the interconnect and the second encapsulation. The semiconductor package of claim 11, wherein: At least one of the first device, the second device, or the third device is an electronic device; and At least one of said first means, said second means or said third means is a passive component. The semiconductor package of claim 11, further comprising an electromagnetic interference (EMI) shield surrounding at least: The first side of the first encapsulated object; the first encapsulation lateral side; and The lateral side of the substrate. The semiconductor package of claim 11, further comprising electromagnetic interference (EMI) shielding, the electromagnetic interference shielding comprising a horizontal barrier and a plurality of vertical barriers, wherein: the horizontal barrier is on the second side of the second enclosure, and The plurality of vertical barriers extend through the second encapsulation from the second side of the substrate to the horizontal barrier. The semiconductor package of claim 16, wherein one of the plurality of vertical barriers is between the second device and the third device. The semiconductor package of claim 16, wherein the horizontal barrier contacts the second encapsulation second side. A semiconductor package including: Substrate, which includes: a first side of the substrate including a first pad of the substrate; a second side of the substrate including a second substrate liner and a third substrate liner; and a substrate lateral side extending between said substrate first side and said substrate second side; a first device on the first side of the substrate and coupled to the substrate first pad; A first encapsulation encapsulating at least the first side of the substrate and the first device, wherein the first encapsulation includes: A first side of the first encapsulation facing the first side of the substrate; a first enclosure second side opposite the first enclosure first side; and a first capsule lateral side extending between the first capsule first side and the first capsule second side; a second device on the second side of the substrate and coupled to the substrate second pad; a third device on the second side of the substrate coupled to a third pad of the substrate; A second encapsulation that encapsulates at least a portion of each of the second side of the substrate, the second device, and the third device, wherein the second encapsulation includes: a first side of a second encapsulation facing the second side of the substrate; a second enclosure second side opposite the second enclosure first side; and a second capsule lateral side extending between the second capsule first side and the second capsule second side; and Electromagnetic interference (EMI) shielding, which includes horizontal barriers and multiple vertical barriers, wherein: the horizontal barrier is on the second side of the second enclosure, and the plurality of vertical barriers extending through the second encapsulation from the second side of the substrate to the horizontal barrier, and One of the plurality of vertical barriers is between the second device and the third device. The semiconductor package of claim 19, wherein the horizontal barrier contacts the second encapsulation second side.