TW202332008A - Sram structure - Google Patents

Abstract

An SRAM layout includes a substrate. A first active region, a second active region, a third active region and a forth active region are disposed on the substrate. A first gate structure includes a first part, a second part and a third part disposed on the substrate. The first part and the third part are perpendicular to the first active region. The second part is parallel to the first active region. The first part covers the first active region, the second active region and the fourth active region. The third part covers the fourth active region. The second part is disposed on an insulating region between the second active region and the fourth active region, and the second part contacts the first part and the third part.

Description

SRAM

The present invention relates to the structure of static random processing memory, in particular to the structure of a ten-transistor (10-T) static random processing memory.

Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as the memory is powered on, the data stored in it can be kept constantly. In contrast, the data stored in the Dynamic Random-Access Memory (DRAM) needs to be updated periodically. However, when the power supply stops, the data stored in SRAM will disappear.

SRAM has the advantage of saving data without refreshing. SRAM units can have different numbers of transistors, usually referred to as the number of transistors, such as six-transistor (6-T) SRAM, eight-transistor (8-T) SRAM, etc. Transistors usually form a data latch used to store bits, and access to transistors can be improved by adding additional transistors. SRAM cells are usually configured as an array with multiple columns and multiple rows. Generally speaking, each column of SRAM cells is connected to a word line, and the word line is used to determine whether the current SRAM cell is selected. Each row of SRAM cells is connected to a bit line or a pair of bit lines, which are used to store bits to and read bits from the SRAM cells.

As the speed requirements of electronic devices increase, there is a need for faster read and write memories.

In view of this, the present invention provides a structure of a ten-transistor SRAM.

According to a preferred embodiment of the present invention, a structure of a SRAM includes a base, a first active area, a second active area, a third active area and a fourth active area are located on the base, Wherein the first active region, the second active region, the third active region and the fourth active region are parallel to each other and are not connected to each other in structure, the third active region, the first active region, the second active region and the fourth active region are separated from the left Arranged in sequence from right to left, a first gate line includes a first part, a second part and a third part, both the first part and the third part are perpendicular to the first active region, and the second part is parallel to the first active region , the first part covers the first active region, the second active region and the fourth active region, the third part covers the fourth active region, the second part is located on an insulating region between the second active region and the fourth active region, and Contact Parts 1 and 3. A second gate line includes a fourth part, a fifth part and a sixth part, the fourth part and the sixth part are perpendicular to the first active region, the fifth part is parallel to the first active region, and the fourth part Covering the first active area, the second active area and the third active area, the sixth part covers the third active area, the fifth part covers the insulating area between the first active area and the third active area and contacts the fourth part and the third active area six parts.

According to another preferred embodiment of the present invention, a structure of SRAM includes a base, a fifth active area, a third active area, a first active area, a second active area, a fourth The active area and a sixth active area are sequentially arranged on the substrate from left to right, wherein the first active area, the second active area, the third active area, the fourth active area, the fifth active area and the sixth active area Parallel to each other, a seventh active region contacts the third active region and the fifth active region, the seventh active region and the fifth active region are perpendicular, an eighth active region contacts the fourth active region and the sixth active region, and the eighth active region Perpendicular to the sixth active area, a first gate line covers the first active area, the second active area and the fourth active area, and a second gate line covers the fourth active area, wherein the second gate line and the first The gate lines are parallel, a third gate line covers the first active area, the second active area and the third active area, and a fourth gate line covers the third active area, wherein the fourth gate line and the third gate The lines are parallel, a first metal wire is electrically connected to the first gate line and the second gate line, wherein the first metal wire is perpendicular to the eighth active region and a second metal wire is electrically connected to the third gate line and the fourth gate polar line, wherein the second metal wire is perpendicular to the seventh active region.

Fig. 1 shows the structure of the SRAM according to the first preferred embodiment of the present invention, and Fig. 2 is a side view along the tangent line I-I' in Fig. 1.

As shown in FIG. 1, a ten-transistor SRAM structure 100 includes a substrate 10, a first active area 12, a second active area 14, a third active area 16, and a fourth active area. Region 18, a fifth active region 20 and a sixth active region 22 are arranged on the substrate 10, the first active region 12, the second active region 14, the third active region 16, the fourth active region 18, the fifth active region 20 and the sixth active region 22 are parallel to each other, the fifth active region 20, the third active region 16, the first active region 12, the second active region 14, the fourth active region 18 and the sixth active region 22 from left to right In addition, an insulating region 24 is used between the first active region 12, the second active region 14, the third active region 16, the fourth active region 18, the fifth active region 20 and the sixth active region 22 to make the first The active region 12 , the second active region 14 , the third active region 16 , the fourth active region 18 , the fifth active region 20 and the sixth active region 22 are not connected to each other in structure.

In addition, a first gate line 26 covers the first active region 12, the second active region 14, the fourth active region 18 and the insulating region 24, and the first gate line 26 is divided into a first part 26a and a second part 26b And a third part 26c, the first part 26a and the third part 26c are both perpendicular to the first active region 12, the second part 26b is parallel to the first active region 12, it is worth noting that: the second part 26b is located in the second active region 12 Both ends of the second portion 26b on the insulating region 24 between the region 14 and the fourth active region 18 are in contact with the first portion 26a and the third portion 26c respectively. The first part 26a continuously covers the first active region 12, the second active region 14, the fourth active region 18 and the insulating region 24 between the first active region 12, the second active region 14, and the fourth active region 18, The third part 26c covers the fourth active region 18 and the insulating region 24 between the second active region 14 and the fourth active region 18, the third part 26c does not cover the second active region 14 and the sixth active region 22, the first part 26a It is not structurally connected to the third part 26c. In addition, the first gate line 26 is a continuous structure.

A second gate line 28 covers the second active region 14, the first active region 12 and the third active region 16, and the second gate line 28 is divided into a fourth part 28a, a fifth part 28b and a sixth part 28c, the fourth part 28a and the sixth part 28c are perpendicular to the first active region 12, the fifth part 28b is parallel to the first active region 12, and the fourth part 28a continuously covers the first active region 12 and the second active region 18 , the third active region 16 and the insulating region 24, the sixth part 28c covers the third active region 16 and the insulating region 24 between the first active region 12 and the third active region 16, but the sixth part 28c does not cover the first The active region 12 and the second active region 14, the fifth part 28b covers the insulating region 24 between the first active region 12 and the third active region 16, and the two ends of the fifth part 28b contact the fourth part 28a and the fourth part 28a respectively. The six parts 28c, the fourth part 28a and the sixth part 28c are not connected structurally, and the second gate line 28 is a continuous structure.

A third gate line 30 covers the sixth active region 22 and the insulating region 24, a fourth gate line 32 covers the sixth active region 22 and the insulating region 24, and a fifth gate line 34 covers the fifth active region 20 and the The isolation region 24 and a sixth gate line 36 cover the fifth active region 20 and the isolation region 24 .

A first pull-down transistor PD21 and a second pull-down transistor PD22 are arranged in the third active region 16, in detail, the sixth part 28c overlapping the third active region 16 is used as the gate of the first pull-down transistor PD21 The fourth part 28a overlapping the third active region 16 is used as the gate electrode of the second pull-down transistor PD22; a third pull-down transistor PD11 and a fourth pull-down transistor PD12 are arranged in the fourth active region 18, overlapping the fourth The first part 26a of the active region is used as the gate electrode of the fourth pull-down transistor PD12, and the third part 26c overlapping the fourth active region is used as the gate electrode of the third pull-down transistor PD11; a first pull-up transistor PU1 is arranged on The first active region 12, overlapping the first part 26a of the first active region 12 is used as the gate of the first pull-up transistor PU1; a second pull-up transistor PU2 is arranged in the second active region 14, overlapping the second active region The fourth part 28a of 14 is used as the gate of the second pull-up transistor PU2. A first passing gate transistor (passing gate transistor) PG1 and a second passing gate transistor PG2 are arranged in the sixth active region 22, and the third gate line 30 overlapping the sixth active region 22 is used as the first passing gate transistor. The gate of the gate transistor PG1; the fourth gate line 32 overlapping the sixth active region 22 is used as the gate of the second passing gate transistor PG2. A third passing gate transistor PG3 and a fourth passing gate transistor PG4 are arranged in the fifth active area 20, and the fifth gate line 34 overlapping the fifth active area 20 is used as the third passing gate transistor PG3 gate; the sixth gate line 36 overlapping the fifth active region 20 is used as the gate of the fourth passing gate transistor PG4.

The substrate 10 is divided into a P-type transistor area A and two N-type transistor areas B, the first pull-up transistor PU1 and the second pull-up transistor PU2 are both in the P-type transistor area A, and the remaining transistors For example, the first pull-down transistor PD21, the second pull-down transistor PD22, the third pull-down transistor PD11, the fourth pull-down transistor PD12, the first pass gate transistor PG1, the second pass gate transistor PG2, the third pass gate transistor Both the pass gate transistor PG3 and the fourth pass gate transistor PG4 are located in the N-type transistor region B. Please refer to Fig. 1 and Fig. 2 at the same time. Since the second part 26b is located in the N-type transistor region B, the structure of the second part 26b of the first gate line 26 will be compatible with all the parts in the N-type transistor region B. The structure of the gate is the same, for example, the structure of the second part 26b will be the same as the structure of the gate of the fourth pull-down transistor PD12; and the fifth part 28b is also in the N-type transistor region B, so the structure of the fifth part 28b The situation will be the same as the second part 26b, that is to say, the structure of the fifth part 28b will be the same as that of all gates in the N-type transistor region B, so please refer to the second part 26b for the structure of the fifth part 28b side view. As shown in Fig. 2, the gate electrode 130 of the fourth pull-down transistor PD12 in the N-type transistor region B (the range of the gate electrode 130 is marked with a dotted line) and the second part 26b (the range of the second part 26b is marked with a dotted line) ) includes a gate dielectric layer 132, an N-type work function layer 134 and a metal gate 138, and the gate 140 of the first pull-up transistor PU1 in the P-type transistor region A (the gate is marked with a dotted line 140) includes a gate dielectric layer 132, an N-type work function layer 134, a P-type work function layer 136 and a metal gate 138, that is to say, the gate in the P-type transistor region A is compared to the gate in the N A P-type work function layer 136 is added to the gate electrode in the P-type transistor region B.

Fig. 3 shows the structure of the static random processing memory 200 according to the second preferred embodiment of the present invention, and Fig. 4 is a side view along the tangent line J-J' in Fig. 3, where the position Components with the same function will continue to use the component numbers in the first preferred embodiment. The difference between the second preferred embodiment and the first preferred embodiment is that the second portion 26b and the fifth portion 28b in the second preferred embodiment are in the P-type transistor region C, while in the first embodiment , the second portion 26b and the fifth portion 28b are in the N-type transistor region B, and the rest of the components in the second preferred embodiment are the same as those in the first preferred embodiment. As shown in Figures 3 and 4, the second part 26b is in the P-type transistor region C, and the first pull-down transistor PD21, the second pull-down transistor PD22, the third pull-down transistor PD11, and the fourth pull-down transistor The crystal PD12 , the first pass gate transistor PG1 , the second pass gate transistor PG2 , the third pass gate transistor PG3 and the fourth pass gate transistor PG4 are all in the N-type transistor region D. The structure of the second portion 26b is the same as that of the gate 140 (marked by a dotted line) of the first pull-up transistor PU1. It can be seen from the first preferred embodiment and the second preferred embodiment that the structure of the second part 26b and the fifth part 28b can be selectively provided with an N-type transistor region or a P-type transistor region according to product requirements, by Adjusting whether the second part 26 b and the fifth part 28 b contains the P-type work function layer 136 can fine-tune the initial voltages of the first pull-up transistor PU1 and the second pull-up transistor PU2 .

FIG. 5 shows the equivalent circuit diagrams of the SRAM in the first preferred embodiment and the second preferred embodiment. As shown in FIG. 5, the drain of the first-pass gate transistor PG1 is electrically connected to the bit line BL11, and the source of the first-pass gate transistor PG1 is electrically connected to the drain of the third pull-down transistor PD11. The gate of the passing gate transistor PG1 is electrically connected to the word line WL1, the source of the third pull-down transistor PD11 is electrically connected to a source voltage Vss, and the drain of the second passing gate transistor PG2 is electrically connected to the word line WL2 , the source of the second passing gate transistor PG2 is electrically connected to the drain of the fourth pull-down transistor PD12, the gate of the second passing gate transistor PG2 is electrically connected to the word line WL2, and the source of the third pull-down transistor PD11 The electrode is electrically connected to the source voltage Vss, the drain of the third pass gate transistor PG3 is electrically connected to the bit line BL12, the source of the third pass gate transistor PG3 is electrically connected to the drain of the first pull-down transistor PD21, The gate of the third pass-gate transistor PG3 is electrically connected to the word line WL1, the source of the first pull-down transistor PD21 is electrically connected to the source voltage Vss, and the fourth pass is electrically connected to the drain of the gate transistor PG4. Line BL22, the source of the fourth pass gate transistor PG4 is electrically connected to the drain of the third pull-down transistor PD11, the gate of the fourth pass gate transistor PG4 is electrically connected to the word line WL2, and the second pull-down transistor PD22 The source is electrically connected to the source voltage Vss.

The drain of the first pull-up transistor PU1, the drain of the third pull-down transistor PD11 and the drain of the fourth pull-down transistor PD12 are electrically connected to each other and electrically connected to a node N1, the gate of the third pull-down transistor PD11, The gate of the fourth pull-down transistor PD12 and the gate of the first pull-up transistor are electrically connected to each other and electrically connected to the node N2, the drain of the second pull-up transistor PU2, and the drain of the first pull-down transistor PD21 and the drain of the second pull-down transistor PD22 are electrically connected to each other and electrically connected to the node N2, the gate of the first pull-down transistor PD21, the gate of the second pull-down transistor PD22 and the gate of the second pull-up transistor PU2 They are electrically connected to each other and to the node N1, and the source of the first pull-up transistor PU1 and the source of the second pull-up transistor PU2 are electrically connected to the drain voltage Vdd. In addition, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD21, the second pull-down transistor PD22, the third pull-down transistor PD11 and the fourth pull-down transistor PD12 form two cross-coupled In the inverter, the first pass gate PG1 and the third pass gate PG3 are used as the first port of the equal cross-coupled inverter, and the second pass gate PG2 and the fourth pass gate PG4 are used as the first port of the cross-coupled inverter. Two ports.

FIG. 6 shows the structure of the SRAM according to the third preferred embodiment of the present invention, wherein components with the same function will be given the same reference numerals. As shown in Figure 6, a structure 300 of a ten-transistor SRAM includes a substrate 50, a fifth active area 60, a third active area 56, a first active area 52, and a second active area. The region 54, a fourth active region 58 and a sixth active region 62 are arranged on the substrate 50 sequentially from left to right, wherein the first active region 52, the second active region 54, the third active region 56, the fourth The active region 58 , the fifth active region 60 and the sixth active region 62 are parallel to each other, and the first active region 52 , the second active region 54 , the third active region 56 and the fourth active region 58 are not connected to each other in structure. The two ends of the seventh active region 64 contact the third active region 56 and the fifth active region 60 respectively, the seventh active region 64 and the fifth active region 60 are vertical, the third active region 56, the fifth active region 60 and the seventh active region The active area 64 forms an H shape. The two ends of the eighth active region 66 respectively contact the fourth active region 58 and the sixth active region 62, the eighth active region 66 and the sixth active region 62 are vertical, the eighth active region 66, the fourth active region 58 and the sixth active region The active regions 62 together form another H-shape. Set between the first active area 52, the second active area 54, the third active area 56, the fourth active area 58, the fifth active area 60, the sixth active area 62, the seventh active area 64 and the eighth active area 66 There is an insulating region 68 .

A first gate line 70 continuously covers the first active region 52, the second active region 54, the fourth active region 58 and the insulating region 68, and a second gate line 72 covers the fourth active region 58, wherein the second gate The pole line 72 is parallel to the first gate line 70 , but the second gate line 72 does not cover the sixth active region 62 and the second active region 54 . A third gate line 74 continuously covers the first active region 52, the second active region 54, the third active region 56 and the insulating region 68, and a fourth gate line 76 covers the third active region 56, wherein the fourth gate The pole line 76 is parallel to the third gate line 74, but the fourth gate line 76 does not cover the first active area 52 and the fifth active area 60, and a first metal wire 86 is electrically connected to the first gate line 70 and the second The gate line 72 is perpendicular to the first metal wire 86 and the eighth active region 66 viewed from the top view direction, and part of the first metal wire 86 overlaps with the eighth active region 66, and a second metal wire 88 is electrically connected to the third The gate line 74 and the fourth gate line 76 , wherein the second metal wire 88 is perpendicular to the seventh active region 64 .

A first pull-down transistor PD21 and a second pull-down transistor PD22 are arranged in the third active area 56, in detail, the fourth gate line 76 overlapping the third active area 56 is used as the first pull-down transistor PD21 Gate, the third gate line 74 overlapping the third active region 56 is used as the gate of the second pull-down transistor P22; a third pull-down transistor PD11 and a fourth pull-down transistor PD12 are arranged in the fourth active region 58 The first gate line 70 overlapping the fourth active region 58 is used as the gate of the fourth pull-down transistor PD12, and the second gate line 72 overlapping the fourth active region 58 is used as the gate of the third pull-down transistor PD11 ; A first pull-up transistor PU1 is arranged in the first active area 52, and the first gate line 70 overlapping the first active area 52 is used as the gate of the first pull-up transistor PU1; a second pull-up transistor PU2 is disposed in the second active area 54 , and the third gate line 74 overlapping the second active area 54 is used as the gate of the second pull-up transistor PU2 . A first pass gate transistor PG1 and a second pass gate transistor PG2 are arranged in the sixth active area 62, and the seventh gate line 82 overlapping the sixth active area 62 is used as the first pass gate transistor PG1 gate; the eighth gate line 84 overlapping the sixth active region 62 serves as the gate of the second passing gate transistor PG2. A third pass gate transistor PG3 and a fourth pass gate transistor PG4 are arranged in the fifth active area 60, and the fifth gate line 78 overlapping the fifth active area is used as the third pass gate transistor PG3 Gate: the sixth gate line 80 overlapping the fifth active region 60 is used as the gate of the fourth passing gate transistor PG4. In addition, in FIG. 6 , metal wires are indicated by frame lines formed of dotted lines.

In addition, the equivalent circuit diagrams of the third preferred embodiment are the same as those of the first preferred embodiment, please refer to FIG. 5 , and details will not be repeated here.

The difference between the first preferred embodiment and the third preferred embodiment is that the third preferred embodiment uses the first metal wire 86 to replace the second part 26b of the first gate line 26 in the first preferred embodiment, and uses The second metal wire 88 replaces the fifth portion 28b of the second gate line 28 in the first preferred embodiment. In addition, as shown in FIG. 1, the drain of the first pull-down transistor PD21 and the drain of the second pull-down transistor PD22 in the first preferred embodiment are connected by a metal wire (marked by a dotted frame) and The source of the third pass gate transistor PG3 and the source of the fourth pass gate transistor PG4 are electrically connected. As shown in FIG. 6, in the third preferred embodiment, the drain of the first pull-down transistor PD21 and the drain of the second pull-down transistor PD22 are connected by the seventh active region 64 and the third pass gate. The source of the transistor PG3 and the source of the fourth passing gate transistor PG4 are electrically connected, and the drain of the third pull-down transistor PD11 and the drain of the fourth pull-down transistor PD12 in the first preferred embodiment are the same The source of the first passing gate transistor PG1 and the source of the second passing gate transistor PG2 are electrically connected through the metal wire. But in the third preferred embodiment, the drain of the third pull-down transistor PD11 and the drain of the fourth pull-down transistor PD12 are connected by the eighth active region 66 and the source of the first pass gate transistor PG1 and The source of the second pass gate transistor PG2 is electrically connected. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base 12: The first active area 14:Second active area 16: The third active area 18: The fourth active area 20: Fifth active area 22: The sixth active area 24: Insulation area 26: The first gate line 26a: Part 1 26b: Part Two 26c: Part III 28: Second gate line 28a: Part Four 28b: Part V 28c: Part VI 30: The third gate line 32: The fourth gate line 34: Fifth gate line 36: The sixth gate line 50: base 52: First Active Area 54:Second active area 56: The third active area 58: The fourth active area 60: Fifth active area 62: The sixth active area 64: The seventh active area 66: The eighth active area 68: Insulation area 70: The first gate line 72: Second gate line 74: The third gate line 76: The fourth gate line 78: Fifth gate line 80: The sixth gate line 82: The seventh gate line 84: Eighth gate line 86: The first metal wire 88: Second metal wire 100:Static random processing memory structure 130: Gate 132: gate dielectric layer 134: N-type work function layer 138: metal gate 140: Gate 200: Static random processing memory structure 300: Static random processing memory structure A: P-type transistor area B: N-type transistor area C: P-type transistor area D: N-type transistor area BL11: bit line BL12: bit line BL21: bit line BL22: bit line PU1: the first pull-up transistor PU2: The second pull-up transistor PG1: The first pass gate transistor PG2: The second pass gate transistor PG3: The third pass gate transistor PG4: The fourth pass gate transistor PD11: The third pull-down transistor PD12: The fourth pull-down transistor PD21: the first pull-down transistor PD22: Second pull-down transistor Vdd: drain voltage Vss: source voltage WL1: word line WL2: word line

FIG. 1 shows the structure of the SRAM according to the first preferred embodiment of the present invention. Figure 2 is a side view along the line I-I' in Figure 1. FIG. 3 shows the structure of the SRAM according to the second preferred embodiment of the present invention. Figure 4 is a side view along the line J-J' in Figure 3. Fig. 5 is an equivalent circuit diagram according to the first preferred embodiment of the present invention. FIG. 6 shows the structure of the SRAM according to the third preferred embodiment of the present invention.

10: Base

12: The first active area

14:Second active area

16: The third active area

18: The fourth active area

20: Fifth active area

22: The sixth active area

24: Insulation area

26: The first gate line

26a: Part 1

26b: Part II

26c: Part III

28: Second gate line

28a: Part Four

28b: Part V

28c: Part VI

30: The third gate line

32: The fourth gate line

34: Fifth gate line

36: The sixth gate line

100:Static random processing memory structure

A: P-type transistor area

B: N-type transistor area

PU1: the first pull-up transistor

PU2: The second pull-up transistor

PG1: The first pass gate transistor

PG2: The second pass gate transistor

PG3: The third pass gate transistor

PG4: The fourth pass gate transistor

PD11: The third pull-down transistor

PD12: The fourth pull-down transistor

PD21: the first pull-down transistor

PD22: Second pull-down transistor

Claims (9)

A structure for static random processing memory, comprising: a base; A first active region, a second active region, a third active region and a fourth active region are located on the substrate, wherein the first active region, the second active region, the third active region and the fourth active region The four active regions are parallel to each other and structurally not connected to each other, the third active region, the first active region, the second active region and the fourth active region are arranged in sequence from left to right; A first gate line is disposed on the substrate, and the first gate line includes: A first part, a second part and a third part, the first part and the third part are perpendicular to the first active area, the second part is parallel to the first active area, the first part covers the first Active area, the second active area and the fourth active area, the third part covers the fourth active area, the second part is located on an insulating area between the second active area and the fourth active area and access to the first part and the third part; and A second gate line is disposed on the substrate, and the second gate line includes: A fourth part, a fifth part and a sixth part, the fourth part and the sixth part are perpendicular to the first active area, the fifth part is parallel to the first active area, and the fourth part covers The first active region, the second active region and the third active region, the sixth part covers the third active region, the fifth part covers the insulation between the first active region and the third active region area and access to the fourth part and the sixth part; - the fifth active area; a sixth active region, the fifth active region and the sixth active region are parallel to the first active region, the third active region is located between the first active region and the fifth active region, the fourth The active region is located between the sixth active region and the second active region, wherein the first active region, the second active region, the third active region, the fourth active region, the fifth active region and the The sixth active regions are not structurally connected to each other; a third gate line covering the sixth active region; A fourth gate line covers the sixth active region; a fifth gate line covers the fifth active region; and A sixth gate line covers the fifth active region. The structure of the SRAM according to claim 1, wherein the first part and the third part are structurally disconnected, and the fourth part and the sixth part are structurally disconnected. The structure of static random processing memory as described in claim item 1, wherein: A first pull-down transistor and a second pull-down transistor are arranged in the third active region; A third pull-down transistor and a fourth pull-down transistor are arranged in the fourth active region; a first pull-up transistor is disposed on the first active region; and A second pull-up transistor is disposed on the second active region. The structure of static random processing memory as described in claim item 3, wherein: a first pass-gate transistor and a second pass-gate transistor disposed in the sixth active region; and A third pass gate transistor and a fourth pass gate transistor are disposed in the fifth active region. The structure of SRAM as described in claim item 4, wherein the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the third The pull-down transistor and the fourth pull-down transistor form two cross-coupled inverters. The structure of SRAM according to claim 5, wherein the first pass gate and the third pass gate serve as the first ports of the cross-coupled inverters, the second pass gate and the pass gate The fourth passing gate serves as the second port of the cross-coupled inverters. The structure of SRAM according to claim 3, wherein the overlap between the first part and the fourth active area is used as the gate of the fourth pull-down transistor, and the overlap between the first part and the first active area as the gate of the first pull-up transistor. The structure of the SRAM according to claim 7, wherein the structure of the second part is the same as the gate of the fourth pull-down transistor. The structure of the SRAM according to claim 7, wherein the structure of the second part is the same as the gate of the first pull-up transistor.

Images