TW202331856A - Manufacturing method of package structure of electronic device - Google Patents

Abstract

A manufacturing method of a package structure of an electronic device including steps below is provided. Forming a first seed layer on a carrier plate. Forming a first metal layer on the first seed layer. Forming a first insulating layer on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. Performing a first plasma treatment on the first insulating layer and the portion of exposed first metal layer. Placing the carrier plate on which the first seed layer, the first metal layer, and the first insulating layer are formed in a microenvironment controlling box after performing the first plasma treatment. Forming a second seed layer on the first insulating layer and the portion of exposed first metal layer after taking out the carrier plate from the microenvironment controlling box.

Description

Method for manufacturing package structure of electronic device

The present invention relates to a manufacturing method of a packaging structure, and in particular to a manufacturing method of a packaging structure of an electronic device.

In the process of manufacturing the packaging structure of electronic devices, before forming a seed layer for growing subsequent metal layers on the surface of the formed insulating layer and metal layer, the formed insulating layer and metal layer will be treated with a surface treatment device. The surface of the metal layer is surface-treated to remove residues on the surface and enhance the adhesion of the seed layer to the surface; however, after the surface is surface-treated, waiting for the next process (such as When using a coating device to form a seed layer) and expose it to the atmosphere for a long time, it will, for example, cause defects on the surface of the formed insulating layer and metal layer (such as moisture intrusion) or generate oxides (such as metal layer oxidation ), resulting in a decrease in the adhesion between the seed layer and the surface, that is, the decrease in the effect of the surface treatment, which in turn reduces the reliability and/or electrical properties of the electronic device including the package structure.

The disclosure provides a method for manufacturing a packaging structure of an electronic device. When the manufactured packaging structure is applied to an electronic device, the electronic device can have improved reliability and/or electrical performance.

According to some embodiments of the present disclosure, a method for manufacturing a package structure includes the following steps. First, a first seed layer is formed on the carrier. Next, a first metal layer is formed on the first seed layer. Afterwards, a first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes part of the first metal layer. Next, a first plasma treatment is performed on the first insulating layer and the exposed part of the first metal layer. Then, after the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer and the first insulating layer is placed in the micro-environment control box. Then, after the carrier board is taken out from the micro-environment control box, a second seed layer is formed on the first insulating layer and the exposed part of the first metal layer.

In order to make the above-mentioned features and advantages of the present disclosure more comprehensible, the following specific embodiments are described in detail with accompanying drawings.

The present disclosure can be understood by referring to the following detailed description and combined with the accompanying drawings. It should be noted that, in order to make the readers easy to understand and the drawings are concise, several drawings in the present disclosure only depict a part of the electronic device, and Certain elements in the drawings are not drawn to actual scale. In addition, the number and size of each component in the figure are only for illustration, and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout this disclosure and in the appended claims to refer to particular elements. Those skilled in the art should understand that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between those elements that have the same function but have different names. In the following specification and patent application scope, words such as "comprising", "containing", and "having" are open-ended words, so they should be interpreted as meaning "including but not limited to...". Therefore, when the terms "comprising", "comprising" and/or "having" are used in the description of the present disclosure, it specifies the existence of corresponding features, regions, steps, operations and/or components, but does not exclude one or more The existence of a corresponding feature, region, step, operation and/or component.

The directional terms mentioned in this document, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Accordingly, the directional terms used are for illustration, not for limitation of the present disclosure. In the drawings, each figure illustrates the general characteristics of methods, structures and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses and positions of layers, regions and/or structures may be reduced or exaggerated for clarity.

When a corresponding element (eg, a film or region) is referred to as being "on" another element, it can be directly on the other element or there may be other elements interposed therebetween. On the other hand, when a component is referred to as being "directly on" another component, then there is no component in between. In addition, when a component is referred to as "on another component", the two have a vertical relationship in the plan view direction, and the component can be above or below the other component, and this vertical relationship depends on the orientation of the device ( orientation).

The terms "about", "substantially" or "approximately" are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3% of a given value or range , 2%, 1% or 0.5%.

The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify elements, which do not imply and represent that the (or these) elements have any previous ordinal numbers, nor The use of these ordinal numbers is only used to clearly distinguish an element with a certain designation from another element with the same designation. The same wording may not be used in the scope of the patent application and the specification. Accordingly, the first component in the specification may be the second component in the scope of the patent application.

It should be noted that in the following embodiments, without departing from the spirit of the present disclosure, features in several different embodiments may be replaced, reorganized, and mixed to complete other embodiments. As long as the features of the various embodiments do not violate the spirit of the invention or conflict, they can be mixed and matched arbitrarily.

The electrical connection or coupling described in this disclosure can refer to direct connection or indirect connection. In the case of , there are switches, diodes, capacitors, inductors, other suitable components, or a combination of the above components between the terminals of the components on the two circuits, but not limited thereto.

In this disclosure, the thickness, length and width can be measured by optical microscope, and the thickness can be measured by cross-sectional image in electron microscope, but not limited thereto. In addition, any two values or directions used for comparison may have certain errors. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the difference between the first direction and the second direction The angle between them may be between 80° and 100°; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0° and 10°.

The electronic device may have the composite layer circuit structure of the disclosed embodiments. The electronic device of the present disclosure may include display, antenna (such as liquid crystal antenna), lighting, sensing, touch, splicing, other suitable functions, or a combination of the above functions, but is not limited thereto. Electronic devices include, but are not limited to, rollable or flexible electronic devices. The electronic device may, for example, include liquid crystal (liquid crystal), light emitting diode (light emitting diode, LED), quantum dot (quantum dot, QD), fluorescence (fluorescence), phosphorescence (phosphor), other suitable materials or the above-mentioned combination. The light emitting diodes may for example comprise organic light emitting diodes (organic light emitting diodes, OLEDs), miniature light emitting diodes (micro-LEDs, mini-LEDs) or quantum dot light emitting diodes (QLEDs, QDLEDs), but not This is the limit. In the following, a display device or a splicing device will be used as an electronic device to illustrate the content of the disclosure, but the disclosure is not limited thereto. Electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, circuit boards, chips, dies, Integrated circuits (integrated circuits, IC) or a combination of the above components or other suitable electronic components are not limited thereto. The diodes may include light emitting diodes or photodiodes. The light emitting diodes may, for example, include organic light emitting diodes (organic light emitting diodes, OLEDs), submillimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs) or quantum dot light emitting diodes (quantum light emitting diodes). dot LED), but not limited to.

Exemplary embodiments of the present disclosure are illustrated below, and the same reference numerals are used in the drawings and descriptions to denote the same or similar parts.

FIG. 1 is a flow chart of a manufacturing method of a packaging structure of an electronic device according to an embodiment of the disclosure, FIG. 2 is a schematic cross-sectional view of a packaging structure of an electronic device according to an embodiment of the disclosure, and FIG. 3 is a packaging of the electronic device according to FIG. 2 A partially enlarged cross-sectional schematic diagram of the structure, and FIG. 4 is a schematic diagram of a micro-environment control device according to an embodiment of the present disclosure.

Please refer to FIG. 1 and FIG. 2 at the same time. In step S100 of this embodiment, a first seed layer SEED1 is formed on the carrier CP. The material of the carrier CP can be, for example, an organic material or an inorganic material, such as glass, quartz, sapphire, silicon wafer, stainless steel, ceramic, polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) , polyethylene terephthalate (polyethylene terephthalate, PET), resin, organosilicon compound, other suitable substrate materials, or a combination thereof. In this embodiment, the carrier CP includes a glass carrier, but the disclosure is not limited thereto. In addition, in this embodiment, before forming the first seed layer SEED1 on the carrier CP, the release layer RL may be formed on the carrier CP first. The disposition of the release layer RL can make the subsequent components disposed on the carrier plate CP be easily separated therefrom. In some embodiments, the release layer RL has good heat resistance to withstand subsequent heat treatment processes. The material of the release layer RL can be, for example, selected from a suitable organic material, and the present disclosure is not limited thereto. In some embodiments, the top surface of the release layer RL (the surface away from the carrier CP) may be planarized to have a high degree of coplanarity. The method for forming the first seed layer SEED1 may be, for example, a physical vapor deposition process or a chemical vapor deposition process, and the present disclosure is not limited thereto. The material of the first seed layer SEED1 may be, for example, metal, and may, for example, have a single-layer structure or a composite layer structure having a plurality of sub-layers formed of different metals, wherein the sub-layers are stacked on top of each other. For example, the first seed layer SEED1 of this embodiment may include a titanium layer (not shown) and a copper layer (not shown) laminated on the titanium layer, thus having a composite layer structure, but this disclosure does not limit.

In some embodiments, the carrier CP may have panel-level dimensions. Based on this, in the subsequent process to be performed in this embodiment, for example, the rewiring structure is arranged on the carrier board CP with panel-level dimensions and then the chip is packaged; or the chip can be placed on the carrier board with panel-level dimensions The packaging on the CP, that is, the manufacturing method of the packaging structure shown in this embodiment can be used, for example, as a fan-out panel level package (Fan out panel level package; FOPLP), where the fan-out panel level package can include rewiring Structure first (RDL first) process or wafer first (chip first) process. In this embodiment, the fan-out panel-level packaging can greatly increase the productivity compared with the wafer-level packaging because the carrier CP with panel-level dimensions is used. At the same time, the carrier CP with panel-level dimensions has a rectangular profile, which can greatly improve the utilization rate of the carrier CP compared with wafer-level packaging. Therefore, the packaging structure of the electronic device manufactured in this embodiment can be used to meet the requirement of high production capacity.

In step S110 of this embodiment, a first metal layer M1 is formed on the first seed layer SEED1. In this embodiment, forming the first metal layer M1 may include the following steps, but the disclosure is not limited thereto. A first photoresist layer (not shown) is formed on the surface of the first seed layer SEED1 away from the carrier plate CP, where the first photoresist layer can be formed by, for example, a spin-coating process or other suitable processes followed by a patterning process. , and the first photoresist layer includes a plurality of openings exposing part of the first seed layer SEED1. Next, the first metal layer M1 is formed in the openings by using, for example, an electroplating process to grow the first seed layer SEED1 . Based on this, the material of the first metal layer M1 may, for example, be the same as that of the first seed layer SEED1. In this embodiment, the first metal layer M1 may be a copper layer, that is, the material of the first metal layer M1 includes copper. Afterwards, the first photoresist layer may be removed, for example, by performing an ashing process or other suitable stripping processes, but the disclosure is not limited thereto.

In step S120 of this embodiment, a first insulating layer IL1 is formed on the first metal layer M1 , wherein the first insulating layer IL1 exposes part of the first metal layer M1 . In this embodiment, forming the first insulating layer IL1 may include the following steps, but the disclosure is not limited thereto. First, a first insulating material layer (not shown) covering the first metal layer M1 is formed on the surface of the first seed layer SEED1 far away from the carrier plate CP, wherein the first insulating material layer can be formed by, for example, a chemical vapor deposition process Or other suitable processes are formed, and the present disclosure is not limited thereto. Next, a patterning process is performed on the first insulating material layer to form a first insulating layer IL1 having a plurality of first openings OP1 , wherein a portion of the first metal layer M1 is exposed by the first openings OP1 . The material of the first insulating layer IL1 can be, for example, organic material, oxide, nitride, oxynitride or a combination thereof, and the present disclosure is not limited thereto. In this embodiment, the material of the first insulating layer IL1 includes photosensitive polyimide.

In step S130 of this embodiment, a first plasma treatment is performed on the first insulating layer IL1 and the exposed part of the first metal layer M1 . In some embodiments, the first plasma treatment may be performed on the first insulating layer IL1 and the exposed part of the first metal layer M1 by using a surface treatment device in the prior art, and the present disclosure is not limited thereto. Performing the first plasma treatment on the first insulating layer IL1 and the exposed part of the first metal layer M1 can, for example, achieve the following effects. increasing the surface roughness of the first insulating layer IL1 and/or increasing the degree of cross-linking of materials in the first insulating layer IL1; and/or removing native oxide formed on the first metal layer M1. That is, after the surface of the first insulating layer IL1 and the exposed surface of the first metal layer M1 are treated with the first plasma, the adhesion between the seed layer to be formed subsequently and the surface thereof can be improved. In some embodiments, the gas used in the first plasma treatment may include oxygen, hydrogen, argon or a combination thereof, the present disclosure is not limited thereto.

In step S140 of this embodiment, after the first plasma treatment, the carrier plate CP formed with the first seed layer SEED1, the first metal layer M1 and the first insulating layer IL1 is placed in the micro-environment control box 110 . In an embodiment shown in Figure 4, the microenvironment control box 110 belongs to one of the components in the microenvironment control device 100, wherein the microenvironment control device 100 may include the microenvironment control box 110, a gas supply device 120, a gas The delivery pipeline 130 and the gas condition control device 140, but the present disclosure is not limited thereto. The micro-environment control box 110 may, for example, include an upper bracket 112, a lower bracket 114, a plurality of pillars 116 and a plurality of poles 118, wherein the plurality of pillars 116 are arranged between the upper bracket 112 and the lower bracket 114 to form a micro-environment control box 110, a plurality of struts 118 are arranged at intervals on each strut 116, and the extension direction of the plurality of struts 118 is perpendicular to the extension direction of the struts 116, for example, for carrying the carrier plate CP, but the present disclosure does not This is the limit. The gas supply device 120 is loaded with, for example, nitrogen gas, clean dry air (Clean Dry Air; CDA) or other suitable gas for supplying to the mini-environment control box 110 . The gas delivery pipeline 130 is used, for example, to deliver the gas loaded in the gas supply device 120 to the micro-environment control box 110 . The gas condition control device 140 is used, for example, to control the condition of the gas delivered to the micro-environment control box 110 . In detail, in this embodiment, the gas condition control device 140 includes an oxygen condition control element 142 and a water vapor condition control element 144, wherein the oxygen condition control element 142 can control the concentration of the gas delivered to the microenvironment control box 110, And the moisture condition control element 144 can control the relative humidity of the gas delivered to the micro-environment control box 110 . In this embodiment, the oxygen concentration in the micro-environment control box 110 is less than 1000 ppm, and the relative humidity in the micro-environment control box 110 is less than 50%. In addition, in some embodiments, the temperature in the microenvironment control box 110 is greater than or equal to 25°C and less than or equal to 30°C, the air pressure in the microenvironment control box 110 is greater than 1 atm, and the temperature in the microenvironment control box 110 The gas may include nitrogen or clean dry air (delivered by gas supply 120). Based on this, after the carrier plate CP formed with the first seed layer SEED1, the first metal layer M1 and the first insulating layer IL1 is placed in the micro-environment control box 110, due to the oxygen and moisture in the micro-environment control box 110 The content of the oxygen and water vapor in the exposed part of the first metal layer M1 can not be rapidly oxidized and/or the rough surface of the first insulating layer IL1 can not be permeated by a large amount of water vapor, The second seed layer SEED2 to be formed later can be stably formed and attached to the exposed part of the surface of the first metal layer M1 and the surface of the first insulating layer IL1, that is, it can make the second seed layer The adhesion between the SEED2 and a portion of the surface of the first metal layer M1 and the surface of the first insulating layer IL1 increases. In addition, in some embodiments, before the first plasma treatment is performed on the first insulating layer IL1 and the exposed part of the first metal layer M1, the carrier board CP may also be transported to the coating device and then to the surface treatment device. A mini-environment control box 110 is utilized. In some embodiments, the surface roughness of the first metal layer M1 becomes larger after plasma treatment. In other words, the surface roughness of the first metal layer M1 after plasma treatment may be greater than that without plasma treatment. Surface roughness of the first metal layer M1. In some embodiments, the roughness can be measured using an Atomic Force Microscope (AFM) or other suitable measuring instruments. In addition, the aforementioned “roughness” may be an arithmetic mean roughness (Ra), that is, the arithmetic mean of deviation values from the center line to the shape along the length of the sampling portion, but the present disclosure is not limited thereto.

In step S150 of this embodiment, after the carrier board CP is taken out of the micro-environment control box 110 , a second seed layer SEED2 is formed on the first insulating layer IL1 and the exposed part of the first metal layer M1 . For the step of forming the second seed layer SEED2, reference may be made to the aforementioned step S100, which will not be repeated here. In addition, after the carrier board CP is taken out of the micro-environment control box 110, it can be selectively imported into the atmosphere environment for subsequent manufacturing processes, but the time after it is not long so that the first metal layer M1 on the carrier board CP is in contact with the first The surface of the insulating layer IL1 may not be affected by it. In addition, the present disclosure does not need to deliberately connect the surface treatment device and the coating device, which improves the process efficiency of manufacturing the packaging structure of the electronic device.

In this embodiment, at least one cycle of the steps of forming the metal layer and the insulating layer can be repeated to form a redistribution structure RDL as shown in FIG. 2 , wherein the redistribution structure RDL can be used as the wiring of an electronic device layer to provide the required conductive transmission path. For example, as shown in FIG. 2, the rewiring structure RDL may include a first seed layer SEED1, a first metal layer M1, a first insulating layer IL1 having a plurality of first openings OP1, a second seed layer SEED2 , the second metal layer M2, the second insulating layer IL2 having a plurality of second openings OP2, the third seed layer SEED3, the third metal layer M3, the third insulating layer IL3 having a plurality of third openings OP3, the fourth The seed layer SEED4, the fourth metal layer M4, the insulation layer IL4 having a plurality of fourth openings OP4, the fifth seed layer SEED5, and the fifth metal layer M5, but the present disclosure is not limited thereto. In detail, after forming the second seed layer SEED2 on the first insulating layer IL1 and the exposed part of the first metal layer M1 (step S150 ), for example, the following steps may be performed sequentially for at least one cycle: first , forming the second metal layer M2 on the second seed layer SEED2. For this step, refer to the step S110 of the previous embodiment. In addition, during the process of forming the second metal layer M2, part of the second seed layer SEED2 is combined was removed. Next, a second insulating layer IL2 is formed on the second metal layer M2, wherein the second insulating layer IL2 exposes a part of the second metal layer M2. For this step, refer to the step S120 of the foregoing embodiment. Afterwards, a second plasma treatment is performed on the second insulating layer IL2 and the exposed part of the second metal layer M2 , and for this step, refer to the step S130 of the foregoing embodiment. Next, after the second plasma treatment, the first seed layer SEED1, the first metal layer M1, the first insulating layer IL1, the second seed layer SEED2, the second metal layer M2 and the second insulating layer will be formed. The carrier plate CP of IL2 is placed in the mini-environment control box 110 , and this step can refer to the step S140 of the previous embodiment. Then, after the carrier board CP is taken out from the micro-environment control box 110, the third seed layer SEED3 is formed on the second insulating layer IL2 and the exposed part of the second metal layer M2. This step can refer to the above-mentioned embodiment. Step S150.

In some embodiments, as shown in FIG. 3 , the first opening OP1 may have a width W in a direction perpendicular to the normal direction of the carrier plate CP, wherein the width W may be greater than or equal to 10 microns and less than or equal to 20 microns. micron, so that the resistance of the second seed layer SEED2 and the second metal layer M2 formed in the first opening OP1 may be less than or equal to 0.05 ohm, but the present disclosure is not limited thereto. In addition, the second opening OP2 , the third opening OP3 , and the fourth opening OP4 may also have a width W greater than or equal to 10 micrometers and less than or equal to 20 micrometers, and the present disclosure is not limited thereto.

So far, the fabrication of the package structure 10 of the disclosed embodiment is completed. It is worth noting that the method for manufacturing the package structure 10 of this embodiment is described by taking the above method as an example; however, the method for forming the package structure disclosed in the present disclosure is not limited thereto. For example, after the redistribution structure RDL is formed, the process of forming the semiconductor wafer can be continued, that is, the manufacturing method of the packaging structure 10 in this embodiment is a redistribution structure first (RDL first) process. In addition, although the package structure 10 of the embodiment of the present disclosure is applied to panel level packaging as an example; however, the package structure 10 of the present disclosure can be applied to various semiconductor devices and/or semiconductor manufacturing processes, and the present disclosure is not limited thereto. . In addition, the packaging structure 10 of the embodiment of the present disclosure can be bonded with electronic components such as integrated circuit chips and/or printed circuit boards in subsequent manufacturing processes, but the present disclosure is not limited thereto. The above bonding method can be, for example, by disposing bonding pads between the redistribution structure RDL and the electronic components, but the present disclosure is not limited thereto.

In summary, some embodiments of the present disclosure provide a method for manufacturing a packaging structure by performing plasma treatment on the insulating layer and the exposed metal layer on the carrier and forming a subsequent wafer on the carrier. Before the seed layer, the carrier plate comprising the metal layer and the insulating layer formed in the previous process is placed in the micro-environment control box, which can make the subsequent formation of the seed layer and the surface of the metal layer and the insulating layer on the carrier plate The adhesion between the surfaces of the packaging structure is increased, which further improves the reliability and/or electrical performance of the electronic device including the packaging structure. Furthermore, the surface treatment device and the film coating device used in the manufacturing method of the packaging structure provided by the present disclosure do not need to be connected. This improves the process efficiency of manufacturing the packaging structure of the electronic device of the present disclosure.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present disclosure. scope. As long as the features of the various embodiments do not violate the spirit of the invention or conflict, they can be mixed and matched arbitrarily.

10: Package structure 100: Micro-environment control device 110: Micro-environment control box 112: upper bracket 114: lower bracket 116: Pillar 118: pole 120: gas supply device 130: Gas delivery pipeline 140: Gas condition control device 142: Oxygen condition control element 144: water vapor condition control element CP: carrier board IL1: first insulating layer IL2: Second insulating layer IL3: third insulating layer IL4: fourth insulating layer M1: first metal layer M2: second metal layer M3: The third metal layer M4: fourth metal layer M5: fifth metal layer OP1: first opening OP2: second opening OP3: the third opening OP4: fourth opening RDL: Rewiring Structure RL: release layer S100, S110, S120, S130, S140, S150: steps SEED1: the first seed layer SEED2: second seed layer SEED3: the third seed layer SEED4: the fourth seed layer SEED5: fifth seed layer W: width

FIG. 1 is a flowchart of a method for manufacturing a packaging structure of an electronic device according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of a packaging structure of an electronic device according to an embodiment of the present disclosure. FIG. 3 is a partially enlarged cross-sectional schematic diagram of the packaging structure of the electronic device according to FIG. 2 . FIG. 4 is a schematic diagram of a micro-environment control device according to an embodiment of the present disclosure.

S100, S110, S120, S130, S140, S150: steps

Claims (10)

A method for manufacturing a package structure of an electronic device, comprising: forming a first seed layer on the carrier; forming a first metal layer on the first seed layer; forming a first insulating layer on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer; performing a first plasma treatment on the first insulating layer and the exposed portion of the first metal layer; After performing the first plasma treatment, placing the carrier plate formed with the first seed layer, the first metal layer and the first insulating layer in a micro-environment control box; and After the carrier board is taken out of the micro-environment control box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer. The manufacturing method of the packaging structure of the electronic device according to claim 1, wherein the oxygen concentration in the micro-environment control box is less than 1000 ppm. The manufacturing method of the packaging structure of the electronic device according to claim 1, wherein the relative humidity in the micro-environment control box is less than 50%. The manufacturing method of the packaging structure of electronic devices according to claim 1, wherein the temperature in the micro-environment control box is greater than or equal to 25°C and less than or equal to 30°C. The manufacturing method of the packaging structure of the electronic device according to claim 1, wherein the air pressure in the micro-environment control box is greater than 1 atm. The manufacturing method of the packaging structure of electronic devices according to claim 1, wherein the gas in the micro-environment control box includes nitrogen or clean dry air. The method for manufacturing a packaging structure of an electronic device as claimed in claim 1, wherein the carrier includes a glass carrier. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein a release layer is formed on the carrier before forming the first seed layer on the carrier. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein the gas used in the first plasma treatment includes oxygen, hydrogen, argon or a combination thereof. The method for manufacturing a packaging structure of an electronic device according to claim 1, wherein after forming the second seed layer on the first insulating layer and the exposed portion of the first metal layer, Also includes: forming a second metal layer on the second seed layer; forming a second insulating layer on the second metal layer, wherein the second insulating layer exposes a portion of the second metal layer; performing a second plasma treatment on the second insulating layer and the exposed portion of the second metal layer; After the second plasma treatment, the first seed layer, the first metal layer, the first insulating layer, the second seed layer, the second metal layer and The carrier plate of the second insulating layer is placed in the mini-environment control box; and After the carrier board is taken out of the micro-environment control box, a third seed layer is formed on the second insulating layer and the exposed portion of the second metal layer.

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