TW202316676A - Capacitor structure and manufacturing method thereof - Google Patents

Abstract

A capacitor structure including a substrate and a capacitor is provided. The substrate has a recess. The capacitor includes a first electrode, a second electrode, and a dielectric layer. The first electrode includes conductive pillars and a conductive layer. The conductive pillars are located on the substrate in the recess. There are various pitches between the conductive pillars. The conductive layer is connected to the conductive pillars. The second electrode is located on the first electrode. The dielectric layer is located between the first electrode and the second electrode.

Description

Capacitor structure and manufacturing method thereof

The embodiments of the present invention relate to a semiconductor structure and its manufacturing method, and in particular to a capacitor structure and its manufacturing method.

Capacitors are very important basic components in current semiconductor structures. However, as the integration level of semiconductor devices continues to increase, the size of capacitors also shrinks. Therefore, how to improve the capacitance value of the capacitor under the condition that the size of the capacitor is reduced is the goal of continuous efforts.

The invention provides a capacitor structure and a manufacturing method thereof, which can increase the capacitance value of the capacitor.

The invention provides a capacitor structure, including a substrate and a capacitor. The base has grooves. The capacitor includes a first electrode, a second electrode and a dielectric layer. The first electrode includes a plurality of conductive pillars and a conductive layer. A plurality of conductive posts are positioned on the base in the groove. There are various spacings between the plurality of conductive posts. The conductive layer is connected to a plurality of conductive pillars. The second electrode is located on the first electrode. The dielectric layer is located between the first electrode and the second electrode.

According to an embodiment of the present invention, in the above capacitor structure, the plurality of conductive pillars can extend away from the base.

According to an embodiment of the present invention, in the above capacitor structure, the conductive layer may be a doped region located in the substrate.

According to an embodiment of the present invention, in the above capacitor structure, the conductive layer may cover a plurality of conductive pillars.

According to an embodiment of the present invention, in the above capacitor structure, the bottoms of two adjacent conductive pillars may be connected to each other.

According to an embodiment of the present invention, in the above capacitor structure, the substrate may have at least one needle located in the groove.

According to an embodiment of the present invention, in the above capacitor structure, a part of the plurality of conductive pillars can be located on the sidewall of the needle.

According to an embodiment of the present invention, in the above capacitor structure, the tops of two adjacent conductive pillars located on the sidewalls of the needles may be connected to each other.

According to an embodiment of the present invention, in the above capacitor structure, the base located in the groove may have a plurality of upper surfaces. The plurality of upper surfaces can have various heights.

According to an embodiment of the present invention, in the above capacitor structure, the plurality of conductive pillars may have various heights.

According to an embodiment of the present invention, in the above capacitor structure, the substrate may be a substrate of an interposer.

The invention provides a method for manufacturing a capacitor structure, which includes the following steps. Provide the base. The base has grooves. form a capacitor. The capacitor includes a first electrode, a second electrode and a dielectric layer. The first electrode includes a plurality of conductive pillars and a conductive layer. A plurality of conductive posts are positioned on the base in the groove. There are various spacings between the plurality of conductive posts. The conductive layer is connected to a plurality of conductive pillars. The second electrode is located on the first electrode. The dielectric layer is located between the first electrode and the second electrode.

According to an embodiment of the present invention, in the method for manufacturing the above capacitor structure, the method for forming the capacitor may include the following steps. A patterned hard mask layer is formed on the substrate. Using the patterned hard mask layer as a mask, part of the substrate is removed to form a groove and a plurality of needles on the substrate in the groove. A conductive layer is formed in the base and the plurality of needles around the groove. A layer of conductive post material is conformally formed on the substrate, the plurality of needles, and the patterned hard mask layer. Part of the material layer of the conductive pillar is removed to form a plurality of conductive pillars and expose a plurality of needles. At least a portion of the exposed plurality of needles is removed. A dielectric layer is formed on the conductive layer and the plurality of conductive pillars. A second electrode is formed on the dielectric layer.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned capacitor structure, the method of forming the grooves and the needles is, for example, performing a reactive ion etching (RIE) process on the substrate.

According to an embodiment of the present invention, in the method for manufacturing the above capacitor structure, the method for removing part of the conductive column material layer may include the following steps. After forming the conductive post material layer, a flat layer filling the grooves is formed on the substrate. An etch-back process is performed on the planar layer, so that the planar layer exposes a portion of the conductive column material layer on the plurality of needles. An etching process is performed on a part of the conductive column material layer exposed by the planar layer.

According to an embodiment of the present invention, the manufacturing method of the above capacitor structure may further include the following steps. After removing at least a portion of the exposed plurality of needles, the planarization layer is removed.

According to an embodiment of the present invention, in the method for manufacturing the above capacitor structure, the method for forming the second electrode and the dielectric layer may include the following steps. A layer of dielectric material is conformally formed on the conductive layer, the plurality of conductive pillars, and the patterned hard mask layer. A layer of electrode material is formed on the layer of dielectric material. A filling material layer filling the grooves is formed on the electrode material layer. A part of the filling material layer, a part of the electrode material layer, a part of the dielectric material layer and the patterned hard mask layer are removed by a chemical mechanical polishing process to form the filling layer, the second electrode and the dielectric layer.

According to an embodiment of the present invention, in the method for manufacturing the above capacitor structure, the method for forming the capacitor may include the following steps. A patterned hard mask layer is formed on the substrate. Using the patterned hard mask layer as a mask, part of the substrate is removed to form a groove and a plurality of needles on the substrate in the groove. A layer of conductive post material is conformally formed on the substrate, the plurality of needles, and the patterned hard mask layer. Part of the material layer of the conductive pillar is removed to form a plurality of conductive pillars and expose a plurality of needles. At least a portion of the exposed plurality of needles is removed. Remove the patterned hardmask layer. A conductive layer is conformally formed on the substrate and the plurality of conductive posts. A dielectric layer is formed on the conductive layer. A second electrode is formed on the dielectric layer.

According to an embodiment of the present invention, in the method for manufacturing the above capacitor structure, the method for forming the capacitor may include the following steps. A patterned hard mask layer is formed on the substrate. Using the patterned hard mask layer as a mask, part of the substrate is removed to form a groove and a plurality of needles on the substrate in the groove. A layer of conductive post material is conformally formed on the substrate, the plurality of needles, and the patterned hard mask layer. An etch-back process is performed on the conductive pillar material layer to form a plurality of conductive pillars and expose a plurality of needles, a part of the substrate and a patterned hard mask layer. At least a portion of the exposed needles and a portion of the base are removed. A conductive layer is conformally formed on the substrate, the plurality of conductive pillars, and the patterned hard mask layer. A dielectric layer is formed on the conductive layer. A second electrode is formed on the dielectric layer.

According to an embodiment of the present invention, in the manufacturing method of the above capacitor structure, the substrate positioned in the groove may have a plurality of upper surfaces. The plurality of upper surfaces can have various heights. A portion of the plurality of upper surfaces may be lower than bottoms of the plurality of conductive pillars.

Based on the above, in the capacitor structure and its manufacturing method proposed by the present invention, the first electrode includes a plurality of conductive pillars with various pitches and a conductive layer connected to the plurality of conductive pillars. Since the plurality of conductive pillars can effectively increase the surface area of the first electrode, the capacitance of the capacitor can be increased.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Embodiments are listed below and described in detail with accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, for the convenience of understanding, the same components will be described with the same symbols in the following description.

1A-1J are cross-sectional views of the fabrication process of capacitor structures according to some embodiments of the invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. Next, a patterned hard mask layer 102 is formed on the substrate 100 . The material of the patterned hard mask layer 102 is, for example, silicon oxide. In some embodiments, the method for forming the patterned hard mask layer 102 may include the following steps, but the invention is not limited thereto. First, a hard mask material layer (not shown) and a patterned photoresist layer 104 can be sequentially formed on the substrate 100 . The forming method of the hard mask material layer is, for example, chemical vapor deposition or physical vapor deposition. The patterned photoresist layer 104 can be formed by a photolithography process. Next, the patterned photoresist layer 104 can be used as a mask to remove part of the hard mask material layer to form the patterned hard mask layer 102 . The method for removing part of the hard mask material layer is, for example, dry etching.

Then, the patterned photoresist layer 104 and the patterned hard mask layer 102 can be used as a mask to remove part of the substrate 100 to form the groove R and the black silicon on the substrate 100 in the groove R. ) 106 (ie, a plurality of needles 108). Accordingly, the substrate 100 can have a groove R. Referring to FIG. The black silicon 106 can be a part of the substrate 100 . In addition, the black silicon 106 can have a needle-shaped surface structure, and can have very low reflectivity and very high incident light absorption. For example, the black silicon 106 can include a plurality of needles 108 . In some embodiments, the plurality of needles 108 may have various pitches P1 and various heights H1. The method for forming the groove R and the needles 108 is, for example, performing a reactive ion etching process on the substrate 100 .

Referring to FIG. 1B , the patterned photoresist layer 104 can be removed. The removal method of the patterned photoresist layer 104 is, for example, dry stripping or wet stripping. Next, a patterned photoresist layer 109 may be formed on the patterned hard mask layer 102 . The patterned photoresist layer 109 can be formed by a photolithography process.

Then, a conductive layer 110 may be formed in the substrate 100 and the plurality of needles 108 around the groove R. Referring to FIG. In this embodiment, the conductive layer 110 may be a doped region. The method for forming the conductive layer 110 is, for example, using the patterned photoresist layer 109 as a mask to perform an ion implantation process on the substrate 100 and the plurality of needles 108 .

Referring to FIG. 1C , the patterned photoresist layer 109 can be removed. The removal method of the patterned photoresist layer 109 is, for example, a dry stripping method or a wet stripping method. Next, a conductive post material layer 112 may be conformally formed on the substrate 100 , the plurality of needles 108 and the patterned hard mask layer 102 . The material of the conductive column material layer 112 is, for example, a conductive material such as titanium nitride (TiN). The method of forming the conductive column material layer 112 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 1D , after the conductive column material layer 112 is formed, a flat layer 114 filling the groove R may be formed on the substrate 100 . The planarization layer 114 is, for example, an organic planarization layer (OPL). The method of forming the flat layer 114 is, for example, a spin coating method.

Referring to FIG. 1E , an etch-back process may be performed on the planar layer 114 , so that the planar layer 114 exposes a portion of the conductive column material layer 112 on the plurality of needles 108 . The aforementioned etch back process is, for example, a dry etching process.

Referring to FIG. 1F , an etching process may be performed on a portion of the conductive column material layer 112 exposed by the planar layer 114 . Thereby, part of the conductive column material layer 112 can be removed to form a plurality of conductive columns 112 a and expose a plurality of needles 108 . In addition, etch selectivity can also be adjusted so that etching back the planar layer 114 ( FIG. 1E ) and etching part of the conductive pillar material layer 112 ( FIG. 1F ) are combined into one etching step. In this embodiment, the electrode 116 can be formed by the above method. The electrode 116 may include a plurality of conductive pillars 112 a and a conductive layer 110 . The conductive layer 110 is connected to a plurality of conductive pillars 112a. In some embodiments, after performing the above etching process, part of the needles 108 may not be exposed. The above etching process is, for example, a dry etching process or a wet etching process.

Referring to FIG. 1G , after forming the plurality of conductive pillars 112a, at least a portion of the plurality of exposed needles 108 may be removed. In this embodiment, it is taken as an example to completely remove the exposed needles 108 , but the invention is not limited thereto. In other embodiments, a portion of the exposed needle 108 may be removed, leaving a portion of the needle 108 . In other embodiments, in addition to completely removing the exposed needles 108 , a portion of the substrate 100 below the exposed needles 108 may be removed. A method for removing at least a part of the plurality of needles 108 is, for example, dry etching.

Next, after removing at least a portion of exposed plurality of needles 108, planarization layer 114 may be removed. The method of removing the flat layer 114 is, for example, wet etching.

Referring to FIG. 1H , a dielectric material layer 118 may be conformally formed on the conductive layer 110 , the plurality of conductive pillars 112 a and the patterned hard mask layer 102 . The material of the dielectric material layer 118 is, for example, a high dielectric constant material. The method for forming the dielectric material layer 118 is, for example, chemical vapor deposition.

Next, an electrode material layer 120 may be formed on the dielectric material layer 118 . The material of the electrode material layer 120 is, for example, a conductive material such as titanium nitride (TiN). The method for forming the electrode material layer 120 is, for example, chemical vapor deposition or physical vapor deposition.

Then, a filling material layer 122 filling the groove R may be formed on the electrode material layer 120 . The material of the filling material layer 122 is, for example, silicon oxide, such as tetraethoxysilane (tetraethyl orthosilicate, TEOS) silicon oxide. The method for forming the filling material layer 122 is, for example, chemical vapor deposition.

Referring to FIG. 1I, a part of the filling material layer 122, a part of the electrode material layer 120, a part of the dielectric material layer 118 and the patterned hard mask layer 102 can be removed by a chemical mechanical polishing process to form the filling layer 122a, the electrode 120a and The dielectric layer 118a exposes the conductive layer 110 . Accordingly, a dielectric layer 118a can be formed on the conductive layer 110 and the plurality of conductive pillars 112a, and an electrode 120a can be formed on the dielectric layer 118a. In addition, the capacitor 124 can be formed by the method described above. The capacitor 124 includes an electrode 116, an electrode 120a and a dielectric layer 118a.

Referring to FIG. 1J , a dielectric layer 126 covering the capacitor 124 may be formed on the substrate 100 . The material of the dielectric layer 126 is, for example, silicon oxide. The forming method of the dielectric layer 126 is, for example, chemical vapor deposition.

Next, a contact window 128 may be formed in the dielectric layer 126, and a contact window 130 may be formed in the dielectric layer 126 and the filling layer 122a. The contact window 128 is electrically connected to the conductive layer 110 of the electrode 116 . The contact window 130 is electrically connected to the electrode 120a. The material of the contact window 128 and the contact window 130 is, for example, a conductive material such as tungsten. In some embodiments, the contact window 128 and the contact window 130 may be formed by a damascene process.

In addition, although the method for forming the capacitor structure 10 is described by taking the above method as an example, the present invention is not limited thereto. In some other embodiments, after forming the structure shown in FIG. 1G , a double patterning process can be performed by using the conductive pillars 112a as a core pattern, thereby forming more conductive pillars, and Helps increase electrode surface area.

Hereinafter, the capacitor structure 10 of the above-mentioned embodiment will be described with reference to FIG. 1J .

Referring to FIG. 1J , the capacitor structure 10 includes a substrate 100 and a capacitor 124 . The substrate 100 has a groove R. Referring to FIG. In some embodiments, the substrate 100 may be a substrate of an interposer, that is, the capacitor structure of this embodiment may be integrated with the interposer. In some embodiments, the interposer may have components such as through silicon vias (TSVs) and redistribution layers (RDLs). In addition, the substrate 100 may have at least one needle 108 located in the groove R. As shown in FIG. The number of needles 108 is not limited to that shown in FIG. 1J . As long as the number of needles 108 is at least one, it falls within the scope of the present invention. In addition, the substrate 100 located in the groove R may have a plurality of upper surfaces S1. The plurality of upper surfaces S1 may have various heights H2. For example, the height H2 of the upper surface S12 may be higher than the height H2 of the upper surface S11.

The capacitor 124 includes an electrode 116, an electrode 120a and a dielectric layer 118a. The electrode 116 includes a plurality of conductive columns 112 a and a conductive layer 110 . A plurality of conductive pillars 112a are located on the substrate 100 in the groove R. As shown in FIG. There are various pitches P2 between the plurality of conductive pillars 112a. The plurality of conductive pillars 112a can have various heights H3. For example, the height H3 of the conductive pillar 112a1 may be higher than the height H3 of the conductive pillar 112a4. The plurality of conductive pillars 112a can extend away from the substrate 100 . The bottoms of two adjacent conductive pillars 112a (eg, the conductive pillars 112a1 and the conductive pillars 112a2 ) can be connected to each other, but the invention is not limited thereto. Parts of the plurality of conductive pillars 112 a (eg, the conductive pillars 112 a 3 and the conductive pillars 112 a 4 ) can be located on the sidewalls of the needles 108 . The tops of two adjacent conductive pillars 112a (eg, the conductive pillars 112a3 and the conductive pillars 112a4 ) on the sidewall of the needle 108 may be connected to each other, but the invention is not limited thereto. The conductive layer 110 is connected to a plurality of conductive pillars 112a. In this embodiment, the conductive layer 110 may be a doped region located in the substrate 100 . Electrode 120a is located on electrode 116 . The dielectric layer 118a is located between the electrode 116 and the electrode 120a.

In addition, the capacitor structure 10 may further include at least one of the filling layer 122 a , the dielectric layer 126 , the contact window 128 and the contact window 130 . The filling layer 122a is located in the groove R and located on the electrode 120a. The dielectric layer 126 is on the substrate 100 and covers the capacitor 124 . The contact window 128 is located in the dielectric layer 126 and is electrically connected to the conductive layer 110 of the electrode 116 . The contact window 130 is located in the dielectric layer 126 and the filling layer 122a, and is electrically connected to the electrode 120a.

In addition, the materials and forming methods of each component in the capacitor structure 10 have been described in detail in the above-mentioned embodiments, and will not be further described here.

Based on the above embodiments, in the capacitor structure 10 and its manufacturing method, the electrode 116 includes a plurality of conductive pillars 112 a with various pitches P2 and a conductive layer 110 connected to the plurality of conductive pillars 112 a. Since the plurality of conductive pillars 112 a can effectively increase the surface area of the electrode 116 , the capacitance of the capacitor 124 can be increased.

2A to 2C are cross-sectional views of the manufacturing process of capacitor structures according to other embodiments of the present invention.

The structure of Figure 2A is provided. Please refer to FIG. 1G and FIG. 2A , the differences between the structure of FIG. 2A and the structure of FIG. 1G are as follows. The structure of FIG. 2A can omit the conductive layer 110 in FIG. 1G . That is, the formation method of the structure of FIG. 2A may omit the step of forming the conductive layer 110 . In addition, the same components in the structure of FIG. 2A and the structure of FIG. 1G are represented by the same symbols, and for the same or similar content between the structure of FIG. 2A and the structure of FIG. 1G, reference may be made to the description of the structure of FIG. 1G in the above-mentioned embodiments , which will not be explained here.

Referring to FIG. 2B , after the structure of FIG. 2A is provided, the patterned hard mask layer 102 can be removed. The removal method of the patterned hard mask layer 102 is, for example, a dry etching method or a wet etching method.

Next, after removing the patterned hard mask layer 102 , a conductive layer 210 may be conformally formed on the substrate 100 and the plurality of conductive pillars 112 a. In this embodiment, the electrode 216 can be formed by the above method. The electrode 216 may include a plurality of conductive pillars 112 a and a conductive layer 210 . The conductive layer 210 is connected to the plurality of conductive pillars 112a. The material of the conductive layer 210 is, for example, a conductive material such as titanium nitride (TiN). The forming method of the conductive layer 210 is, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 2C, the dielectric layer 118a, the electrode 120a, the filling layer 122a, the dielectric layer 126, the contact window 128 and the contact window 130 can be formed by referring to the method shown in FIG. 1H to FIG. 1J, and the description thereof is omitted here. .

In addition, although the method for forming the capacitor structure 20 is described by taking the above method as an example, the present invention is not limited thereto. In some other embodiments, after forming the structure in FIG. 2A , a double patterning process can be performed by using the conductive pillars 112 a as core patterns, thereby forming more conductive pillars and improving the electrode surface area. In other embodiments, the conductive layer 210 can be patterned according to requirements, so that the conductive layer 210 has a desired pattern.

Hereinafter, the capacitor structure 20 of the above-mentioned embodiment will be described with reference to FIG. 2C .

Please refer to FIG. 1J and FIG. 2C , the differences between the capacitor structure 20 in FIG. 2C and the capacitor structure 10 in FIG. 1J are as follows. The capacitor structure 20 may omit the conductive layer 110 in FIG. 1J . Additionally, the capacitor structure 20 may include a conductive layer 210 . The conductive layer 210 is connected to the plurality of conductive pillars 112a, and can cover the plurality of conductive pillars 112a. The contact window 128 is electrically connected to the conductive layer 210 . In addition, the same or similar components in the capacitor structure 20 and the capacitor structure 10 are represented by the same or similar symbols, and for the same or similar content in the capacitor structure 20 and the capacitor structure 10, you can refer to the description of the capacitor structure 10 in the above-mentioned embodiments, No further explanation here.

Based on the above-mentioned embodiments, in the capacitor structure 20 and its manufacturing method, the electrode 216 includes a plurality of conductive columns 112 a with various pitches P2 and a conductive layer 210 connected to the plurality of conductive columns 112 a. Since the plurality of conductive pillars 112 a can effectively increase the surface area of the electrode 216 , the capacitance of the capacitor 124 can be increased.

3A to 3E are cross-sectional views of the manufacturing process of capacitor structures according to other embodiments of the present invention.

The structure of Figure 3A is provided. Please refer to FIG. 1C and FIG. 3A , the differences between the structure of FIG. 3A and the structure of FIG. 1C are as follows. The structure of FIG. 3A can omit the conductive layer 110 in FIG. 1C. That is, the formation method of the structure of FIG. 3A can omit the step of forming the conductive layer 110 . In addition, the same components in the structure of FIG. 3A and the structure of FIG. 1C are represented by the same symbols, and for the same or similar content between the structure of FIG. 3A and the structure of FIG. 1C, you can refer to the description of the structure of FIG. 1C in the above-mentioned embodiments , which will not be explained here.

Referring to FIG. 3B, after the structure of FIG. 3A is provided, an etch-back process may be performed on the conductive column material layer 112 to form a plurality of conductive columns 112b, and expose a plurality of needles 108, part of the substrate 100 and the patterned hard substrate. Mask layer 102 . The aforementioned etch back process is, for example, a dry etching process.

Referring to FIG. 3C , after the plurality of conductive pillars 112b are formed, at least a portion of the plurality of exposed needles 108 and a portion of the substrate 100 are removed. Thereby, the height of the needle 108 can be reduced or the needle 108 can be completely removed. As shown in FIGS. 1A and 3C , after reducing the height of the needles 108 , the height H1 of the needles 108 in FIG. 3C is lower than the height H1 of the needles 108 in FIG. 1A . In addition, in this step, due to the influence of etching characteristics, the substrate 100 located between the two conductive pillars 112b with a small distance is not easy to remove, so the substrate 100 here may only be slightly removed or removed. is not removed. The removal method of at least a part of the plurality of needles 108 and a part of the substrate 100 is, for example, a dry etching method.

Referring to FIG. 3D , after removing at least a portion of the plurality of needles 108 and a portion of the substrate 100 , a conductive layer 310 is conformally formed on the substrate 100 , the plurality of conductive pillars 112 b and the patterned hard mask layer 102 . In this embodiment, the electrode 316 can be formed by the above method. The electrode 316 may include a plurality of conductive pillars 112 b and a conductive layer 310 . The conductive layer 310 is connected to the plurality of conductive pillars 112b. The material of the conductive layer 310 is, for example, a conductive material such as titanium nitride (TiN). The conductive layer 310 is formed by, for example, chemical vapor deposition or physical vapor deposition.

Referring to FIG. 3E, the dielectric layer 118a, the electrode 120a, the filling layer 122a, the dielectric layer 126, the contact window 128 and the contact window 130 can be formed by referring to the method shown in FIG. 1H to FIG. 1J, and the description thereof is omitted here. .

In addition, although the method for forming the capacitor structure 30 is described by taking the above method as an example, the present invention is not limited thereto. In some other embodiments, after forming the structure of FIG. 3C , a double patterning process can be performed by using the conductive pillars 112 b as core patterns, thereby forming more conductive pillars and helping to increase the electrode surface area. In other embodiments, the conductive layer 310 can be patterned according to requirements, so that the conductive layer 310 has a desired pattern.

Hereinafter, the capacitor structure 30 of the above-mentioned embodiment will be described with reference to FIG. 3E .

Please refer to FIG. 1J and FIG. 3E , the differences between the capacitor structure 30 in FIG. 3E and the capacitor structure 10 in FIG. 1J are as follows. The capacitor structure 30 may omit the conductive layer 110 in FIG. 1J . Additionally, the capacitor structure 30 may include a conductive layer 310 . The conductive layer 310 is connected to the plurality of conductive pillars 112b, and can cover the plurality of conductive pillars 112b. The contact window 128 is electrically connected to the conductive layer 310 .

In addition, the substrate 100 located in the groove R may have a plurality of upper surfaces S2. The plurality of upper surfaces S2 may have various heights H4. For example, the height H4 of the upper surface S22 may be higher than the height H4 of the upper surface S21. A part of the plurality of upper surfaces S2 may be lower than the bottoms of the plurality of conductive pillars 112b. For example, the upper surface S21 may be lower than the bottoms of the plurality of conductive pillars 112b. In this way, the depth of the conductive layer 310 can be increased to increase the surface area of the conductive layer 310 , thereby increasing the capacitance of the capacitor 124 .

In addition, the plurality of conductive pillars 112b can have various heights H5. For example, the height H5 of the conductive pillar 112b1 may be higher than the height H5 of the conductive pillar 112b4. The plurality of conductive pillars 112b can extend away from the substrate 100 . The bottoms of two adjacent conductive columns 112b (eg, conductive column 112b1 and conductive column 112b2 ) may not be connected to each other, and the tops of adjacent two conductive columns 112b (eg, conductive column 112b3 and conductive column 112b4 ) may not be connected to each other, but The present invention is not limited thereto. Parts of the plurality of conductive pillars 112b (eg, the conductive pillars 112b1 and the conductive pillars 112b2 ) can be located on the sidewalls of the needles 108 . In this embodiment, another part of the plurality of conductive pillars 112b (eg, the conductive pillars 112b3 and the conductive pillars 112b4 ) may not be located on the sidewall of the needle 108 .

In addition, the same or similar components in the capacitor structure 30 and the capacitor structure 10 are represented by the same or similar symbols, and for the same or similar content in the capacitor structure 30 and the capacitor structure 10, you can refer to the description of the capacitor structure 10 in the above-mentioned embodiments, No further explanation here.

Based on the above embodiments, in the capacitor structure 30 and the manufacturing method thereof, the electrode 316 includes a plurality of conductive pillars 112b with various pitches P2 and a conductive layer 310 connected to the plurality of conductive pillars 112b. Since the plurality of conductive pillars 112 b can effectively increase the surface area of the electrode 316 , the capacitance of the capacitor 124 can be increased.

To sum up, in the capacitor structure and manufacturing method of the above embodiments, the surface area of the electrodes can be increased by using a plurality of conductive pillars, thereby increasing the capacitance of the capacitor.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10,20,30: Capacitor structure 100: base 102: Patterned hard mask layer 104,109: Patterned photoresist layer 106: black silicon 108: Needles 110,210,310: conductive layer 112: conductive column material layer 112a, 112a1~112a4, 112b, 112b1~112b4: conductive pillars 114: flat layer 116, 120a, 216, 316: electrodes 118: dielectric material layer 118a, 126: dielectric layer 120: electrode material layer 122: Filling material layer 122a: filling layer 124: Capacitor 128,130: contact window H1~H5: Height P1, P2: Pitch R: Groove S1, S11, S12, S2, S21, S22: upper surface

1A-1J are cross-sectional views of the fabrication process of capacitor structures according to some embodiments of the invention. 2A to 2C are cross-sectional views of the manufacturing process of capacitor structures according to other embodiments of the present invention. 3A to 3E are cross-sectional views of the manufacturing process of capacitor structures according to other embodiments of the present invention.

10: Capacitor structure

100: base

108: Needles

110: conductive layer

112a, 112a1~112a4: conductive pillars

116,120a: electrode

118a, 126: dielectric layer

122a: filling layer

124: Capacitor

128,130: contact window

H2, H3: Height

P2: Pitch

R: Groove

S1, S11, S12: upper surface

Claims (20)

A capacitor structure comprising: a base having grooves; and Capacitors, including: first electrode, including: a plurality of conductive posts on the base in the groove, with various spacings between the plurality of conductive posts; and a conductive layer connected to a plurality of the conductive pillars; a second electrode on said first electrode; and The dielectric layer is located between the first electrode and the second electrode. The capacitor structure as claimed in claim 1, wherein a plurality of the conductive pillars extend away from the substrate. The capacitor structure of claim 1, wherein the conductive layer includes a doped region in the substrate. The capacitor structure according to claim 1, wherein the conductive layer covers a plurality of the conductive pillars. The capacitor structure according to claim 1, wherein the bottoms of two adjacent conductive pillars are connected to each other. The capacitor structure of claim 1, wherein said substrate has at least one needle positioned in said groove. The capacitor structure as claimed in claim 6, wherein a portion of the plurality of conductive posts are located on sidewalls of the needles. The capacitor structure according to claim 7, wherein the tops of two adjacent conductive pillars located on the sidewalls of the needles are connected to each other. The capacitor structure as claimed in claim 1, wherein the base located in the groove has a plurality of upper surfaces, and the plurality of upper surfaces have various heights. The capacitor structure as claimed in claim 1, wherein the plurality of conductive pillars have various heights. The capacitor structure of claim 1, wherein the substrate comprises a substrate of an interposer. A method of manufacturing a capacitor structure, comprising: providing a substrate, wherein the substrate has grooves; and forming a capacitor, wherein the capacitor comprises: first electrode, including: a plurality of conductive posts on the base in the groove, with various spacings between the plurality of conductive posts; and a conductive layer connected to a plurality of the conductive pillars; a second electrode on said first electrode; and The dielectric layer is located between the first electrode and the second electrode. The method for manufacturing a capacitor structure according to claim 12, wherein the method for forming a capacitor comprises: forming a patterned hard mask layer on the substrate; using the patterned hard mask layer as a mask, removing part of the substrate to form the groove and a plurality of needles on the substrate in the groove; forming the conductive layer in the base and the plurality of needles around the groove; conformally forming a layer of conductive post material on the substrate, the plurality of needles, and the patterned hard mask layer; removing part of the conductive column material layer to form a plurality of the conductive columns and expose a plurality of the needles; removing at least a portion of the exposed plurality of needles; forming the dielectric layer on the conductive layer and the plurality of conductive pillars; and The second electrode is formed on the dielectric layer. The method for manufacturing a capacitor structure as claimed in claim 13, wherein the method for forming the groove and the needle-shaped object includes performing a reactive ion etching process on the substrate. The method for manufacturing a capacitor structure according to claim 13, wherein the method for removing part of the conductive column material layer includes: After forming the conductive column material layer, forming a flat layer filling the groove on the substrate; performing an etch-back process on the planar layer, so that the planar layer exposes part of the conductive column material layer on the plurality of needles; and An etching process is performed on the portion of the conductive column material layer exposed by the planar layer. The method for manufacturing a capacitor structure as described in Claim 15, further comprising: The planarization layer is removed after removing at least a portion of the exposed plurality of needles. The method for manufacturing a capacitor structure according to claim 13, wherein the method for forming the second electrode and the dielectric layer comprises: conformally forming a layer of dielectric material over the conductive layer, the plurality of conductive pillars, and the patterned hard mask layer; forming a layer of electrode material on the layer of dielectric material; forming a filling material layer filling the groove on the electrode material layer; and removing part of the filling material layer, part of the electrode material layer, part of the dielectric material layer and the patterned hard mask layer by a chemical mechanical polishing process to form a filling layer, the second electrode and the patterned hard mask layer. the dielectric layer. The method for manufacturing a capacitor structure according to claim 12, wherein the method for forming a capacitor comprises: forming a patterned hard mask layer on the substrate; using the patterned hard mask layer as a mask, removing part of the substrate to form the groove and a plurality of needles on the substrate in the groove; conformally forming a layer of conductive post material on the substrate, the plurality of needles, and the patterned hard mask layer; removing part of the conductive column material layer to form a plurality of the conductive columns and expose a plurality of the needles; removing at least a portion of the exposed plurality of needles; removing the patterned hard mask layer; conformally forming the conductive layer on the substrate and the plurality of conductive pillars; forming the dielectric layer on the conductive layer; and The second electrode is formed on the dielectric layer. The method for manufacturing a capacitor structure according to claim 12, wherein the method for forming a capacitor comprises: forming a patterned hard mask layer on the substrate; using the patterned hard mask layer as a mask, removing part of the substrate to form the groove and a plurality of needles on the substrate in the groove; conformally forming a layer of conductive post material on the substrate, the plurality of needles, and the patterned hard mask layer; performing an etch-back process on the conductive pillar material layer to form a plurality of the conductive pillars and expose a plurality of the needles, a part of the substrate and the patterned hard mask layer; removing at least a portion of the plurality of exposed needles and a portion of the substrate; conformally forming the conductive layer on the substrate, the plurality of conductive pillars, and the patterned hard mask layer; forming the dielectric layer on the conductive layer; and The second electrode is formed on the dielectric layer. The method for manufacturing a capacitor structure as claimed in claim 19, wherein the substrate positioned in the groove has a plurality of upper surfaces, the plurality of upper surfaces have various heights, and a part of the plurality of upper surfaces lower than the bottoms of the plurality of conductive pillars.

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