TW202307817A - Gate of array driving circuit and display panel including the same - Google Patents

Abstract

A gate of array driving circuit and a display panel including the same are disclosed. The gate of array driving circuit and the source driving circuit are disposed on the same side of the display area, so as to drive the plurality of pixels in the display area. The gate of array driving circuit includes a plurality of shift registers. The plurality of shift registers are arranged as multiple sets of serial circuits. Among the plurality of shift registers, the shift registers with the same pull-up signal transmission path are arranged adjacently in the same group of serial circuits.

Description

Gate driving circuit and display panel including same

The present invention relates to a gate drive circuit and a display panel including it, in particular to a gate drive circuit and a display panel including the gate drive circuit which reduces the circuit configuration width by grouping shift registers to achieve a narrow frame design panel.

In the competition of the panel industry, thin, light and small products have always been the design goals of various companies. For display panels, in order to achieve a narrow frame or no frame design, it seems to be a way to integrate the gate driver chip on the glass substrate. feasible solution. Therefore, under design and cost considerations, the application of the Gate Driver on Array (GOA) has become a technical subject that various manufacturers are competing to study.

In order to reduce the width of the peripheral circuits of the display panel, various changes or simplifications can be made to the design of the circuit components to save the installation space. However, many simplified circuits may cause various abnormalities or abnormalities during the operation of the display panel in actual operation The poor display effect reduces the display quality of the device instead. How to reduce the installation space required by the driving circuit without affecting the operation of the driving circuit will be the main problem to be solved in the design of the narrow bezel display device.

In view of the foregoing, the inventor of the present invention conceived and designed a gate drive circuit and a display panel including it, in order to improve the problems of the conventional technology, and further enhance the implementation and utilization in the industry.

In view of the problems described in the prior art, the object of the present invention is to provide a gate drive circuit and a display panel including it, and change the circuit configuration to reduce the width of the frame, thereby solving the problem of a display panel originally designed with a gate drive circuit and a gate drive circuit. Due to the difference in the width of the borders, the display panels with the polar chip design cannot share the mechanism design.

Based on the above purpose, the present invention provides a gate driving circuit, the gate driving circuit and the source driving circuit are arranged on the same side of the display area, and are used to drive a plurality of pixels in the display area. The gate drive circuit includes a plurality of shift registers, and the plurality of shift registers receive n-phase clock signals. After being controlled by the pull-up signal of this stage, the a-stage shift register is controlled, and before being pulled down by the pull-down signal of this stage, b Stage shift register, a, b, n are positive integers. A plurality of shift registers are configured as a series connection circuit of m groups, m is a positive integer between 2 and a and m is a factor of a, the shift registers with the same pull-up signal transmission path among the plurality of shift registers The bit registers are adjacently arranged in the same group of serial circuits.

In an embodiment of the present invention, shift registers having the same pull-down signal transmission path among the plurality of shift registers can be adjacently arranged in the same group of serial circuits.

In an embodiment of the present invention, the plurality of shift registers may respectively include a wiring area, a first circuit area, a transmission line area, and a second circuit area.

In an embodiment of the present invention, a plurality of clock signal lines can be arranged in the wiring area, and the number of the plurality of clock signal lines is n/m.

In an embodiment of the present invention, the transmission line area may include signal transmission lines for transmitting pull-up signals and pull-down signals.

In an embodiment of the present invention, the first circuit area may include a pull-down circuit, and the second circuit area may include a pull-up circuit.

In the embodiment of the present invention, a plurality of shift registers can receive sixteen-phase clock signals. memory.

In the embodiment of the present invention, the series connection circuits can be divided into two groups, four groups or eight groups.

The present invention provides a display panel including a gate drive circuit, which includes a display area and a peripheral circuit area, the peripheral circuit area is arranged on one side of the display area, and the peripheral circuit area includes the aforementioned gate drive circuit, the gate The driving circuit is respectively connected to a plurality of pixels in the display area, and transmits a gate driving signal to drive the plurality of pixels.

In an embodiment of the present invention, the peripheral circuit area may include source driving circuits, the source driving circuits are respectively connected to the plurality of pixels in the display area, and transmit data signals to the plurality of pixels.

Based on the above, the gate drive circuit of the present invention and the display panel including it can be arranged adjacent to the shift register circuits with the same pull-up signal transmission path or the same pull-down signal transmission path, so that the gate drive circuit can be divided into two parts. For multiple groups of series-connected circuits, the line configuration space is reduced by reducing the wiring area and the transmission line area, and the goal of reducing the width of the peripheral circuit is achieved. Without changing the internal drive circuit components of the gate drive circuit, the The effect of reducing the width of the panel perimeter.

In order to facilitate the understanding of the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby combined with the accompanying drawings and described in detail in the form of embodiments as follows, and the purpose of the drawings used therein is only For the purpose of illustrating and assisting the description, it may not be the true proportion and precise configuration of the present invention after implementation. Therefore, the scale and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Description.

In the drawings, the thickness or width of substrates, panels, regions, lines, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a substrate, panel, region, or line is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" means that other elements exist between two elements. In addition, it should be understood that although the terms "first", "second", and "third" may be used herein to describe various elements, components, regions, layers and/or sections, they are used to refer to an element, component , region, layer and/or section from another element, component, region, layer and/or section. Therefore, they are for descriptive purposes only and should not be construed as indicating or implying relative importance or ordering relationship thereof.

Unless otherwise defined, all terms used herein have the meanings commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

Please refer to FIG. 1 , which is a schematic diagram of a gate drive circuit grouping according to an embodiment of the present invention. As shown in the figure, the display panel 100 includes a display area AA and a peripheral circuit area NA. The peripheral circuit area NA is disposed on the sky side of the display area AA. The peripheral circuit area NA includes a gate driving circuit 10. The display area AA includes a plurality of pixels 21. Composed of pixel matrix 20 . The gate drive circuit 10 and the source drive circuit are arranged on the same side, the gate drive circuit 10 transmits the gate drive signal G to each pixel row in the pixel matrix 20, and drives each pixel 21 in the pixel row to write into the source drive circuit The transmitted data signal D is used to present the display image of the display area AA. The gate driving circuit 10 and the source driving circuit are arranged on the same side of the display area AA, which can reduce the width of the peripheral circuit NA on the side of the display area AA, so that the display panel 100 conforms to the design of a narrow bezel display device.

The gate drive circuit 10 includes a plurality of shift registers connected in series, and the number of the plurality of shift registers is different according to the pixel columns of the pixel matrix 20. In this embodiment, the plurality of shift registers It includes the first-stage shift register G1, the second-stage shift register G2... to the 2160th-stage shift register G2160. The gate drive circuit 10 receives the 16-phase clock signal, the plurality of shift registers are controlled by the pull-up signal of the current level, and the rear 8-level shift register is controlled by the pull-up signal of the current level. The shift register receives the clock signal, pulls down the voltage level provided by the pull-up signal to a predetermined level through the pull-down signal, and outputs it to the corresponding pixel row to drive each pixel 21 in the pixel row. The plurality of shift registers includes a plurality of chip-on-film (Chip on film) areas COF1~COF8, which are set to provide clock signal sources to provide clock signals required by each shift register.

In a general gate drive circuit 10, a plurality of shift registers are arranged in order of pixel columns, that is, from the first-stage shift register G1, the second-stage shift register G2... to the second-stage shift register The sequence arrangement of the 2160-level shift register G2160 is set. However, the shift register is controlled by the pull-up signal of this stage, and the shift register of stage b before being pulled down by the pull-down signal of this stage. A and b are positive integers. If each The shift registers are arranged adjacent to each other with shift registers having the same pull-up signal transmission path, or the shift registers with the same pull-down signal transmission path are arranged adjacent to each other , in the routing configuration of the pull-up signal or the pull-down signal, it can effectively reduce the wiring configuration space, thereby reducing the width W of the NA setting of the peripheral circuit. In addition, the configuration of the clock signal can also be reduced accordingly, further reducing the width W of the peripheral circuit NA setting.

In this embodiment, 2160 shift registers can be divided into 8 groups of serially connected circuits, which are the order of the first serially connected circuit GOA1, the second serially connected circuit GOA2, ... to the eighth serially connected circuit GOA8 configuration. The first series circuit GOA1 includes the first stage shift register G1, the ninth stage shift register G9... to the 2153rd stage shift register G2153; the second series circuit GOA2 includes the second stage The shift register G2, the 10th stage shift register G10... to the 2154th stage shift register G2154; and so on. Since the shift register is the 8-stage shift register controlled by the pull-up signal of this stage, the ninth-stage shift register G9 receives the control signal of the first-stage shift register G1, and the 17th-stage shift register G9 receives the control signal of the first-stage shift register G1. The bit register G17 receives the control signal of the ninth shift register G9, and so on, that is, the transmission path of the same pull-up signal in the first serial circuit GOA1, and the line does not need to cross other shift registers Registers to reduce the space required for line configuration. On the pull-down signal transmission path, the shift register pulls down the previous 8-stage shift register through the pull-down signal of this stage, and the first-stage shift register G1 receives the control signal of the ninth-stage shift register G9 , the shift register G9 of the ninth stage receives the control signal of the shift register G17 of the seventeenth stage, and so on, each shift register in the first serial connection circuit GOA1 has the same pull-down signal transmission path. The traces for these signal transmissions can also be arranged adjacently in the same group of serial circuits without crossing over other shift registers.

In the above gate drive circuit 10, the number of stages of the 8-stage shift register after pull-up and the 8-stage shift register before pull-down is the same (a=b), so the best line saving can be obtained in grouping effect. In other embodiments, the number of pull-up or pull-down stages of the shift register may be different. In terms of group configuration, the configuration with the same transmission path of the pull-up signal can be selected as the same group, or the configuration with the same transmission path of the pull-down signal can be selected. for the same group. As for the number of groups (m), if the same pull-up signal is divided into the same group with the same path, then m is a positive integer between 2 and a and m is a factor of a. In this embodiment, a=8 is For example, a plurality of shift registers can be divided into different groups such as 2 groups, 4 groups, and 8 groups. The more the number of different groups, the greater the width of the line savings. The number of groups can be based on the required width of the peripheral circuit NA or with The display panel 100 is determined based on the requirements of related organizations.

Please refer to FIG. 2 , which is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. The gate drive circuit includes a plurality of shift registers. As shown in the figure, the circuit configuration of the shift register 30 includes a wiring area 31, a first circuit area 32, a transfer line area 33, and a second circuit area 34. . The wiring area 31 includes various signal lines of the gate drive circuit, such as clock signal lines and voltage signal lines. These lines are coupled to the first circuit area 32, and the first circuit area 32 includes a pull-down circuit, which is coupled to the second circuit area. The pull-up circuit in the second circuit area 34, the pull-up circuit receives the pull-up signal and the clock signal of the previous stage a, and pulls the voltage of the voltage node to a high level, and the pull-down circuit uses the pull-down signal of the next stage b to shift the temporary The node voltage of the register is pulled down to a predetermined level, and the gate drive signal is output from the output terminal. In order to transmit the control signal between the pull-up circuit and the pull-down circuit, a transmission line area 33 for transmitting the pull-up signal and the pull-down signal is provided between the first circuit area 32 and the second circuit area 34, and the signal is transmitted through the transmission line area 33 To the pull-up circuit or pull-down circuit of the previous a stage or the rear b stage.

As described in the foregoing embodiment, the pull-up circuit of the shift register 30 receives the pull-up control signals of the first 8 stages, and the pull-down circuit receives the pull-down control signals of the last 8 stages. Under the original sequence configuration, the transmission line area 33 needs Set up 9 wires for transmitting pull-up control signals and 9 wires for transmitting pull-down control signals. Under the configuration of this embodiment, the shift registers with the same pull-up signal transmission path and the same pull-down signal transmission path are adjacently arranged in the same group of serial circuits, and there is no need to arrange cross-level wiring, and the transmission line area 33 The wiring can be reduced to one pull-up control signal wiring and one transmission pull-down control signal wiring, reducing the wiring configuration space required for the transmission line area 33 , thereby reducing the configuration space required for the shift register 30 .

In addition to reducing the configuration space of the transfer line area 33, among the above serial circuits, the shift registers arranged adjacently only use part of the clock signal. For example, only the first serial circuit GOA1 needs to use the first clock signal and the ninth clock signal to drive, there is no need to draw all 16-phase clock signal traces in the wiring area 31, which can reduce the configuration space of 14 signal traces and reduce the need for shift register 30. configuration space. By arranging the shift registers 30 of the same transfer path adjacently in the same group of serial circuits, the configuration space required for the wiring area 31 and the transfer line area 33 can be effectively reduced, thereby reducing the cost of each shift register. The setting width reduces the space configuration required by the gate drive circuit and meets the design requirements of the narrow frame of the display device.

Please refer to FIG. 3 , which is a schematic circuit diagram of a gate driving circuit according to an embodiment of the present invention. Please refer to FIG. 2 at the same time. As shown in the figure, the circuit configuration of the shift register 30A includes a pull-down circuit 32a and a pull-up circuit 34a. The pull-down circuit 32a and the pull-up circuit 34a are circuit configurations of 19 transistors (T11~T64) and 1 capacitor (C), wherein the pull-up circuit 34a is coupled to the high voltage source VGHD, and receives the clock signal HC1 and the first 8 stages The pull-up control signal ST(n-8) pulls up the voltage of the node Q(n) to a high level. The pull-down circuit 32a is coupled to the low-voltage sources VSSQ and VSSG. After receiving the 8-level pull-down control signal ST(n+8), the voltage of the node Q(n) is pulled down to a predetermined level, so that the shift register 30A can output the corresponding The control signal to drive the gate of each pixel.

In this embodiment, the transmission lines of the pull-up control signal ST(n-8) and the pull-down control signal ST(n+8) are coupled to the transmission line area 33a. The shift registers of the last 8 stages are arranged adjacent to each other, so there is no need to set a cross-stage transmission line, which can effectively reduce the installation space of the transmission line area 33a. The transmission line of the clock signal HC1 is arranged in the wiring area 31. Similar to the control signal, the same group of serial circuits only need to set the corresponding clock signal transmission line, which can reduce the setting space of the wiring area 31. Therefore, in the When the required transmission lines are reduced, the installation space required by the gate drive circuit can be reduced, and the installation width of peripheral circuits can be reduced.

Please refer to FIG. 4, which is a schematic diagram of the peripheral circuit area of the embodiment of the present invention. As shown in the figure, the peripheral circuit area 40 includes a gate drive circuit 41 and a wiring area 42. The gate drive circuit 41 includes a first-stage shift register G1, a second-stage shift register G2... to In the 2160th level shift register G2160, the wiring area 42 includes the first clock signal HC1, the second clock signal HC2... to the 16th clock signal HC16 and other wiring areas LC/VSS. The gate driving circuit 41 receives the 16-phase clock signal, and each shift register is controlled by the pull-up signal of its own level to the rear 8 shift registers, and the first 8 shift registers are pulled down by the pull-down signal of the current level.

In this embodiment, the gate drive circuit 41 arranges the shift registers in groups to form 8 sets of series circuits (GOA1~GOA8). In the first series circuit GOA1, the first stage shift registers arranged adjacently The bit register G1, the shift register G9 of the 9th stage ... to the shift register G2153 of the 2153rd stage, and other wiring areas LC/VSS, The first clock signal HC1 and the ninth clock signal HC9. The second series circuit GOA2 includes the second-stage shift register G2, the tenth-stage shift register G10... to the 2154th-stage shift register G2154, and other cables are arranged correspondingly area LC/VSS, the second clock signal HC2 and the tenth clock signal HC10, and so on. Similar to the foregoing embodiments, the transmission line of the gate drive circuit 41 between the pull-up circuit and the pull-down circuit can be configured in groups to reduce the configuration space of the gate circuit 41, and at the same time, the number of clock signals configured in each series circuit is 2. Compared with the configuration space required by the original 16 clock signal lines, the width of the peripheral circuit 40 can also be significantly reduced.

Please refer to FIG. 5 , which is a schematic diagram of another group of peripheral circuit areas according to an embodiment of the present invention. As shown in the figure, the peripheral circuit area 50 includes a gate drive circuit 51 and a wiring area 52, and the gate drive circuit 51 includes a first-stage shift register G1, a second-stage shift register G2... to In the 2160th stage shift register G2160, the wiring area 52 includes the first clock signal HC1, the second clock signal HC2... to the 16th clock signal HC16 and other wiring areas LC/VSS. The gate drive circuit 51 receives the 16-phase clock signal, and each shift register is controlled by the pull-up signal of its own level to the rear 8 shift registers, and the first 8 shift registers are pulled down by the pull-down signal of the same level.

In this embodiment, the gate drive circuit 51 arranges shift registers in groups to form 4 sets of series circuits (GOA1~GOA4). In the first series circuit GOA1, the first stage shift registers arranged adjacent From the bit register G1, the shift register G5 of the 5th stage... to the shift register G2157 of the 2157th stage, other wiring areas LC/VSS, The first clock signal HC1, the fifth clock signal HC5, the ninth clock signal HC9, and the thirteenth clock signal HC13. The second series connection circuit GOA2 includes the second-level shift register G2, the sixth-level shift register G6... to the 2158th-level shift register G2158, and other cables are arranged correspondingly area LC/VSS, the second clock signal HC2, the sixth clock signal HC6, the tenth clock signal HC10, and the fourteenth clock signal HC14, and so on. The transfer line of the gate drive circuit 51 between the pull-up circuit and the pull-down circuit can reduce the configuration space of the gate circuit 51 according to the grouping configuration, and at the same time, the number of clock signals configured in each serial circuit is 4, compared with the original The configuration space required by 16 clock signal lines can also significantly reduce the width of the peripheral circuit 50 . In another embodiment, the gate drive circuit can be further divided into two groups of series circuits, and the shift registers with the same pull-up control signal transmission path or the same pull-down signal transmission path are arranged adjacently, and the two groups are connected in series. The circuits are respectively configured with odd-numbered clock signal lines and even-numbered clock signal lines.

According to the above-mentioned grouping methods with different numbers of groups, the number of control signal transmission lines in each group of series circuits is different, and the number of clock signal lines corresponding to each group of series circuits is also different. However, different grouping methods can reduce the configuration space of peripheral circuits and meet the requirement of reducing the width of peripheral circuits. Therefore, the grouping method can be determined according to the requirement of the display device’s frame width, so as to meet the display device specifications or cooperate with the display device. Design to institutional specifications.

The above descriptions are illustrative only, not restrictive. Any equivalent modification or change made without departing from the spirit and scope of the present invention shall be included in the scope of the appended patent application.

10, 41, 51: Gate drive circuit 20: Pixel Matrix 21: Pixel 30, 30A: shift register 31, 42, 52: wiring area 32: The first circuit area 32a: Pull-down circuit 33, 33a: transfer line area 34: The second circuit area 34a: Pull-up circuit 40, 50: Peripheral circuit area 100: display panel AA: display area C: Capacitance COF1~COF8: chip-on-chip thin film area D: data signal G: Gate drive signal G1~G2160: the first level shift register~the 2160th level shift register GOA1~GOA8: 1st series connection circuit~8th series connection circuit HC1~HC16: 1st clock signal~16th clock signal LC/VSS: other wiring area NA: peripheral circuit area Q(n): node ST(n-8): The first 8 pull-up control signals ST(n+8): The last 8 pull-down control signals T11~T64: Transistor W: width

In order to make the technical features, content and advantages of the present invention and the effects that can be achieved more obvious, the present invention will be described in conjunction with the following drawings: FIG. 1 is a schematic diagram of a group of gate drive circuits according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a gate drive circuit according to an embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a gate drive circuit according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the peripheral circuit area of the embodiment of the present invention. FIG. 5 is a schematic diagram of another group of peripheral circuit areas according to an embodiment of the present invention.

10: Gate drive circuit

20: Pixel matrix

21: Pixel

100: display panel

AA: display area

COF1~COF8: chip-on-chip thin film area

D: data signal

G: Gate drive signal

G1~G2160: the first level shift register~the 2160th level shift register

GOA1~GOA8: 1st series connection circuit~8th series connection circuit

NA: peripheral circuit area

W: width

Claims (10)

A gate drive circuit is arranged on the same side of a display area as a source drive circuit, and is used to drive a plurality of pixels in the display area. The gate drive circuit includes: A plurality of shift registers, the plurality of shift registers receive the n-phase clock signal, the a-stage shift register is controlled by the pull-up signal of the current stage, and the b-stage shift register is pulled down by the pull-down signal of the current stage register, a, b, n are positive integers; Wherein, the plurality of shift registers are configured as m groups of serial circuits, m is a positive integer between 2 and a and m is a factor of a, and the plurality of shift registers have the same pull-up signal The shift registers of the transfer path are adjacently arranged in the same group of the serial circuits. The gate drive circuit according to claim 1, wherein among the plurality of shift registers, shift registers having the same pull-down signal transmission path are adjacently arranged in the same group of the serial circuit. The gate drive circuit according to claim 1, wherein the plurality of shift registers respectively include a wiring area, a first circuit area, a transfer line area and a second circuit area. The gate drive circuit as described in Claim 3, wherein a plurality of clock signal lines are arranged in the wiring area, and the number of the plurality of clock signal lines is n/m. The gate drive circuit as described in claim 3, wherein the transmission line area includes signal transmission lines for transmitting pull-up signals and pull-down signals. The gate drive circuit according to claim 3, wherein the first circuit area includes a pull-down circuit, and the second circuit area includes a pull-up circuit. The gate drive circuit as described in claim 1, wherein the plurality of shift registers receive sixteen-phase clock signals, the pull-up signal of this level controls the eight-stage shift register, and the pull-down signal of this level Pull down the first eight shift registers. The gate drive circuit according to claim 7, wherein the series circuits are divided into two groups, four groups or eight groups. A display panel including a gate drive circuit, which includes a display area and a peripheral circuit area, the peripheral circuit area is set on one side of the display area, and the peripheral circuit area includes any one of the request items 1 to 8 In the gate driving circuit, the gate driving circuit is respectively connected to a plurality of pixels in the display area, and transmits a gate driving signal to drive the plurality of pixels. The display panel including the gate driving circuit as described in claim 9, wherein the peripheral circuit area includes a source driving circuit, and the source driving circuit is respectively connected to the plurality of pixels in the display area to transmit a data signal to the plurality of pixels.

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