TW202248466A - Spatially and dimensionally non-uniform channelled plate for tailored hydrodynamics during electroplating - Google Patents

Abstract

An ionically resistive ionically permeable element for use in an electroplating apparatus includes ribs to tailor hydrodynamic environment proximate a substrate during electroplating. In one implementation, the ionically resistive ionically permeable element includes a channeled portion that is at least coextensive with a plating face of the substrate, and a plurality of ribs extending from the substrate-facing surface of the channeled portion towards the substrate. Ribs include a first plurality of ribs of full maximum height and a second plurality of ribs of smaller maximum height than the full maximum height. In one implementation the ribs of smaller maximum height are disposed such that the maximum height of the ribs gradually increases in a direction from one edge of the element to the center of the element.

Description

Spatially and dimensionally inhomogeneous channel plates for specific hydrodynamics during electroplating

Embodiments of the invention relate to methods and apparatus for controlling the fluid dynamics of an electrolyte during electroplating. More specifically, the methods and apparatus described herein are particularly useful for electroplating metal onto semiconductor wafer substrates, especially substrates having a plurality of recessed features.

In semiconductor device fabrication, deposition and etching techniques are used to form patterns of material such as metal lines embedded in dielectric layers. Electrochemical deposition processing is an established technique in modern integrated circuit fabrication. The switch from aluminum to copper wire interconnects in the early years of the 21st century drove the need for more sophisticated electrodeposition processing and plating equipment. Many sophisticated technologies have been developed in response to the increasingly smaller current-carrying wires in the metal layers of devices. These copper lines are formed by electroplating metal into very thin, high aspect ratio trenches and vias in a so-called "damascene" process technique (pre-passivation metallization).

Electrochemical deposition systems are now being used to meet the commercial needs of complex packaging and multi-die interconnect technologies, commonly colloquially referred to as wafer-level packaging (WLP) and through-silicon via (TSV) electrical connection technologies. These technologies present their own formidable challenges due in part to generally larger feature sizes (compared to front-end-of-line (FEOL) interconnects) and high aspect ratios.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. The achievements of the inventors listed in the background paragraph of this application and the descriptions that cannot be regarded as prior art at the time of application are not the prior art that the present invention expressly or implicitly recognizes.

In one aspect, an electroplating apparatus. In certain embodiments, the electroplating apparatus includes: (a) an electroplating chamber for containing the electrolyte and an anode when metal is electroplated onto a substrate; (b) a substrate support for supporting the substrate during electroplating so that a plated side of the substrate is separated from the anode; and an ion-resistive element comprising: (i) a channel plate adapted to provide a channel through the ion-resistive element during electroplating; (ii) a substrate side parallel to and separated from the plated surface of the substrate by a gap; (iii) a plurality of ridges located on the plated surface of the ion-resistive element On the surface substrate side, wherein the plurality of ridges includes a first plurality of ridges having a full maximum height and a second plurality of ridges whose maximum height is less than the full maximum height. The electroplating apparatus further comprises: an inlet of the gap for introducing a cross-flow electrolyte into the gap; and an outlet of the gap for receiving the cross-flow electrolyte flowing in the gap, wherein during electroplating the inlet and the outlet is adjacent to the azimuth-relative perimeter position of the electroplating surface of the substrate.

In certain embodiments, the ion-resistive element is positioned such that the second plurality of ridges having a smaller maximum height is adjacent to the entrance of the gap. In some embodiments, all of the ridges are parallel to each other and perpendicular to a direction in which the cross-flow electrolyte flows in the gap. In certain embodiments, the second plurality of ridges comprises at least two ridges having different maximum heights. In some embodiments, the ridges of the second plurality of ridges are arranged such that the maximum ridge height increases along a direction from an edge of the ion-resistive plate to a center, wherein the ridges with smaller heights The second plurality of ridges is disposed on only one side of the ion-resistive element.

In certain embodiments, the total number of ridges is between about 15 and about 30, the second plurality of ridges having the smaller maximum height has between about 2 and about 10 ridges. In certain embodiments, the full maximum height of the ridge is less than about 5 mm. For example, in some embodiments, the full maximum height of the ridge is about 1-3 mm. In certain embodiments, the gap between a bottom of the substrate support and the ion-resistive element is less than about 20 mm.

In some embodiments, at least a portion of the plurality of ridges has a variable height. In some embodiments, at least a portion of the plurality of ridges has a variable height and the ridge height of a ridge with the variable height decreases gradually in a direction toward an edge of the ridge.

In some embodiments, the ion-resistive element includes a region in which the ridge height is less than the full maximum height and the region is substantially crescent-shaped. In some embodiments, the region is located adjacent to the entrance or the exit of the gap.

In some embodiments, the ion-resistive element includes a region in which the ridge height is less than the full maximum height and the region is substantially annular. In some embodiments, the ion-resistive element includes a region in which the ridge height is less than the full maximum height and the region has the shape of a martini cup.

In some embodiments, the ion-resistive element includes a plurality of disconnected channels. In other embodiments, the ion-resistive element includes a three-dimensional network of communicating channels.

In some embodiments, the electroplating apparatus further includes a cross-flow injection manifold fluidly coupled to the inlet. In some embodiments, the cross-flow injection manifold is at least partially defined by a cavity in the ion-resistive element. In some embodiments, the electroplating apparatus further includes a flow restriction ring positioned over a peripheral portion of the ion-resistive element. In certain embodiments, the inlet spans an arc of between about 90-180° adjacent to the perimeter of the plated face of the substrate.

In another aspect, there is provided a use of an ion resistive plate in an electroplating apparatus, wherein the resistive plate is suitable for plating materials on standard diameter semiconductor wafers, in some embodiments, the resistive plate comprises : a circular portion having a plurality of channels coextensive with a plated surface of the semiconductor wafer, wherein the resistive plate has a thickness between about 2-25 mm; and a plurality of ridges extending from the circular portion Extending, wherein the plurality of ridges includes a first plurality of ridges having a full maximum height and a second plurality of ridges having a maximum height less than the full maximum height.

In another aspect, a substrate electroplating method is provided. In some embodiments, the method includes: (a) receiving a substrate in a substrate support, wherein a plating side of the substrate is exposed, wherein the substrate support is used to support the substrate during electroplating for separating the plated side of the substrate from an anode; (b) immersing the substrate in an electrolyte, wherein a gap is formed between the plated side of the substrate and an ion resistive element plane, wherein the ion The resistive element is at least about coextensive with the plating surface of the substrate, wherein the ion resistive element comprises a channel plate adapted to provide ion transport through the ion resistive element during electroplating, wherein the ion resistive element comprises a A plurality of ridges on the substrate side of one surface of the ion-resistive element, wherein the plurality of ridges includes a first plurality of ridges with a full maximum height and a second plurality of ridges with a maximum height less than the full maximum height; (c) making the electrolytic Liquid flows into the gap from a side inlet and flows out from a side outlet to contact the electrolyte with the substrate in the substrate support, wherein the side inlet and the side outlet are designed or used to pass through the gap during electroplating. generating a lateral flow of electrolyte in (c); (d) rotating the substrate support; and (e) electroplating material onto the plated side of the substrate while flowing the electrolyte in (c).

In some embodiments, the electroplated material includes tin and silver. In some embodiments, the electroplated material includes copper.

In certain embodiments, the electrodeposition methods provided herein are used with photolithographic patterning, and the methods provided further comprise the steps of: applying a photoresist to the semiconductor substrate; exposing the photoresist to light; patterning the photoresist and transferring the pattern to the semiconductor substrate; and selectively removing the photoresist from the semiconductor substrate.

In another aspect, a non-transitory computer machine-readable medium is provided, wherein the non-transitory computer machine-readable medium includes program instructions for controlling an apparatus for substrate processing, wherein the program instructions include instructions for controlling a substrate according to The method presented herein achieves a code for electrodeposition of materials.

These and other aspects of the implementation object described in this specification are set forth in the drawings and the following description.

Methods and apparatus for electrodepositing metals onto semiconductor wafers with better control over electrolyte fluid dynamics are provided. Electrodeposition uniformity can be improved due to better control of electrolyte fluid dynamics. The method is particularly useful for electroplating metal onto semiconductor wafers having a plurality of recessed features. For example, recessed features can be filled using the provided methods, such as in a WLP process. The method uses an ion-resistance ion-permeable element comprising an ion-permeable plate having channels and a plurality of ridges extending from a face substrate surface of the plate toward the substrate, wherein the plurality of ridges have different maximum heights or, the individual ridges have variable height (eg, tapered ridges), or both. In certain embodiments, electrolyte is injected into the gap between the ion-resistive element and the surface of the substrate, creating electrolyte lateral flow (lateral electrolyte flow parallel to the surface of the substrate). In some embodiments, the ridge (referring to the "length" dimension of the ridge) is substantially perpendicular to the direction of electrolyte cross flow. In one embodiment, ridges adjacent to the entrance of the gap (eg, within 50 mm of the entrance) have a smaller maximum height than ridges farther from the entrance. For example, the ion resistive element may comprise a first ridge (or first plurality of ridges) and a second ridge (or second plurality of ridges), wherein the ion resistive element is positioned such that the first ridge (or first plurality of ridges) A plurality of ridges) is closer to the entrance of the gap than a second ridge (or second plurality of ridges), wherein the first ridge (or first plurality of ridges) is closer to the entrance of the gap than the second ridge (or second plurality of ridges) Has a smaller maximum height. In some embodiments, the maximum ridge height gradually increases along a direction from the edge of the element towards the center of the element.

In certain embodiments, the ion-resistive element has ridges of various sizes distributed in a spatially non-uniform pattern. It can generate customized convection at the substrate surface to improve plating performance. By customizing the ridge height, taper, and distributing the ridges at certain locations across the ion-resistive element, the fluid dynamics at the wafer surface can be modulated to improve plating performance.

The word "metal" used herein refers to one or more metals, and "electrodeposited metal" is not limited to electrodeposited single metal. For example, "metal" may be a combination of tin and silver. In certain embodiments, the method is for electrodepositing copper (Cu). In some embodiments, the method is used to electrodeposit nickel (Ni), tin (Sn), or tin-silver alloy (SnAg).

In this specification, the term "semiconductor wafer" may refer to a substrate at any stage of semiconductor device fabrication that contains semiconductor material throughout its structure. The following detailed description assumes that embodiments of the invention are implemented on a wafer. It should be appreciated that the semiconductor material in the semiconductor wafer need not be exposed. A semiconductor wafer having a plurality of layers of other materials (such as dielectric materials) covering the semiconductor material is an example of a semiconductor substrate. The following detailed description assumes that the disclosed embodiments are implemented on a semiconductor wafer, such as a 200 mm, 300 mm, or 450 mm semiconductor wafer. However, the disclosed embodiments are not limited thereto. Workpieces can be of various shapes, various sizes, and various materials. In addition to semiconductor wafers, other workpieces that may benefit from the disclosed embodiments include various items such as printed circuit boards and the like.

Unless otherwise indicated, the word "about" used in conjunction with a numerical value includes a range of ±10% of the stated numerical value.

The term "ridge" refers to a protrusion on the face substrate side of an ion-resistance ion-permeable element. In many embodiments, the ridges have a length to height ratio greater than at least 3:1. The ridge length is typically coextensive with at least the portion of the ion-resistance ion-permeable element having the channel. In certain embodiments the ion-resistance ion-permeable element is fabricated from a single piece of a non-conductive material such as polycarbonate. In other embodiments, the ridge can be removable and can be inserted into a notch on the portion of the ion-resistive element having the channel.

The terms "ion-resistive element", "ion-resistance ion-permeable element", "ion-resistive plate with channels" are used interchangeably herein and mean a material made of non-conductive material having a plurality of channels to allow the passage of electrolyte components. In some embodiments, the element introduces resistance to ion flow between the anode and the wafer substrate that is cathodically biased.

The term "maximum height" refers to the maximum height of the spine. For example, a ridge that tapers at the edge will have a maximum height outside the tapered region. If the spine has a fixed height, then its maximum height will be equal to its fixed height. "Full maximum height" of a ridge means the largest maximum height of a plurality of ridges, for example a plurality of ridges having a maximum height of 5 mm each and a plurality of ridges having a maximum height of 3 mm spine, the "full maximum height" will be 5 mm.

The provided method controls the electrolyte fluid dynamics adjacent to the substrate using an ion-resistive plate (CIRP) with channels, also known as an ion-resistance ion-permeable element. The CIRP provides small channels (lateral flow manifolds) between the plated surface of the wafer substrate and the top of the CIRP. The CIRP can have a number of functions, including at least one of: 1) enabling a flow of ions from the anode located substantially below the CIRP to the wafer; 2) enabling fluid flow up through the CIRP and generally toward the wafer surface; 3 ) restrict electrolyte flow away from and out of the cross-flow manifold area. In certain embodiments, the electrolyte flow in the region of the cross-flow manifold includes flow up through holes in the CIRP and into one side of the wafer from a cross-flow injection manifold typically located on the CIRP to create a cross-flow of electrolyte. fluid. In certain embodiments, the apparatus is used to operate under certain conditions to produce a velocity of about 3 cm/sec or greater (e.g., about 5 cm/s or greater, about 10 cm/sec) across the center point of the plated face of the substrate. cm/s or greater, about 15 cm/s or greater, or about 20 cm/s or greater) average electrolyte lateral velocity.

When using a CIRP with uniform ridge elements (thin protrusions of the same height), a uniform flow disturbance across the CIRP should be provided. However, in some cases inlet or outlet effects can interact with the ridge elements, creating regions of highly turbulent flow, resulting in non-uniform plating performance. According to certain embodiments provided herein, spatially distributed ridges can counteract and minimize inlet/outlet turbulence and produce more uniformly plated substrates.

In one aspect, an electroplating apparatus is provided, wherein the electroplating apparatus comprises: (a) an electroplating chamber for containing an electrolyte and an anode when electroplating metal onto a substrate; (b) a substrate support , for supporting the substrate during electroplating so that one plated side of the substrate is separated from the anode; and an ion-resistance ion-permeable element positioned so that there is a gap between the working surface of the substrate and the face substrate surface of the element. The ion resistive element comprises: a channel plate adapted to provide ion transport through the ion resistive element during electroplating; a substrate side parallel to the electroplated side of the substrate and with a gap to the electroplated side of the substrate plane separation; a plurality of ridges located on the plane substrate side of the ion resistive element, wherein the plurality of ridges includes a first plurality of ridges having a full maximum height and a second plurality of ridges whose maximum height is less than the full maximum height. In some embodiments, the apparatus further comprises: an inlet of the gap for introducing a cross-flow electrolyte into the gap; and an outlet of the gap for receiving the cross-flow electrolyte flowing in the gap, Wherein during electroplating, the inlet and outlet are azimuthally opposite perimeter positions adjacent to the electroplating surface of the substrate.

Using non-uniform ridges on the ion-impedance ion-permeable element, the hydrodynamic environment at the substrate is customized by adjusting the electrolyte convection in the gap (also known as a cross-flow manifold or CIRP chamber).

An example of an electroplating apparatus 100 having a CIRP 101 having ridges of different maximum heights as described above is shown in FIG. 1 and a schematic cross-sectional view of the apparatus 100 is shown. The electroplating apparatus 100 comprises a plating chamber 102 filled with an electrolyte solution (comprising ions of the metal to be plated and optionally acids and plating additives) containing an anode 103 at the bottom. Anode 103 may be an active or inert anode, which is electrically connected to a power source and intended to be positively biased. In the illustrated embodiment, the wafer substrate 105 is supported in a face-down orientation by the substrate support 107 for being negatively biased and immersed in the electrolyte during electroplating. In the illustrated embodiment, the apparatus further includes a membrane frame 109 and a membrane mounted on the membrane frame 109 between the anode 103 and the wafer substrate 105 which is cathodically biased. The membrane can be an ion selective membrane, which can be used to maintain a different composition in the anode compartment 111 below the membrane and the cathode compartment 113 above the membrane. For example, during simultaneous tin-silver plating with an active tin anode, membranes can be used to inhibit or avoid transport of silver ions from the catholyte to the anolyte compartment. In the illustrated embodiment, the CIRP 101 is seated in a cathode chamber 113 and includes a channel plate 114 and a plurality of ridges 115 (in this embodiment the ridges themselves have no channels), the channels in the channel plate 114 (not shown) shown) to allow electrolyte to flow through the CIRP 101, the plurality of ridges 115 includes a first plurality of ridges with a full maximum height (shown schematically as the 7 ridges on the right) and a second plurality of ridges with a smaller maximum height (shown schematically Shown as the 4 lower ridges on the left). Electrolyte is injected into the inlet 117 as indicated by the arrow, enters the cross-flow manifold (CIRP chamber) 119 and flows to the CIRP chamber without experiencing undesired turbulence after encountering the ridge 115 of increasing height The outlet 121 of 119, the outlet 121 is the perimeter position (relative to the inlet) relative to the azimuth angle of the plating surface adjacent to the substrate.

The flow path for conveying the cross-flow electrolyte begins as it passes in a vertically upward direction through the cross-flow feed channels in the plate. This flow path then enters a cross-flow injection manifold formed within the body of the ion-resistive plate with channels. The cross-flow injection manifold is an azimuth cavity that is a bored channel in the plate that distributes fluid from various independent feed channels, such as from each of the six cross-flow feed channels, to the various points of the cross-flow showerhead plate. Plural flow disperse holes. This cross-flow injection manifold can be arranged along the corner sections of the perimeter or edge regions of the ion-resistive plate 101 with channels. In certain embodiments, the cross-flow injection manifold forms a C-shaped structure spanning an angle of about 90-180° of the perimeter region of the plate. Details of the cross-flow injection manifold are not shown in Figure 1 to maintain clarity.

It should be appreciated that in Fig. 1 a device overview is shown, ie a larger number of spines could be used in a real CIRP.

In certain embodiments, the full maximum height of the ridges is less than about 5 mm, such as between about 1-3 mm. In certain embodiments, the total number of ridges is between about 15-30, and the number of ridges with a smaller maximum height less than the full maximum height is between about 2-10.

It should be noted that in the embodiment shown, the use of a lower ridge height adjacent to the electrolyte inlet 117 reduces turbulence substantially compared to CIRP where all ridges have the same maximum height. Therefore, the reduction of turbulence can lead to better plating uniformity. Also, the use of CIRP as shown in FIG. 1 in the embodiments of simultaneous tin and silver electroplating can result in a more uniform silver content in the tin-silver layer across the entire wafer surface.

In each case, CIRP is a solid, non-porous disk of dielectric material with ionic and electrical impedance properties. The material is also chemically stable for use in electroplating solutions. In some cases, CIRP is a ceramic (such as aluminum oxide, tin oxide, titanium oxide, or a mixture of metal oxides) or a plastic material (such as polyethylene, polyvinylidene fluoride (PVDF), polytetrafluoroethylene, poly made of polyvinyl chloride (PVC), polycarbonate, etc.), have between about 6,000-12,000 unconnected through-holes. In many implementations, the portion of the plate with the channel is at least substantially coextensive with the plated surface of the wafer (e.g., a CIRP plate has a diameter of about 300 mm when used with a 300 mm wafer) and is immediately adjacent to the wafer such as Located directly below the wafer in the under-wafer plating equipment. The plated surface of the wafer preferably sits within about 20 mm, more preferably within about 5 mm of the closest CIRP surface.

Another characteristic of CIRP is the diameter or major dimension of the via and its relationship to the distance between the CIRP and the substrate. In some embodiments, the diameter of each via (or the diameter of a majority of the vias, or the average diameter of the vias is no greater than about the distance between the plating surface of the wafer and the closest surface of the CIRP. Therefore, In such embodiments, when the CIRP is placed within about 5 mm of the plating surface of the wafer, the diameter or major dimension of the vias should not exceed about 5 mm.

As above, the overall ionic and flow resistance of the plate is dependent on the plate thickness and the total porosity (the component of the area that enables fluid to flow through the plate) and the size/diameter of the holes. Plates with lower porosity will have higher impingement flow rates and ionic impedance. Compared to plates with the same porosity, a plate with smaller diameter 1-D holes (and thus a greater number of 1-D holes) will have a more uniform flow distribution across the wafer because there are more individual liquid A flow source can have the function of a point source, which can be dispersed over the same phase gap and also have a higher total pressure drop (high viscosity flow resistance).

In some cases, however, the ion-resistive plate is porous as described above. The pores in the plate may not form independent 1-D channels, but may form a grid of through-holes that may or may not be interconnected. For example, a board may contain a three-dimensional network of interconnected channels. It should be understood that the terms ion-resistive plate with channels (CIRP) and ion-resistive element with channels as used herein are intended to encompass this embodiment unless the context indicates otherwise. conical ridge

In certain embodiments, the individual ridges of the CIRP have variable heights, eg, are tapered at the edges. Such a taper can improve the hydrodynamics of the electrolyte at the substrate adjacent the edge of the ridge and can also result in more uniform plating. Ridge height variation of individual ridges can be used alone or in combination with ridges having different maximum heights as described above. 2 and 3A-3D show several illustrations of a CIRP 200 including ridges with different maximum heights and ridges with tapered edges that can be used as shown in the apparatus of FIG. 1 . Figure 2 illustrates a CIRP 200 with 27 parallel ridges, where the maximum height of the ridges at one side of the CIRP is smaller than the maximum height of the remaining ridges. Also, in addition, a portion of the ridge is tapered at the edge (the height of the ridge at the edge is less than the height of the ridge at the center). The tapered ridge can be a ridge with a full maximum height, a ridge with a smaller maximum height, or both. For example, the full maximum height may be about 3 mm and such ridges may or may not be tapered at the edges. For example, referring to FIG. 2, a CIRP 200 includes a non-tapered ridge 201 having a full maximum height at one side of the CIRP 200, a tapered ridge 203 having a smaller maximum height at an opposite side of the CIRP 200, and a tapered ridge 205 having a full maximum height. Figure 3A shows a top view of a portion of the CIRP 200 shown in Figure 2 showing a crescent-shaped region 310 where the ridge height is less than the full maximum height. Regions are formed by a combination of tapers at the edges, where the height of individual ridges decreases towards the edge, and ridges whose maximum height is less than the full maximum height. In the portion of the CIRP 200 outside crescent region 310 , referred to as region 320 , the ridges have full height. Figure 3B shows an isometric view of a portion of such a CIRP 200 showing more clearly the tapering of the ridges at the edges. Figure 3C shows a cross-section of a portion of the same CIRP 200, more clearly showing the gradual increase in maximum height of successive ridges. Figure 3D shows a different cross-section of a portion of the same CIRP 200 showing tapering of the ridges at the edges.

Using the CIRP shown in FIGS. 2 and 3A-3D (also referred to as Example 1) for tin-silver plating in the apparatus shown in FIG. Height without cone) compared to CIRP results. Figure 4 is an experimental diagram 400 showing the silver content (in %) in the electroplated tin-silver layer as the radial profile (in mm) of the uniform ridge CIRP (black diamond) and the CIRP (white diamond) of Example 1 unit) function. As can be seen, using CIRP with uniform ridges results in layers near the edge of the wafer having more silver content than layers in the center of the wafer. When using the CIRP of Example 1, the variation in silver content as a function of radial position is advantageously reduced and the silver content remains substantially constant at all radial positions. 5 is an experimental graph 500 showing the thickness (bump height) of the electroplated tin-silver layer as a function of the radial position (in mm) of the uniform ridge CIRP (black diamond) and the CIRP (white diamond) of Example 1 function. As can be seen from the figure, the use of uniform ridge CIRP results in a drastic reduction in film thickness at the edge of the wafer compared to the film thickness at the center of the wafer. When using the CIRP of Example 1, thickness uniformity is advantageously restored and the tin-silver bump thickness remains substantially constant at all radial positions. It is generally believed that the improvement in both the silver content variation and the uniformity of the deposited layer is due to the less turbulent flow achieved with the CIRP of Example 1. When tin-silver is electroplated, in this embodiment the amount of silver provided in the electrolyte is less than the amount of tin, and the concentration of silver in the deposited film is limited by convection. When the turbulent flow at the edge increases (uniform ridge CIRP encountered, electrolyte flow interruption due to encountering full-height first ridge at electrolyte inlet), larger amounts of silver can be included at the edge of the wafer in the tin-silver thin film. This problem is solved by providing a CIRP of successive ridges of increasing height at the electrolyte inlet and by the CIRP of Example 1 providing tapering of the ridges at the edges. For increased plating at the edge using uniform ridge CIRP, the increased turbulence in this case would result in increased functionality of the plating leveler added to the tin-silver plating bath. Similarly, use of the CIRP of Example 1 reduces turbulence at the electrolyte inlet and edges, resulting in a substantially uniform plating profile.

6A, 6B, and 6C provide different views of CIRP 600 according to Embodiment 2. FIG. Example 2 is similar to Example 1, but differs from Example 1 in that the crescent-shaped region 610 comprising regions with ridge heights less than the full maximum height (including shorter ridges and tapered ridge portions) is smaller than that of Example 1. The CIRP 200 of Example 1 has a larger area. Specifically, it can be seen from FIG. 6A that the area of this region is about 50% of the total area of the portion of the CIRP with channels. What remains is an area 620 with a full height ridge. In certain embodiments, the area of this region is between about 40-60% of the total throughput of the CIRP's face substrate surface with channels.

CIRPs with non-uniform ridges can be used to improve the fluid dynamics of the electrolyte and improve plating uniformity in various other embodiments. It is especially useful when CIRPs with non-uniform ridges are used in electroplating equipment with cross-flow of electrolyte between the inlet and outlet in the cross-flow manifold. A number of CIRP embodiments are illustrated in Figure 7, which schematically illustrates a top view of a CIRP, where the gray areas represent areas where the ridge height is less than the full maximum height (tapered regions and/or ridges whose maximum height is less than the full maximum height). Areas of full maximum height are shown as white areas. Arrows show the direction of electrolyte flow over the CIRP. In Example 3, the area of smaller ridge height has a crescent shape as shown in Example 1, but the CIRP in Example 3 is positioned such that this crescent-shaped area is located adjacent to the outlet of the cross flow manifold. non-entry. This can be used to reduce any non-uniformity due to turbulence at the outlet. In Example 4, the regions of smaller ridge height are located on the right and left edges of the CIRP (relative to the direction of electrolyte flow). For example in this embodiment, substantially all of the ridges may be tapered at the edges. In Example 5, the area of smaller ridge height has a ring shape (also known as the bull's eye example). In Example 6, the region of smaller ridge height has a horseshoe shape and is located adjacent to the inlet of the cross-flow manifold. In Example 7, the area of smaller ridge height has the shape of a martini cup and the larger area is closer to the inlet of the crossflow manifold.

In another aspect, a method of electroplating metal on a substrate is provided, wherein the method includes: (a) receiving a substrate in a substrate support, wherein a plated side of the substrate is exposed, wherein the substrate supports A member is used to support the substrate during electroplating so that the plated side of the substrate is separated from an anode; (b) immersing the substrate in an electrolyte, wherein a gap is formed between the plated side of the substrate and an anode between the planes of the ion-resistive element, wherein the ion-resistive element is at least about coextensive with the plated side of the substrate, wherein the ion-resistive element comprises an ion-resistive element adapted to provide ion transport through the ion-resistive element during electroplating A channel plate, wherein the ion resistive element comprises a plurality of ridges on one substrate side of the ion resistive element, wherein the plurality of ridges comprises a first plurality of ridges having a full maximum height and a plurality of ridges with a maximum height less than the full maximum height Second plural ridges. The method further includes: (c) causing electrolyte (i) to flow into the gap from a side inlet and out from a side outlet so that the electrolyte contacts the substrate in the substrate support, wherein the side inlet and the The side outlet is designed or used to create a lateral flow electrolyte in the gap during electroplating; (d) rotate the substrate support; and (e) plate material onto the substrate while the electrolyte is flowing in (c) the plated surface.

In another aspect, there is provided a method for electroplating materials onto semiconductor wafers with standard diameters using an ion-resistive plate in an electroplating device, the ion-resistive plate includes: a circular portion having a shape corresponding to the semiconductor wafer A plurality of channels coextensive on the plating surface, wherein the resistive plate has a thickness between about 2-25 mm; and a plurality of ridges extending from the circular portion, wherein the plurality of ridges include A first plurality of ridges and a second plurality of ridges having a maximum height less than the full maximum height. In certain embodiments, the full maximum ridge height is about 5 mm or less, such as about about 3 mm or less. system

The deposition methods described herein can be performed in various configurations of electroplating equipment including the provided CIRP.

A suitable metal deposition apparatus includes a plating chamber for supporting the electrolyte and an anode, and a substrate support having contacts for cathodically biasing the substrate. The apparatus can be used to rotate the substrate during electroplating. Deposition can be performed in a face-up or face-down orientation. Some electroplating equipment can also run vertically. An example of a suitable device is the SABER 3D device sold by Colin Research & Development, Fremont, CA. In certain embodiments, the electroplating apparatus comprises a plurality of electroplating cells (for electroplating the same or different metals) and a robotic device, wherein at least one of the electroplating cells comprises a CIRP with non-uniform ridges as described herein, and the robotic device is used to Transfer substrates between separate plating cells. In some embodiments, the apparatus further includes a controller including a plurality of programmed instructions for performing any of the methods described herein.

An integrated apparatus for electrodepositing metals is shown in FIG. 8 . In this embodiment, the apparatus 800 has a pair or pluralities of electroplating cells 807 in a dual configuration, each electroplating cell 807 comprising an electrolytic bath containing an electrolyte. In addition to electroplating itself, the apparatus 800 can perform various other electroplating or electroplanarization related processes and sub-steps such as spin rinse, spin dry, wet etching of metal and silicon, electroless deposition, prewetting and prechemical treatment, reduction, annealing , photoresist stripping, and surface pre-activation. While a top view of device 800 is schematically shown in FIG. 8, only a single level or "floor" is shown in the figure, but those of ordinary skill in the art will appreciate that such devices, such as the Saber ^™ 3D device developed by Colin, may have mutual Two or more levels that are "stacked" one above the other, with each level potentially having the same or different types of processing stations. In some embodiments, plating stations for different metals are located on different levels of the facility. In other embodiments, a single level may include plating stations for plating both the first and second metals.

Referring again to FIG. 8 , substrates 806 to be plated are generally fed into apparatus 800 via a front-end loading FOUP (Front Loading Unified Pod) 801. In the substrate processing area, the front end robot 802 can be driven by the spindle 803 to retract and move the substrate 806 in multiple dimensions from one station to another of the access station - the access station contains two front ends shown in this example Access station 804 and two front-end access stations 808 . Front-end access stations 804 and 808 may include, for example, pre-processing stations and spin rinse-dry (SRD) stations. Lateral movement of the front end robot 802 from side to side is accomplished using robot rails 802a. Each of the base plates 806 may be supported by a transverse/cone assembly (not shown) driven by a mandrel connected to a motor, which may be attached to a mounting bracket 809 . Four pairs of electroplating cells 807 are also shown in this example, for a total of eight electroplating cells 807 . Different metals may be plated using the plating cell 807 . After the first metal has been plated in one of the plating stations 807 , the substrate is transferred to a plating cell for plating a second metal on the same level of the apparatus or on a different level of the apparatus 800 . A system controller (not shown) may be coupled to electrodeposition apparatus 800 to control some or all of the characteristics of electrodeposition apparatus 800 . The system controller can be programmed or otherwise configured to execute instructions according to the processes described above.

The system controller usually includes one or more memory devices and one or more processors, and the processors are used to execute instructions to make the device implement the method according to the present invention. A machine-readable medium containing instructions to control processing operations in accordance with the present invention may be coupled to the system controller.

In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor process equipment that includes a process tool or tools, a process chamber or chambers, a process platform or platforms, and/or specific process components (wafer platforms, gas flow systems Wait). Such systems are integrated with electronic devices used to control the operation of the systems before, during and after semiconductor wafer or substrate processing. These electronic devices are referred to as "controllers" which can control various elements or subcomponents of a system or systems. Depending on the process requirements and/or system type, the controller can be programmed to control any of the processes disclosed herein including delivery of plating baths, temperature settings (e.g., heating and/or cooling), voltage delivery to the cathode, wafer transfer into and off-tool and other transfer equipment and/or load interlocks connected to the system or interfaced with a specific system.

In general, a controller can be defined as an electronic device with various integrated circuits, logic, memory and/or software, which can receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurement, etc. . An integrated circuit may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), one or more microprocessors, or a chip capable of executing A microcontroller with programmed instructions (such as software). Program instructions may be in the form of various independent settings (or program files) communicated with the controller, which define operating parameters for a specific process on or for the semiconductor wafer or for the system. In some embodiments, an operating parameter is one or more parameters that a process engineer performs during fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. Part of a recipe defined by multiple processing steps.

In some embodiments the controller is part of or the controller is coupled to a computer integrated into the system, coupled to the system, connected to the system via a network, or a combination thereof. For example, the controller may reside in the "cloud" or in all or part of the factory's mainframe computer system, which allows users to remotely access wafer processing. The computer can enable remote access to the system to monitor the current progress of a manufacturing operation, view the history of past manufacturing operations, view trends or performance metrics from multiple manufacturing operations, change parameters of an existing process, set process steps to match an existing process, or Start a new process. In some examples, a remote computer (or server) can provide processing recipes to the system via a computer network, which includes a local area network or the Internet. The remote computer may include a user interface that allows a user to enter or program parameters and/or settings and then communicate with the system from the remote computer. In some examples, the controller receives instructions in the form of data specifying parameters for each of the process steps to be performed during one or more operations. It should be appreciated that the parameters are specific to the type of process to be performed and the type of tool the controller is using to interface or control. Thus, as described above, controllers can be distributed eg by comprising one or more discrete controllers interconnected by a network and working toward a common purpose of processing and control as described herein. An example of a decentralized controller for such purposes is one or more integrated circuits on a processing chamber that are connected to one or more integrated circuits located remotely (such as at platform level or as part of a remote computer) Communication to jointly control the processing on the processing chamber.

Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, edge etch chambers or modules group, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, atomic layer deposition (ALD) chamber or module, atomic layer etching (ALE) chamber or module, ion implantation Entry chambers or modules, orbital chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication of semiconductor wafers.

As mentioned above, depending on the processing step or steps to be performed by the tool, the controller may communicate with one or more of the following: circuits or modules of other tools, components of other tools, cluster tools, interfaces of other tools , an adjacent tool, an adjacent tool, a tool located in a fab, a host computer, another controller, or a material transport tool for loading and unloading wafer containers into and out of a tool location and/or loading interface in a semiconductor fabrication facility . Patterning method / equipment

The various devices/processes described above may be used with lithographic patterning devices or processes, such as those used to manufacture semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such equipment/processes will be used or performed together in a common manufacturing plant. Photolithographic patterning of thin films typically involves some or all of the following steps, each of which can be accomplished by a number of possible devices: (1) applying photoresist to a workpiece using spin-coating or spray-coating equipment; (2) applying thermal (3) using a device such as a wafer stepper to expose the photoresist to visible light or UV or EUV or X-rays; (4) using a tool such as a wet bath developing the photoresist to selectively remove and thereby pattern the photoresist; (5) using a dry or plasma-assisted etch tool to transfer the photoresist pattern into the underlying film or workpiece; and (6) using A tool such as RF or microwave plasma photoresist stripping equipment removes the photoresist.

100: Electroplating equipment 101, 200, 600: Ion-resistive plate/CIRP with channels 102: Electroplating room 103: anode 105: Wafer substrate 107: substrate support 109: film frame 111: anode chamber 113: cathode chamber 114: Channel plate 115: Ridge 117: Entrance 119: CIRP Room 121: export 201: no tapered ridge 203: tapered ridge 205: tapered ridge 310, 610: Crescent area 620, 320: area 400:Experimental graph 500:Experimental graph 800: Equipment 802: Front-end robot 802a: Robot track 801:Front loading unit/FOUP 804: front access station 806: Substrate 808: front access station 807: Electroplating pool 809: Mounting bracket

FIG. 1 is a schematic cross-sectional view of an electroplating apparatus with an ion-resistive element according to one embodiment provided herein.

FIG. 2 is a view of an ion-resistive element according to one embodiment provided herein.

FIG. 3A is a top view of a portion of the ion-resistive element shown in FIG. 2. FIG.

FIG. 3B is another view of a portion of the ion-resistive element shown in FIG. 2. FIG.

FIG. 3C is a cross-sectional view of a portion of the ion-resistive element shown in FIG. 2. FIG.

FIG. 3D is a different cross-sectional view of a portion of the ion-resistive element shown in FIG. 2. FIG.

Figure 4 is an experimental graph illustrating the silver content (in %) in the electrodeposited tin-silver layer as a uniform ridge CIRP (upper curve) and the radial profile (in mm) of the CIRP of Example 1 function.

Figure 5 is an experimental graph illustrating the thickness (bump height) of the electrodeposited tin-silver layer as a function of the radial position (in mm) of the uniform ridge CIRP and the CIRP of Example 1.

FIG. 6A is a top view of a resistive element according to one embodiment provided herein.

6B is a view of a portion of a resistive element according to one embodiment provided herein.

6C is a cross-sectional view of a portion of a resistive element according to one embodiment provided herein.

FIG. 7 illustrates top views of different ion-resistive elements according to embodiments provided herein.

8 is a schematic diagram of an integrated apparatus for electrodepositing metals according to one embodiment provided herein.

100: Electroplating equipment

101: Ion Resistive Plates with Channels/CIRP

102: Electroplating room

103: anode

105: Wafer substrate

107: substrate support

109: film frame

111: anode chamber

113: cathode chamber

114: Channel plate

115: Ridge

117: Entrance

119: CIRP Room

121: export

Claims (27)

A kind of electroplating equipment, comprising: (a) a plating chamber for containing the electrolyte and an anode when metal is plated onto a substrate; (b) a substrate support for supporting the substrate during electroplating so that a plated side of the substrate is separated from the anode; (c) An ion-resistive element comprising: (i) a channel plate adapted to provide ion transport through the ion-resistive element during electroplating; (ii) a substrate side parallel to and separated from the plated side of the substrate by a gap; and (iii) a plurality of ridges located on the surface substrate side of the ion-resistive element, wherein the plurality of ridges includes a first plurality of ridges having a full maximum height and a second plurality of ridges having a maximum height less than the full maximum height spine; (d) an inlet to the gap for introducing cross-flow electrolyte into the gap; and (e) an outlet of the gap for receiving the lateral flow electrolyte flowing in the gap, Wherein the inlet and outlet are positioned at azimuthally opposite perimeter positions adjacent to the plating surface of the substrate during electroplating. The electroplating apparatus of claim 1, wherein the ion-resistive element is positioned such that the second plurality of ridges having a smaller maximum height is adjacent to the entrance of the gap. The electroplating device according to claim 1, wherein all the ridges are parallel to each other and perpendicular to a direction in which the cross-flow electrolyte flows in the gap. The electroplating apparatus according to claim 1, wherein the second plurality of ridges comprises at least two ridges with different maximum heights. The electroplating apparatus as claimed in claim 1, wherein the ridges in the second plurality of ridges are arranged so that the maximum ridge height increases along a direction from an edge of the ion-resistive element to a center, wherein a smaller The second plurality of ridges of height are disposed on only one side of the ion-resistive element. The electroplating apparatus according to any one of claims 1-5, wherein a total number of the ridges is between about 15-30, and the second plurality of ridges having a smaller maximum height has between about 2-30 10 ridges. The electroplating apparatus of any one of claims 1-5, wherein the full maximum height of the ridge is less than about 5 mm. The electroplating apparatus according to any one of claims 1-5, wherein the overall maximum height of the ridge is about 1-3 mm. 5. The electroplating apparatus of any one of claims 1-5, wherein the gap between a bottom of the substrate support and the ion-resistive element is less than about 20 mm. The electroplating apparatus according to any one of claims 1-5, wherein at least a part of the plurality of ridges has a variable height. The electroplating apparatus according to any one of claims 1-5, wherein at least a portion of the plurality of ridges has a variable height and the ridge height gradually decreases along a direction toward an edge of the ridge. The electroplating apparatus of claim 1, wherein the ion-resistive element includes a region in which the ridge height is less than the full maximum height and the region is substantially crescent-shaped. The electroplating device according to claim 12, wherein the region is located adjacent to the entrance or the exit of the gap. The electroplating apparatus of claim 1, wherein the ion-resistive element comprises a region in which the ridge height is less than the full maximum height and the region is substantially annular. The electroplating apparatus of claim 1, wherein the ion-resistive element includes a region in which the ridge height is less than the full maximum height and the region has a shape of a martini cup. The electroplating device as claimed in claim 1, wherein the ion-resistive element includes a plurality of channels without communication. The electroplating device as claimed in claim 1, wherein the ion-resistive element comprises a 3-D network of a plurality of communication channels. The electroplating apparatus of claim 1, further comprising a cross-flow injection manifold fluidly coupled to the inlet. The electroplating apparatus of claim 18, wherein the cross-flow injection manifold is defined at least in part by a cavity in the ion-resistive element. The electroplating apparatus according to claim 1, further comprising a liquid flow restriction ring located above a peripheral portion of the ion-resistive element. The electroplating apparatus of claim 1, wherein the inlet spans an arc of between about 90-180° adjacent to the perimeter of the electroplating surface of the substrate. An ion-resistive plate for electroplating materials onto standard-diameter semiconductor wafers in electroplating equipment, comprising: a circular portion having channels coextensive with a plated side of the semiconductor wafer, wherein the resistive plate has a thickness between about 2-25 mm; and A plurality of ridges extending from the circular portion, wherein the plurality of ridges includes a first plurality of ridges having a full maximum height and a second plurality of ridges having a maximum height less than the full maximum height. A substrate electroplating method, comprising: (a) receiving a substrate in a substrate support, wherein a plated side of the substrate is exposed, wherein the substrate support is used to support the substrate during electroplating so that the plated side of the substrate is in contact with an anode separation; (b) immersing the substrate in an electrolyte solution, wherein a gap is formed between the plated side of the substrate and an ion resistive element plane; wherein the ion-resistive element is at least about coextensive with the plated side of the substrate, wherein the ion resistive element comprises a channel plate adapted to provide ion transport through the ion resistive element during electroplating, and Wherein the ion resistive element comprises a plurality of ridges located on one side of the ion resistive element on the substrate side, wherein the plurality of ridges comprises a first plurality of ridges having a full maximum height and a second plurality of ridges having a maximum height less than the full maximum height plural ridges; (c) bringing electrolyte into contact with the substrate in the substrate support by flowing electrolyte into the gap from a side inlet and flowing out from a side outlet, wherein the side inlet and the side outlet are designed or used to creating a lateral flow of electrolyte in the gap during electroplating; (d) rotating the substrate support; and (e) electroplating a material onto the plated side of the substrate while flowing the electrolyte in (c). The substrate electroplating method according to claim 23, wherein the electroplating materials include tin and silver. The substrate electroplating method according to claim 23, wherein the electroplating material includes copper. Such as the substrate electroplating method of claim 23, further comprising the following steps: applying photoresist to the semiconductor substrate; exposing the photoresist to light; patterning the photoresist and transferring the pattern to the semiconductor substrate; and The photoresist is selectively removed from the semiconductor substrate. A non-transitory computer machine-readable medium comprising a plurality of program instructions for controlling equipment for substrate processing, wherein the plurality of program instructions include program codes for achieving electrodeposition of materials according to the substrate electroplating method of claim 23.

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