TW202238729A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of transistors, an isolation structure, a dielectric layer, a capacitor structure, and an insulation layer. Each transistor includes a gate electrode disposed on the substrate, a gate dielectric layer disposed between the substrate and the gate electrode, and source/drain electrodes disposed in the substrate and located at two opposite sides of the gate electrode. The isolation structure is disposed in the substrate and between the two adjacent transistors. The dielectric layer is disposed on the substrate and covers the transistors. The capacitor structure is disposed in the dielectric layer and electrically connected to the source/drain electrodes adjacent to the isolation structure. The insulation wall is disposed in the dielectric layer and has a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall. The capacitor structure is disposed on the first and second sidewalls of the insulation wall.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a capacitor structure and a manufacturing method thereof.

With the advancement of technology, semiconductor components are also constantly developing towards "light, thin, short, and small" types. However, as the size of semiconductor components becomes smaller and smaller, the effective surface area of capacitors is also smaller and smaller, resulting in a decrease in capacitance. Therefore, how to maintain a large enough capacitance when the size of the semiconductor device is reduced has become one of the problems that the research and development personnel want to solve urgently.

The present invention provides a semiconductor device and a manufacturing method thereof. A capacitor structure is formed on a first side wall of an insulating wall and a second side wall opposite to the first side wall of the insulating wall to increase the effective surface area of the capacitor structure, so that even in the components of the semiconductor device In the case of shrinking size, it can still maintain a large enough capacitance.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps. A dielectric layer covering a plurality of transistors is formed on the substrate, wherein the substrate has an isolation structure between two adjacent transistors, and each transistor includes a gate formed on the substrate, a gate formed on the gate A gate dielectric layer between the substrate and a source/drain formed in the substrate at opposite sides of the gate. A first opening is formed in the dielectric layer to expose the isolation structure and the source/drain adjacent to the isolation structure. An insulating wall is formed on the sidewall of the first opening, wherein the insulating wall has a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall. A second opening is formed in the dielectric layer, wherein the second opening exposes a portion of the first sidewall of the isolation wall. A capacitive structure is formed in the first opening and the second opening, wherein the capacitive structure is formed on a part of the first sidewall of the insulating wall and the second sidewall of the insulating wall and is electrically connected to the source/drain of the adjacent isolation structure.

In an embodiment of the invention, the method for forming the second opening includes the following steps. A mask pattern is formed on the dielectric layer, wherein the mask pattern exposes a part of the dielectric layer, and the mask pattern includes a first portion filled in the first opening and a second portion located on the top surface of the dielectric layer. Said portion of the dielectric layer is located between the insulating wall and the second portion of the mask pattern from a top view. The portion of the dielectric layer is removed to form a second opening. Remove the mask pattern.

In an embodiment of the invention, a method for forming a mask pattern includes the following steps. A mask material layer is formed on the dielectric layer, wherein the mask material layer is filled into the first opening and covers the insulating wall. The mask material layer is patterned to form a first portion of the mask pattern filling the first opening and a second portion of the mask pattern on the top surface of the dielectric layer.

In an embodiment of the present invention, the second portion of the mask pattern includes a first material layer formed on the top surface of the dielectric layer and a second material layer formed on the first material layer, and the mask pattern The material of the first part is the same as that of the first material layer.

In an embodiment of the invention, the second opening is formed to expose the source/drain.

In an embodiment of the invention, a method for forming an insulating wall includes the following steps. After forming the first opening in the dielectric layer, an insulating material layer is formed on the top surface of the dielectric layer and the sidewall and bottom surface of the first opening. The insulating material layer on the top surface of the dielectric layer and the bottom surface of the first opening is removed to form an insulating wall on the sidewall of the first opening.

In an embodiment of the invention, the second opening has a third sidewall adjacent to the gate and a fourth sidewall adjacent to the isolation structure in the horizontal direction, and the top of the third sidewall is higher than the top of the fourth sidewall.

In an embodiment of the invention, a method for forming a capacitor structure includes the following steps. A lower electrode material layer is formed on the top surface of the dielectric layer and the surfaces of the first opening and the second opening. Filling the first opening and the second opening with a mask pattern, wherein the mask pattern exposes a part of the lower electrode material layer, and the part of the lower electrode material layer includes the top surface of the lower electrode material layer located on the dielectric layer and extending from the portion of the top surface of the dielectric layer to a portion of the third sidewall of the second opening. The portion of the bottom electrode material layer exposed by the mask pattern is removed to form a bottom electrode. After removing the mask pattern, a dielectric is formed on the lower electrode, wherein a part of the dielectric is formed on a portion of the third sidewall of the second opening. An upper electrode is formed on the dielectric.

A method for manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps. A dielectric layer covering a plurality of transistors is formed on the substrate, wherein the substrate has an isolation structure between two adjacent transistors, and each transistor includes a gate formed on the substrate, a gate formed on the gate and a gate formed on the substrate. A gate dielectric layer between the substrates and a source/drain formed in the substrates at opposite sides of the gate. A first opening is formed in the dielectric layer to expose the isolation structure and the source/drain adjacent to the isolation structure. An insulating material layer is formed on the top surface of the dielectric layer and the sidewall and bottom surface of the first opening. A mask pattern is formed on the insulating material layer. The mask pattern exposes a part of the insulating material layer, and the mask pattern includes a first portion and a second portion separated from each other, wherein the first portion is filled in the first opening, and the second portion is located above the dielectric layer. Said portion of the layer of insulating material is located between the first portion and the second portion of the mask pattern when viewed from above. The portion of the layer of insulating material and a portion of the dielectric layer underlying the portion of the layer of insulating material are removed to form a second opening. Remove the mask pattern. The insulating material layer on the top surface of the dielectric layer and the bottom surface of the first opening is removed to form an insulating wall. The insulation wall has a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall, wherein the second opening exposes a part of the first sidewall of the insulation wall. A capacitor structure is formed in the first opening and the second opening. The capacitor structure is formed on the portion of the first sidewall of the isolation wall and the second sidewall of the isolation wall and is electrically connected to the source/drain of the adjacent isolation structure.

In an embodiment of the present invention, in the step of removing the insulating material layer on the top surface of the dielectric layer and the bottom surface of the first opening, a portion of the insulating material layer at the top end on the sidewall of the first opening is also removed. Then removed, so that the level of the top surface of the dielectric layer is higher than the level of the top of the insulating wall.

In an embodiment of the invention, a method for forming a mask pattern includes the following steps. A mask material layer is formed on the insulating material layer, wherein the mask material layer fills the first opening and covers the insulating wall. Using the insulating material layer as an etching stop layer, a patterning process is performed on the mask material layer to form a mask pattern exposing the portion of the insulating material layer.

In an embodiment of the present invention, the second portion of the mask pattern includes a first material layer formed on the top surface of the dielectric layer and a second material layer formed on the first material layer, wherein the mask pattern The material of the first part is the same as that of the first material layer.

A semiconductor device according to an embodiment of the present invention includes a substrate, a plurality of transistors, an isolation structure, a dielectric layer, a capacitor structure, and an insulating wall. Each transistor includes a gate disposed on a substrate, a gate dielectric layer disposed between the gate and the substrate, and source/drain disposed in the substrate at opposite sides of the gate. The isolation structure is disposed in the substrate and located between two adjacent transistors. The dielectric layer is disposed on the substrate and covers the transistor. The capacitor structure is disposed in the dielectric layer and electrically connected to the source/drain of the adjacent isolation structure. The insulating wall is disposed in the dielectric layer and has a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall. The capacitor structure is arranged on the first side wall and the second side wall of the insulating wall.

In an embodiment of the invention, the top of the insulating wall is lower than the top of the dielectric layer and the bottom of the insulating wall is in contact with the source/drain.

In an embodiment of the present invention, the portion of the capacitor structure disposed on the first side wall of the insulating wall is separated from the source/drain of the adjacent isolation structure by a dielectric layer in the vertical direction, and the capacitor structure is disposed on A portion on the second sidewall of the isolation wall is in contact with the source/drain of the adjacent isolation structure.

In an embodiment of the present invention, wherein the portion of the capacitive structure disposed on the first side wall of the insulating wall is in contact with the source/drain of an adjacent isolation structure, the portion of the capacitive structure disposed on the second side wall of the insulating wall source/drain contacts to adjacent isolation structures.

In an embodiment of the present invention, the semiconductor device further includes an etch stop layer between the dielectric layer and the source/drain, wherein the portion of the capacitor structure disposed on the first sidewall of the insulating wall penetrates the dielectric layer and The source/drain of the adjacent isolation structure is vertically spaced apart by the etch stop layer, and the portion of the capacitor structure disposed on the second sidewall of the insulating wall is in contact with the source/drain of the adjacent isolation structure.

In an embodiment of the present invention, wherein the portion of the capacitor structure disposed on the first side wall of the insulating wall is in contact with the source/drain of an adjacent isolation structure, and the portion of the capacitor structure disposed on the second side wall of the insulating wall Portions are not in contact with the source/drain of adjacent isolation structures.

In an embodiment of the present invention, wherein the capacitive structure includes a lower electrode, a dielectric disposed on the lower electrode, and an upper electrode disposed on the dielectric, wherein the part of the capacitive structure disposed on the first side wall of the insulating layer The dielectric has a portion in contact with the dielectric layer.

Based on the above, in the semiconductor device and its manufacturing method according to the above-mentioned embodiments of the present invention, the capacitor structure is designed to be formed on the first side wall of the insulating wall and the second side wall opposite to the first side wall of the insulating wall, so that the capacitor structure can be increased. The effective surface area enables the semiconductor device to maintain a sufficiently large capacitance even when the size of the element is reduced.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

It will be understood that when an element is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to physical and/or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. "Electrical connection" as used herein may include physical connection (such as wired connection) and physical disconnection (such as wireless connection).

The terms used herein are only used to illustrate exemplary embodiments, not to limit the present disclosure. In such cases, singular forms include plural forms unless the context explains otherwise.

1A to 1G are schematic diagrams of a manufacturing process of a semiconductor device 10 according to an embodiment of the present invention. Figure 1A to Figure 1E, Figure 1F (a) and Figure 1G are schematic cross-sectional views, while Figure 1F (b) is a top view, where Figure 1F (a) is Figure 1F (b) along the section line A-A 'Schematic diagram of the intercepted section. FIG. 2 is a schematic cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention.

Referring to FIG. 1A , an etch stop layer 200 covering a plurality of transistors T1 and T2 is formed on a substrate 100 . The substrate 100 has an isolation structure 102 between two adjacent transistors T1, T2.

The substrate 100 may be a semiconductor substrate such as a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The substrate 100 may be doped (eg, doped with p-type or n-type dopants) or undoped. In some embodiments, the substrate 100 may include elemental semiconductors such as silicon or germanium, or compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, alloy semiconductors, etc. Semiconductor, or such as SiGe, GaAsP, AlInAs. Alloy semiconductors of AlGaAs, GaInAs, GaInP and GaInAsP or combinations thereof, etc.

The isolation structure 102 may be an isolation structure such as a shallow trench isolation (shallow trench isolation, STI) structure, a field oxide layer (field oxide, FOX) and the like. In some embodiments, the isolation structure 102 can be formed through the following steps. First, a mask pattern (not shown) is formed on the substrate 100 to define a region where the substrate 100 is exposed. The mask pattern can be a patterned photoresist layer. Next, a portion of the substrate 100 is removed through the aforementioned region to form a trench (not shown). Then, a dielectric material is filled in the trench. A dielectric material may cover the top surface of the substrate 100 . Afterwards, excess dielectric material is removed through a planarization process (such as a chemical mechanical polishing process), so as to form the isolation structure 102 in the substrate 100 . The dielectric material can be common isolation materials, such as silicon oxide or some other suitable dielectric materials. The dielectric material may be formed by any suitable method, such as chemical vapor deposition (CVD).

The transistors T1 and T2 may include a gate GE formed on the substrate 100, a gate dielectric layer GD formed between the gate GE and the substrate 100, and a gate dielectric layer GD formed in the substrate 100 at opposite sides of the gate GE. Source/Drain S/D. In some embodiments, the transistors T1 and T2 may include spacers GS formed on opposite sidewalls of the gate GE. In the vertical direction, the source/drain S/D may be located between the gate GE and the isolation structure 102 . In some embodiments, the source/drain S/D may extend below the spacer GS. The gate GE may include common gate materials. For example, the gate GE may include doped polysilicon, metal (such as titanium, aluminum, etc.), metal silicide (such as titanium silicide, nickel silicide, etc. metal silicide), or other suitable conductive materials. The gate dielectric layer GD may include commonly used gate dielectric materials. For example, the gate dielectric layer GD may include oxide (such as SiO ₂ ), high dielectric constant material (such as dielectric material with a dielectric constant greater than 3.9), or other suitable dielectric materials. The channels of the transistors T1, T2 may be located between the two source/drains S/D and below the gate GE. The transistors T1 and T2 can be N-type metal oxide semiconductor transistors (NMOS) or P-type metal oxide semiconductor transistors (PMOS).

The etch stop layer 200 can be used as a contact etch stop layer (CESL), but the invention is not limited thereto. The material of the etch stop layer 200 may include silicon nitride.

Next, a dielectric layer 300 covering the plurality of transistors T1 and T2 is formed on the substrate 100 . In some embodiments, etch stop layer 200 may be formed between dielectric layer 300 and substrate 100 . The dielectric layer 300 may include a low dielectric constant material such as silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or a combination thereof.

Referring to FIGS. 1A and 1B , a first opening 302 is formed in the dielectric layer 300 to expose the isolation structure 102 and the source/drain S/D adjacent to the isolation structure 102 . In some embodiments, the first opening 302 is formed through the following steps. First, a patterned photoresist PR1 is formed on the dielectric layer 300 to define a region where the first opening 302 is to be formed on the dielectric layer 300 . Next, a portion of the dielectric layer 300 exposed in the region and the etch stop layer 200 below the portion are removed to expose the isolation structure 102 and a portion of the source/drain S/D adjacent to the isolation structure 102 . After the first opening 302 is formed, the patterned photoresist PR1 can be removed by a suitable method such as ashing.

Next, an insulating material layer 400 is formed on the top surface of the dielectric layer 310 and the sidewall and bottom surface of the first opening 302 . The insulating material layer 400 may be conformally formed on the top surface of the dielectric layer 310 and the surface of the first opening 302 . The material of the insulating material layer 400 may include silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), etc., which have different etching rates from the dielectric layer 310 .

Referring to FIG. 1C and FIG. 1D , a mask pattern MP1 is formed on the insulating material layer 400 . The mask pattern MP1 exposes a portion of the insulating material layer 400 . The mask pattern MP1 includes a first portion MP11 and a second portion MP12 separated from each other. The first portion MP11 of the mask pattern MP1 is filled into the first opening 302 ; and the second portion MP12 of the mask pattern MP1 is formed on the insulating material layer 400 above the dielectric layer 310 . In some embodiments, viewed from above, the portion of the insulating material layer 400 exposed by the mask pattern MP1 is located between the first portion MP11 and the second portion MP12 of the mask pattern MP1.

In some embodiments, the mask pattern MP1 may be formed through the following steps. First, referring to FIG. 1C , a first mask material layer 500 is formed on the insulating material layer 400 . The first mask material layer 500 is formed on the insulating material layer 400 above the dielectric layer 310 and filled into the first opening 302 . The material of the first mask material layer 500 can be, for example, a common material used for a flat layer. Next, a second mask material layer 600 is formed on the first mask material layer 500 . The material of the second mask material layer 600 can be, for example, a common material used for an anti-reflection layer. In some embodiments, the material of the second mask material layer 600 may be different from the material of the first mask material layer 500 . Then, a patterned photoresist PR2 is formed on the second mask material layer 600 to define a region exposing a part of the second mask material layer 600 . Then, please refer to FIG. 1C and FIG. 1D , using the insulating material layer 400 as an etch stop layer, by patterning the part of the second mask material layer 600 exposed by the photoresist PR2, the second mask material layer 600 A patterning process is performed with the first mask material layer 500 to form a mask pattern MP1 exposing a part of the insulating material layer 400 . After the mask pattern MP1 is formed, the patterned photoresist PR2 can be removed by a suitable method such as ashing.

The mask pattern MP1 may include a first portion MP11 formed in the first opening 302 and a second portion MP12 formed on the insulating material layer 400 above the dielectric layer 310 . The first portion MP11 of the mask pattern MP1 may include a portion 510a of the patterned first mask material layer. The second portion MP12 of the mask pattern MP1 may include another portion 510 b of the patterned first mask material layer and the patterned second mask material layer 610 . That is to say, in the case that the second mask material layer 600 is made of a material different from that of the first mask material layer 500, the second portion MP12 of the mask pattern MP1 may include the same material as the first portion MP11 of the mask pattern MP1. The first material layer (for example, another part 510b of the patterned first mask material layer) and the second material layer (for example, patterned Thin second mask material layer 610).

In some embodiments, the top surface of the first portion MP11 of the mask pattern MP1 is slightly lower than the insulation exposed by the mask pattern MP1 due to over etching of the second portion MP12 of the mask pattern MP1. The top surface of the material layer 400, but the invention is not limited thereto. In other embodiments, the top surface of the first portion MP11 of the mask pattern MP1 may also be at the same level as the top surface of the insulating material layer 400 exposed by the mask pattern MP1.

Referring to FIG. 1D and FIG. 1E , a part of the insulating material layer 400 exposed by the mask pattern MP1 and a part of the dielectric layer 310 located below the part of the insulating material layer 400 are removed to form the second opening 304 and each other. The first insulating pattern 410 and the second insulating pattern 420 are spaced apart.

The first insulating pattern 410 may be a cup-shaped structure and may correspond to the portion of the insulating material layer 400 formed on the sidewall and the bottom surface of the first opening 302 , wherein the first insulating pattern 410 corresponds to the portion of the insulating material layer 400 formed on the second opening 302 . The part on the sidewall of an opening 302 can be defined as the sidewall part of the first insulating pattern 410; bottom portion of the insulating pattern 410 . The second insulating pattern 420 may correspond to the insulating material layer 400 covered by the second portion MP12 of the mask pattern MP1.

The second opening 304 may expose a portion of the first insulating pattern 410 . That is, the second opening 304 may include a first sidewall 304a and a second sidewall 304b opposite to each other, wherein the first sidewall 304a may be defined by the first insulating pattern 410 exposed by the second opening 304 (for example, by the second opening 304 are defined by the sidewalls of the first insulating pattern 410 ), while the second sidewalls 304 b may be defined by the dielectric layer 320 .

In some embodiments, the second opening 304 may be formed in the dielectric layer 320 without penetrating through the dielectric layer 320 . In this embodiment, the dielectric layer 320 may include a first portion 320a and a second portion 320b. Viewed from above, the dielectric layer 320 located between the first insulating pattern 410 and the second insulating pattern 420 can be defined as the first portion 320a of the dielectric layer 320, while other portions of the dielectric layer 320 (such as The dielectric layer 320 below the second insulating pattern 420 may be defined as the second portion 320 b of the dielectric layer 320 . In some embodiments, the first portion 320 a of the dielectric layer 320 may surround a portion of the first insulating pattern 410 not exposed by the second opening 304 . In some embodiments, the bottom surface of the second opening 304 may be defined by the first portion 320 a of the dielectric layer 320 , and the second sidewall 304 b of the second opening 304 may be defined by the second portion 320 b of the dielectric layer 320 .

In some embodiments, the second opening 304 can penetrate through the dielectric layer 320 and expose the etch stop layer 200 . In this embodiment, the bottom surface of the second opening 304 may be defined by the etch stop layer 200 .

In some embodiments, in the step of removing a portion of the insulating material layer 400 exposed by the mask pattern MP1 and a portion of the dielectric layer 310 below the portion of the insulating material layer 400, a portion of the mask pattern MP1 It is also removed, so the thickness of the first part MP21 of the mask pattern MP2 shown in FIG. 1E is smaller than the thickness of the first part MP11 of the mask pattern MP1 shown in FIG. 1D, and the second part of the mask pattern MP2 The thickness of the portion MP22 is smaller than the thickness of the second portion MP12 of the mask pattern MP1. In some embodiments, the material of the first portion MP21 of the mask pattern MP2 is the same as that of the second portion MP22 of the mask pattern MP2. In some embodiments, the level of the top surface of the first portion MP21 of the mask pattern MP2 is lower than the level of the bottom surface of the second opening 304 , but the invention is not limited thereto. In other embodiments, the second opening 304 may expose the etch stop layer 200 , and the first portion MP21 of the mask pattern MP2 may be removed to expose the bottom portion of the first insulating pattern 410 .

Please refer to FIG. 1E and (a) and (b) of FIG. 1F , after removing the mask pattern MP2, the bottom part of the first insulating pattern 410 (corresponding to the insulating The portion of the material layer 400 formed on the bottom surface of the first opening 302 ) and the second insulating pattern 420 on the top surface of the dielectric layer 320 to form an insulating wall 430 . The insulation wall 430 may have a first sidewall 430a facing the dielectric layer 320 and a second sidewall 430b opposite to the first sidewall 430a.

In some embodiments, in the step of removing the bottom portion of the first insulating pattern 410 and the second insulating pattern 420, a part of the top of the sidewall portion of the first insulating pattern 410 (corresponding to the portion of the insulating material layer 400 formed on the second The portion at the top of the sidewall of an opening 302 is also removed, so that the top surface of the second portion 320 b of the dielectric layer 320 is at a higher level than the top of the insulating wall 430 . In this way, the height of the first sidewall 304a of the second opening 304 defined by the first insulating pattern 410 also decreases, while the height of the second sidewall 304b of the second opening 304 defined by the dielectric layer 320 remains maintained. In this way, the third opening 306 and the fourth opening 432 as shown in (a) of FIG. 1F can be formed. One sidewall of the third opening 306 is defined by the first sidewall 430 a of the insulating wall 430 , and the other sidewall of the third opening 306 is defined by the dielectric layer 320 . The sidewall of the fourth opening 432 is defined by the second sidewall 430 b of the insulating wall 430 .

Please refer to (a) and (b) of FIG. 1F and FIG. 1G , in the third opening 306 (the relative position thereof may correspond to the second opening 304 ) and the fourth opening 432 (the relative position thereof may correspond to the first opening 302 ) A capacitive structure CS is formed in it. The capacitive structure CS may include a lower electrode BE, a dielectric DL formed on the lower electrode BE, and an upper electrode TE formed on the dielectric DL. The capacitor structure CS is designed to be formed on a part of the first sidewall 430 a of the isolation wall 430 and the second sidewall 430 b of the isolation wall 430 and electrically connected to the source/drain S/D of the adjacent isolation structure 102 . In this way, the effective surface area of the capacitive structure CS (that is, the area of the dielectric DL overlapping between the upper electrode TE and the lower electrode BE) will be able to increase, so that even if the size of the semiconductor device 10 is reduced, the semiconductor device 10 still maintains Can maintain a large enough capacity.

In some embodiments, in the case that the portion of the capacitive structure CS disposed on the second side wall 430b of the insulating wall 430 is in contact with the source/drain S/D of the adjacent isolation structure 102, the capacitive structure CS is disposed on the insulating wall 430. There are three possible configurations of the portion on the first side wall 430 a of the wall 430 and the source/drain S/D adjacent to the isolation structure 102 , but not limited to the following three. The first configuration relationship is: the part of the capacitive structure CS disposed on the first side wall 430a of the insulating wall 430 and the source/drain S/D of the adjacent isolation structure 102 are vertically covered by the first part of the dielectric layer 320 320a spaced apart. The second configuration relationship is: the part of the capacitor structure CS disposed on the first side wall 430a of the insulating wall 430 can penetrate the first part 320a of the dielectric layer 320 and connect to the source/source of the adjacent isolation structure 102 through the etch stop layer 200 The drains S/D are spaced apart in the vertical direction. The third configuration relationship is: the part of the capacitive structure CS disposed on the first side wall 430a of the insulating wall 430 can penetrate the first part 320a of the dielectric layer 320 and the etch stop layer 200 and connect with the source/drain of the adjacent isolation structure 102 Pole S/D contacts. For example, in the semiconductor device 20 shown in FIG. 2 , the capacitive structure CS1 includes a lower electrode BE1 , a dielectric DL1 formed on the lower electrode BE1 , and an upper electrode TE1 formed on the dielectric DL1 . The portion of the capacitive structure CS1 disposed on the second sidewall 430b of the insulating wall 430 may be in contact with the source/drain S/D of the adjacent isolation structure 102, and the portion of the capacitive structure CS1 disposed on the first sidewall 430a of the insulating wall 430 A portion of α may penetrate through the dielectric layer 320 and the etch stop layer 200 and be in contact with the source/drain S/D adjacent to the isolation structure 102 .

In some other embodiments, in the case that the portion of the capacitive structure CS disposed on the second sidewall 430b of the insulating wall 430 is not in contact with the source/drain S/D of the adjacent isolation structure 102 (not shown), The portion of the capacitor structure CS disposed on the first sidewall 430 a of the isolation wall 430 may penetrate the first portion 320 a of the dielectric layer 320 and the etch stop layer 200 and contact the source/drain S/D adjacent to the isolation structure 102 .

The material of the bottom electrode BE or the top electrode TE can be selected including titanium (Ti), cobalt (Co), copper (Cu), copper-aluminum (AlCu), tungsten (W), titanium nitride (TiN), tungsten nitride (TiW), aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The dielectric DL can be selected from, for example, a material with a high dielectric constant. The bottom electrode BE, the dielectric DL or the top electrode TE can be formed by a suitable method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

In some embodiments, the capacitive structure CS is formed by the following steps, for example. First, a lower electrode material layer (not shown) and a dielectric material layer (not shown) are sequentially formed on the dielectric layer 320 , on the surface of the third opening 306 and on the surface of the fourth opening 432 (conformally). out). Next, an upper electrode material layer (not shown) is formed on the dielectric material layer. The upper electrode material layer fills the remaining space of the third opening 306 and the fourth opening 432 (that is, the space in the third opening 306 and the fourth opening 432 that is not filled with the lower electrode material layer and the dielectric material layer). Then, a patterned photoresist (not shown) is formed on the upper electrode material layer to define a region exposing a part of the upper electrode material layer. Then, a part of the upper electrode material layer and a part of the dielectric material layer and a part of the lower electrode material layer located below the part are removed through this region to form the capacitive structure CS.

3A to 3D are schematic diagrams of the manufacturing process of the semiconductor device 10 according to another embodiment of the present invention. FIG. 3A to FIG. 3D are the continuation of the above-mentioned manufacturing process of FIG. 1A and FIG. 1B . The connection relationship, materials and manufacturing processes of the above-mentioned components shown in FIG. 1A and FIG. 1B have been described in detail above, so they will not be repeated hereafter. In addition, the same or similar components shown in FIG. 3A to FIG. 3D and those in FIG. 1A to FIG. 1G use the same or similar technical terms and element symbols.

Referring to FIG. 1B and FIG. 3A, after the insulating material layer 400 is formed on the top surface of the dielectric layer 310 and the sidewall and bottom surface of the first opening 302, the top surface of the dielectric layer 310 can be removed by means such as etching back. The insulating material layer 400 is formed on the top and the bottom surface of the first opening 302 to form insulating walls 430 on the sidewalls of the first opening 302 . The insulation wall 430 has a first sidewall 430a facing the dielectric layer 310 and a second sidewall 430b opposite to the first sidewall 430a.

Referring to FIG. 3B and FIG. 3C , a mask pattern MP1 is formed on the dielectric layer 310 . The mask pattern MP1 exposes a portion of the dielectric layer 310 . The mask pattern MP1 includes a first portion MP11 and a second portion MP12 separated from each other. The first portion MP11 of the mask pattern MP1 is filled into the first opening 302 ; and the second portion MP12 of the mask pattern MP1 is formed on the top surface of the dielectric layer 310 . In some embodiments, viewed from above, the portion of the dielectric layer 310 exposed by the mask pattern MP1 is located between the first portion MP11 and the second portion MP12 of the mask pattern MP1. In some embodiments, the portion of the dielectric layer 310 exposed by the mask pattern MP1 is located between the insulating wall 430 and the second portion MP12 of the mask pattern MP1.

In some embodiments, the portion of the dielectric layer 310 exposed by the mask pattern MP1 may be slightly lower than the top surface of the dielectric layer 310 due to over etching. The top surface of the portion covered by the first portion MP11 of the mask pattern MP1, but the invention is not limited thereto. In other embodiments, the top surface of the portion of the dielectric layer 310 exposed by the mask pattern MP1 may also have the same top surface as the top surface of the portion of the dielectric layer 310 covered by the first portion MP11 of the mask pattern MP1. level height.

In some embodiments, the top surface of the first portion MP11 of the mask pattern MP1 is slightly lower than the top surface of the insulating wall 430 due to over etching (over etching), but the present invention This is not the limit. In other embodiments, the top surface of the first portion MP11 of the mask pattern MP1 may also have the same level as the top surface of the insulating wall 430 .

In some embodiments, the mask pattern MP1 may be formed through the following steps. First, please refer to FIG. 3B , a first mask material layer 500 is formed on the dielectric layer 310 . The first mask material layer 500 is filled into the first opening 302 and covers the insulation wall 430 . The material of the first mask material layer 500 can be, for example, a common material used for a flat layer. Next, a second mask material layer 600 is formed on the first mask material layer 500 . The material of the second mask material layer 600 can be, for example, a common material used for an anti-reflection layer. In some embodiments, the material of the second mask material layer 600 may be different from the material of the first mask material layer 500 . Then, a patterned photoresist PR2 is formed on the second mask material layer 600 to define a region exposing a part of the second mask material layer 600 . Then, referring to FIG. 3B and FIG. 3C, the second mask material layer 600 and the first mask material layer 500 are patterned by patterning the part of the second mask material layer 600 exposed by the photoresist PR2. process to form the mask pattern MP1 exposing a portion of the dielectric layer 310 and a portion of the insulating wall 430 . After the mask pattern MP1 is formed, the patterned photoresist PR2 can be removed by a suitable method such as ashing.

The mask pattern MP1 may include a first portion MP11 formed in the first opening 302 and a second portion MP12 formed on the dielectric layer 310 . The first portion MP11 of the mask pattern MP1 may include a portion 510a of the patterned first mask material layer. The second portion MP12 of the mask pattern MP1 may include another portion 510 b of the patterned first mask material layer and the patterned second mask material layer 610 . That is to say, in the case that the second mask material layer 600 is made of a material different from that of the first mask material layer 500, the second portion MP12 of the mask pattern MP1 may include the same material as the first portion MP11 of the mask pattern MP1. The first material layer (for example, another part 510b of the patterned first mask material layer) and the second material layer (for example, patterned Thin second mask material layer 610).

Referring to FIG. 3C and FIG. 3D , a part of the dielectric layer 310 exposed by the mask pattern MP1 is removed to form a third opening 306 . The third opening 306 may expose a portion of the insulating wall 430 . That is, the third opening 306 may include a first sidewall and a second sidewall opposite to each other, wherein the first sidewall may be defined by the insulating wall 430 exposed by the third opening 306 (for example, the part of the first sidewall 430 a of the insulating wall 430 ), and the second sidewall of the third opening 306 may be defined by the dielectric layer 320 . In some embodiments, the top of the second sidewall of the third opening 306 defined by the dielectric layer 320 is higher than the top of the first sidewall of the third opening 306 defined by the insulating wall 430 .

In some embodiments, in the step of removing a part of the dielectric layer 310 exposed by the mask pattern MP1, a part of the mask pattern MP1 is also removed, so the mask pattern MP2 shown in FIG. 3D The thickness of the first portion MP21 is smaller than the thickness of the first portion MP11 of the mask pattern MP1 shown in FIG. 3C, and the thickness of the second portion MP22 of the mask pattern MP2 is smaller than the thickness of the second portion MP12 of the mask pattern MP1. . In some embodiments, the material of the first portion MP21 of the mask pattern MP2 is the same as that of the second portion MP22 of the mask pattern MP2. In some embodiments, the level of the top surface of the first portion MP21 of the mask pattern MP2 is lower than the level of the bottom surface of the third opening 306 , but the invention is not limited thereto.

In some embodiments, the third opening 306 may be formed in the dielectric layer 320 without penetrating through the dielectric layer 320 . In this embodiment, the dielectric layer 320 may include a first portion 320a and a second portion 320b. Viewed from above, the dielectric layer 320 below the third opening 306 can be defined as the first portion 320a of the dielectric layer 320, while other portions of the dielectric layer 320 (such as the second portion of the mask pattern MP2 The dielectric layer 320 below MP 22 ) can be defined as the second portion 320b of the dielectric layer 320 . In some embodiments, the first portion 320 a of the dielectric layer 320 may surround a portion of the insulating wall 430 not exposed by the third opening 306 . In some embodiments, the bottom surface of the third opening 306 may be defined by the first portion 320 a of the dielectric layer 320 , and the second sidewall of the third opening 306 may be defined by the second portion 320 b of the dielectric layer 320 .

In some embodiments, the third opening 306 may penetrate through the dielectric layer 320 and expose the etch stop layer 200 . In this embodiment, the bottom surface of the third opening 306 may be defined by the etch stop layer 200 . In other embodiments, the third opening 306 may penetrate through the dielectric layer 320 and the etch stop layer 200 to expose the source/drain S/D adjacent to the isolation structure 102 . In this embodiment, the bottom surface of the third opening 306 may be defined by the exposed source/drain S/D.

Referring to FIG. 3D and (a) and (b) of FIG. 1F , the mask pattern MP2 is removed to form the fourth opening 432 as shown in (a) of FIG. 1F . The sidewall of the fourth opening 432 is defined by the second sidewall 430 b of the insulating wall 430 .

As in (a) and (b) of FIG. 1F and the manufacturing process shown in FIG. 1G, in the third opening 306 (the relative position can correspond to the second opening 304) and the fourth opening 432 (the relative position can correspond to into the first opening 302 ) to form a capacitive structure CS. The capacitive structure CS may include a lower electrode BE, a dielectric DL formed on the lower electrode BE, and an upper electrode TE formed on the dielectric DL. The capacitor structure CS is designed to be formed on a part of the first sidewall 430 a of the isolation wall 430 and the second sidewall 430 b of the isolation wall 430 and electrically connected to the source/drain S/D of the adjacent isolation structure 102 . In this way, the effective surface area of the capacitive structure CS (that is, the area of the dielectric DL overlapping between the upper electrode TE and the lower electrode BE) will be able to increase, so that even if the size of the semiconductor device 10 is reduced, the semiconductor device 10 still maintains Can maintain a large enough capacity.

Hereinafter, the structure of the semiconductor device 10 will be described with reference to FIG. 1F and FIG. 1G . The manufacturing process of the semiconductor device 10 described above is an exemplary embodiment to illustrate the manufacturing method of the semiconductor device 10 , but the structure of the semiconductor device 10 of the present invention is not limited to the manufacturing process described above.

The semiconductor device 10 includes a substrate 100 , a plurality of transistors T1 , T2 , an isolation structure 102 , a dielectric layer 320 , a capacitor structure CS and an isolation wall 430 . Each transistor T1, T2 includes a gate GE formed on the substrate 100, a gate dielectric layer GD disposed between the gate GE and the substrate, and a gate dielectric layer GD disposed in the substrate 100 and located on opposite sides of the gate GE. Source/Drain S/D. The isolation structure 102 is disposed in the substrate 100 and located between two adjacent transistors T1, T2. The dielectric layer 320 is disposed on the substrate 100 and covers the transistors T1, T2. The capacitor structure CS is disposed in the dielectric layer 320 and is electrically connected to the source/drain S/D adjacent to the isolation structure 102 . The insulation wall 430 is disposed in the dielectric layer 320 and has a first sidewall 430a facing the dielectric layer 320 and a second sidewall 430b opposite to the first sidewall 430a. The capacitor structure CS is disposed on the first sidewall 430 a and the second sidewall 430 b of the insulating wall 430 .

In some embodiments, the top of the isolation wall 430 is lower than the top of the dielectric layer 320 and the bottom of the isolation wall 430 is in contact with the source/drain S/D.

In some embodiments, the portion of the capacitive structure CS disposed on the first sidewall 430a of the insulating wall 430 is spaced vertically from the source/drain S/D of the adjacent isolation structure 102 by the dielectric layer 320 , The portion of the capacitor structure CS disposed on the second sidewall 430b of the isolation wall 430 is in contact with the source/drain S/D of the adjacent isolation structure 102 , but the invention is not limited thereto. In some other embodiments, in the semiconductor device 20 shown in FIG. , and the portion of the capacitor structure CS disposed on the second sidewall 430 b of the isolation wall 430 is in contact with the source/drain S/D of the adjacent isolation structure 102 .

4A to 4E are schematic diagrams of the manufacturing process of the semiconductor device 30 according to yet another embodiment of the present invention. 4A to 4E are the continuation of the above-mentioned manufacturing process of FIG. 1F . The connection relationship, materials and manufacturing processes of the components shown in FIGS. 1A to 1F have been described in detail above, so they will not be repeated hereafter. In addition, the same or similar components shown in FIGS. 4A to 4E and those in FIGS. 1A to 1G use the same or similar technical terms and element symbols.

Referring to FIG. 1F and FIG. 4A , the bottom electrode material layer BEM2 is conformally formed on the top surface of the dielectric layer 320 and the surfaces of the third opening 306 and the fourth opening 432 . Next, a mask material layer 700 is formed on the bottom electrode material layer BEM2. The mask material layer 700 fills up the remaining space in the third opening 306 and the fourth opening 432 (eg, the space in which the bottom electrode material layer BEM2 is not formed). The material of the mask material layer 700 can be, for example, a common material used for a flat layer.

In some embodiments, the bottom electrode BE2 may be formed through the following steps. First, please refer to FIG. 4A and FIG. 4B , the mask material layer 700 on the second portion 320 b of the dielectric layer 320 may be removed by means of etch back to form a mask pattern 710 . In the above steps, a part of the mask material layer 700 located in the third opening 306 and the fourth opening 432 is also removed, so the top surface of the mask pattern 710 is lower than the dielectric layer 320 and the second part 320b. top surface. In other words, the mask pattern 710 covers a part of the bottom electrode material layer BEM2 in the third opening 306 and the fourth opening 432 and exposes the top surface of the bottom electrode material layer BEM2 in the second portion 320b of the dielectric layer 320. A portion of the upper and lower electrode material layer BEM2 extends from said portion on the top surface of the second portion 320b of the dielectric layer 320 to a sidewall in the third opening 306 defined by the second portion 320b of the dielectric layer 320 part of the above. Next, please refer to FIG. 4B and FIG. 4C , the lower electrode material layer BEM2 exposed by the mask pattern 710 may be removed by means of etch back to form the lower electrode BE2 . Next, after the bottom electrode BE2 is formed, the mask pattern 710 is removed.

In other embodiments, the bottom electrode BE2 may be formed through the following steps. Please refer to FIG. 4A to FIG. 4C at the same time. Firstly, the bottom electrode material layer BEM2 and the mask material layer 700 on the second portion 320 b of the dielectric layer 320 may be simultaneously removed by means of etch back. Since the portion of the mask material layer 700 located in the third opening 306 and the fourth opening 432 is thicker than the lower electrode material layer BEM2 located on the second portion 320b of the dielectric layer 320 and the mask material layer 700 above it, After simultaneously removing the lower electrode material layer BEM2 and the mask material layer 700 on the second portion 320b of the dielectric layer 320 by etching back, the remaining mask material layer 700 and the lower electrode material layer BEM2 will be located on the third A mask pattern 710 as shown in FIG. 4B and a bottom electrode BE2 as shown in FIG. 4C are respectively formed in the opening 306 and the fourth opening 432 . Next, the mask pattern 710 is removed to form the bottom electrode BE2.

Referring to FIG. 4C and FIG. 4D , a dielectric material layer DLM2 is conformally formed on the bottom electrode BE1 and the dielectric layer 320 . A portion of the dielectric material layer DLM2 is formed on a portion of the sidewall of the third opening 306 defined by the dielectric layer 320 . Next, a top electrode material layer TEM2 is formed on the dielectric material layer DLM2. The upper electrode material layer TEM2 fills up the remaining space in the third opening 306 and the fourth opening 432 (for example, the space where the lower electrode BE1 and the dielectric material layer DLM2 are not formed).

Referring to FIG. 4D and FIG. 4E , the upper electrode material layer TEM2 and the dielectric material layer DLM2 are subjected to a planarization process (such as a chemical mechanical polishing process or an etch-back method) to remove the dielectric material on the dielectric layer 320. The layer DLM2 and the top electrode material layer TEM2 can form a capacitive structure CS2 in the dielectric layer 320 including the bottom electrode BE2 , the dielectric DL2 and the top electrode TE2 . In this embodiment, in the portion of the capacitive structure CS2 disposed on the first sidewall 430 a of the insulating layer 430 , the dielectric DL2 of the capacitive structure CS2 has a portion in contact with the dielectric layer 320 . It can be seen that the steps shown in FIGS. 4A to 4D can be used to form the capacitor structure CS2 in the dielectric layer 320 without additional photomask process.

To sum up, in the semiconductor device and its manufacturing method of the above-mentioned embodiments, the capacitor structure is designed to be formed on the first side wall of the insulating wall and the second side wall opposite to the first side wall of the insulating wall, so that the capacity of the capacitor structure can be increased. The effective surface area enables the semiconductor device to maintain a sufficiently large capacitance even when the size of the element is reduced.

10, 20, 30: Semiconductor devices 100: base 102: Isolation structure 200: etch stop layer 300, 310, 320: dielectric layer 302: first opening 304: second opening 304a, 430a: first side wall 304b, 430b: second side wall 306: The third opening 320a: Part I 320b: Part II 400: insulating material layer 410: the first insulation pattern 420: second insulation pattern 430: Insulation Wall 432: The fourth opening 500: The first mask material layer 510a: Portion of Patterned First Mask Material Layer 510b: Another portion of the patterned first mask material layer 600: second mask material layer 610: Patterned Second Mask Material Layer 700: mask material layer 710:Mask pattern BE, BE1, BE2: Bottom electrode BEM2: Bottom electrode material layer CS, CS1, CS2: capacitor structure DL, DL1, DL2: dielectric DLM2: Dielectric material layer GE: Gate GD: gate dielectric layer GS: gap wall MP1, MP2: mask pattern MP11, MP21: Part 1 MP12, MP22: Part Two PR1, PR2: patterned photoresist S/D: source/drain T1, T2: Transistor TE, TE1, TE2: upper electrode TEM2: upper electrode material layer

1A to 1G are schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. 3A to 3D are schematic diagrams of a manufacturing process of a semiconductor device according to another embodiment of the present invention. 4A to 4E are schematic diagrams of a manufacturing process of a semiconductor device according to yet another embodiment of the present invention.

10: Semiconductor device

100: base

102: Isolation structure

200: etch stop layer

320: dielectric layer

320a: Part I

320b: Part II

430: Insulation Wall

430a: first side wall

430b: second side wall

BE: Bottom electrode

CS: capacitor structure

DL: Dielectric

GE: Gate

GD: gate dielectric layer

GS: gap wall

S/D: source/drain

TE: upper electrode

Claims (19)

A method of manufacturing a semiconductor device, comprising: A dielectric layer covering a plurality of transistors is formed on the substrate, the substrate has an isolation structure between two adjacent transistors, and each transistor includes a gate formed on the substrate, formed on the a gate dielectric layer between the gate and the substrate, and source/drain formed in the substrate at opposite sides of the gate; forming a first opening in the dielectric layer to expose the isolation structure and the source/drain adjacent to the isolation structure; forming an insulating wall on a sidewall of the first opening, the insulating wall having a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall; forming a second opening in the dielectric layer exposing a portion of the first sidewall of the insulating wall; and forming a capacitive structure in the first opening and the second opening, the capacitive structure being formed on the portion of the first sidewall of the insulating wall and on the second sidewall of the insulating wall and electrically connected to the source/drain adjacent to the isolation structure. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the second opening comprises: A mask pattern is formed on the dielectric layer, the mask pattern exposes a portion of the dielectric layer, the mask pattern includes a first portion filled in the first opening and a portion located on the dielectric layer. a second portion on the top surface of the layer, said portion of said dielectric layer being located between said insulating wall and said second portion of said mask pattern when viewed from above; removing the portion of the dielectric layer to form the second opening; and The mask pattern is removed. The method for manufacturing a semiconductor device as claimed in item 2, wherein the step of forming the mask pattern comprises: forming a mask material layer on the dielectric layer, the mask material layer filling the first opening and covering the insulating wall; and patterning the mask material layer to form the first portion of the mask pattern filling the first opening and the mask pattern on a top surface of the dielectric layer. the second part. The manufacturing method of a semiconductor device as claimed in claim 2, wherein the second portion of the mask pattern includes a first material layer formed on the top surface of the dielectric layer and a first material layer formed on the first A second material layer on a material layer, the material of the first portion of the mask pattern is the same as that of the first material layer. The method of manufacturing a semiconductor device according to claim 2, wherein the second opening is formed to expose the source/drain. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the insulating wall comprises: forming a layer of insulating material on a top surface of the dielectric layer and on sidewalls and a bottom surface of the first opening after forming the first opening in the dielectric layer; and The insulating material layer on the top surface of the dielectric layer and the bottom surface of the first opening is removed to form the insulating wall on the sidewall of the first opening. The method for manufacturing a semiconductor device according to claim 1, wherein the second opening has a third side wall defined by the dielectric layer and a fourth side wall defined by an insulating wall, and the third side wall The top is higher than the top of the fourth side wall. The method for manufacturing a semiconductor device as claimed in item 7, wherein the step of forming the capacitor structure includes: forming a lower electrode material layer on the top surface of the dielectric layer and the surfaces of the first opening and the second opening; Filling the first opening and the second opening with a mask pattern, the mask pattern exposing a part of the lower electrode material layer, the part of the lower electrode material layer including the lower electrode a portion of the material layer located on the top surface of the dielectric layer and a portion extending from the portion of the top surface of the dielectric layer to the third sidewall of the second opening; removing the portion of the bottom electrode material layer exposed by the mask pattern to form a bottom electrode; forming a dielectric on the lower electrode after removing the mask pattern, a portion of the dielectric is formed on the portion of the third sidewall of the second opening; and An upper electrode is formed on the dielectric. A method of manufacturing a semiconductor device, comprising: A dielectric layer covering a plurality of transistors is formed on a base, the base has an isolation structure between two adjacent transistors, each transistor includes a gate formed on the base, a gate formed on the gate a gate dielectric layer between the gate and the substrate and a source/drain formed in the substrate and located on opposite sides of the gate; forming a first opening in the dielectric layer to expose the isolation structure and the source/drain adjacent to the isolation structure; forming a layer of insulating material on the top surface of the dielectric layer and the sidewalls and bottom surfaces of the first opening; forming a mask pattern on the insulating material layer, the mask pattern exposing a part of the insulating material layer, the mask pattern including a first part and a second part separated from each other, the first part filling the first opening, the second portion is located above the dielectric layer, and the portion of the insulating material layer is located at the first portion of the mask pattern from a top view. and said second part; removing the portion of the layer of insulating material and a portion of the dielectric layer underlying the portion of the layer of insulating material to form a second opening; removing the mask pattern; removing the layer of insulating material on the top surface of the dielectric layer and the bottom surface of the first opening to form an insulating wall having a first a side wall and a second side wall opposite the first side wall, the second opening exposing a portion of the first side wall of the insulating wall; and forming a capacitive structure in the first opening and the second opening, the capacitive structure being formed on the portion of the first sidewall of the insulating wall and on the second sidewall of the insulating wall and electrically connected to the source/drain adjacent to the isolation structure. The method for manufacturing a semiconductor device according to claim 9, wherein in the step of removing the insulating material layer on the top surface of the dielectric layer and the bottom surface of the first opening, the A part of the top of the insulating material layer on the sidewall of the first opening is also removed, so that the level of the top surface of the dielectric layer is higher than the level of the top of the insulating wall. high. The method for manufacturing a semiconductor device as claimed in item 9, wherein the step of forming the mask pattern comprises: forming a mask material layer on the insulating material layer, the mask material layer filling the first opening and covering the insulating material layer; and Using the insulating material layer as an etching stop layer, a patterning process is performed on the mask material layer to form the mask pattern exposing the portion of the insulating material layer. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the second portion of the mask pattern includes a first material layer formed on the top surface of the dielectric layer and a first material layer formed on the first material layer. A second material layer on a material layer, the material of the first portion of the mask pattern is the same as that of the first material layer. A semiconductor device comprising: base; A plurality of transistors, each transistor including a gate formed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a gate dielectric layer disposed in the substrate and located at the gate source/drain at opposite sides of the an isolation structure disposed in the substrate and located between two adjacent transistors; a dielectric layer disposed on the substrate and covering the plurality of transistors; a capacitor structure disposed in the dielectric layer and electrically connected to the source/drain adjacent to the isolation structure; and an insulating wall disposed in the dielectric layer and having a first sidewall facing the dielectric layer and a second sidewall opposite to the first sidewall, Wherein the capacitor structure is disposed on the first side wall and the second side wall of the insulating wall. The semiconductor device according to claim 13, wherein a top of the insulating wall is lower than a top of the dielectric layer and a bottom of the insulating wall is in contact with the source/drain. The semiconductor device according to claim 13, wherein the portion of the capacitive structure disposed on the first side wall of the insulating wall is vertically separated from the source/drain adjacent to the isolation structure The dielectric layer is spaced apart, and a portion of the capacitive structure disposed on the second sidewall of the insulating wall is in contact with the source/drain adjacent to the isolation structure. The semiconductor device according to claim 13, wherein a portion of the capacitive structure disposed on the first side wall of the insulating wall is in contact with the source/drain adjacent to the isolation structure, the capacitive A portion of the structure disposed on the second sidewall of the isolation wall is in contact with the source/drain adjacent to the isolation structure. The semiconductor device as claimed in claim 13, further comprising: an etch stop layer between the dielectric layer and the source/drain, Wherein the portion of the capacitor structure disposed on the first sidewall of the insulating wall penetrates through the dielectric layer and is connected to the source/drain adjacent to the isolation structure through the etch stop layer. Spaced apart in the vertical direction, portions of the capacitive structures disposed on the second sidewalls of the insulating walls are in contact with the source/drain adjacent to the isolation structures. The semiconductor device according to claim 13, wherein a portion of the capacitive structure disposed on the first side wall of the insulating wall is in contact with the source/drain adjacent to the isolation structure, the capacitive A portion of the structure disposed on the second sidewall of the isolation wall is not in contact with the source/drain adjacent to the isolation structure. The semiconductor device according to claim 13, wherein the capacitive structure includes a lower electrode, a dielectric disposed on the lower electrode, and an upper electrode disposed on the dielectric, wherein the capacitive structure In a portion provided on the first sidewall of the insulating layer, the dielectric of the portion of the capacitive structure has a portion in contact with the dielectric layer.

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