TW202204909A - Testing fixture for ball grid array package chip to solve the problem of the prior art in poor positioning accuracy of the chip under test - Google Patents
Testing fixture for ball grid array package chip to solve the problem of the prior art in poor positioning accuracy of the chip under test Download PDFInfo
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- TW202204909A TW202204909A TW109125431A TW109125431A TW202204909A TW 202204909 A TW202204909 A TW 202204909A TW 109125431 A TW109125431 A TW 109125431A TW 109125431 A TW109125431 A TW 109125431A TW 202204909 A TW202204909 A TW 202204909A
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- chip
- grid array
- ball grid
- base
- top support
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- 238000012360 testing method Methods 0.000 title abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 238000003825 pressing Methods 0.000 claims abstract description 14
- 238000007689 inspection Methods 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims 1
- 238000007731 hot pressing Methods 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
本發明係有關一種球柵陣列封裝晶片之檢測治具,尤指一種將相對待測試晶片之錫球接腳具有導引定位孔之頂撐膜片結合於基座底面之設計者。The present invention relates to a test fixture for ball grid array packaging chips, in particular to a designer for combining a top support film with guiding and positioning holes relative to the solder ball pins of the chip to be tested to the bottom surface of a base.
按,球柵陣列封裝(Ball grid array packed )晶片的底部表面具有許多錫球接腳,可利用錫球接腳直接與測試電路板接觸而進行測試作業:如〔圖1〕所示,習知的球柵陣列封裝晶片檢測治具,其於一基座10內部具有一推壓空間11且樞設有一對彈力壓制件12,該推壓空間11底部具有一容置孔13,該容置孔13底緣具有頂撐凸緣14:測試時,該對彈力壓制件12先被頂開,讓晶片推壓器(圖未示)將待測試晶片20吸移至該容置孔13,而由該頂撐凸緣14將待測試晶片20頂撐定位,且讓該對彈力壓制件12恢復壓制待測試晶片20的狀態,即可對待測試晶片20進行測試作業:然而,該容置孔13的尺寸勢必要比待測試晶片20的尺寸稍大一些,才有助於晶片推壓器將待測試晶片20吸移至該容置孔13,但也可能因此造成待測試晶片20的定位產生偏差,進而影響測試作業的進行或/及正確性。Press, the bottom surface of the ball grid array package (Ball grid array packed) chip has many solder ball pins, and the solder ball pins can be used to directly contact the test circuit board for testing operations: as shown in Fig. 1, the conventional The ball grid array package chip inspection fixture has a pushing
本發明之主要目的,係欲解決先前技術造成待測試晶片定位準確性較差之問題,而具有提升待測試晶片定位準確性之功效。The main purpose of the present invention is to solve the problem of poor positioning accuracy of the wafer under test caused by the prior art, and has the effect of improving the positioning accuracy of the wafer under test.
本發明之另一目的,則具有提升測試正確性之功效。Another object of the present invention is to improve the accuracy of the test.
本發明之又一目的,乃具有避免待測試晶片結構受損之功效。Another object of the present invention is to prevent damage to the structure of the chip to be tested.
為達上述功效,本發明之結構特徵,係於一基座內部具有一推壓空間,該推壓空間底部具有一容置孔,該基座底面結合一頂撐膜片,該頂撐膜片相對待測試晶片之錫球接腳具有導引定位孔。In order to achieve the above-mentioned effect, the structural feature of the present invention is that there is a pushing space inside a base, and the bottom of the pushing space has an accommodating hole, and the bottom surface of the base is combined with a top support film, the top support film There are guiding and positioning holes corresponding to the solder ball pins of the chip to be tested.
此外,該基座內部樞設有一對彈力壓制件:該導引定位孔底端還具有下倒角;該導引定位孔頂端還具有上倒角;該基座底面具有數個結合柱,該頂撐膜片相對各該結合柱具有數個結合孔:各該結合柱於各該結合孔套入後熱壓成型出固定凸緣。In addition, a pair of elastic pressing parts are pivoted inside the base: the bottom end of the guide and positioning hole also has a lower chamfer; the top of the guide and positioning hole also has an upper chamfer; the bottom surface of the base has several combining columns, the The top support membrane has several coupling holes relative to each of the coupling posts: each coupling post is inserted into each of the coupling holes to form a fixing flange by hot pressing.
藉此,將相對待測試晶片之錫球接腳具有導引定位孔之頂撐膜片結合於基座底面,當晶片推壓器將待測試晶片吸移至容置孔時,待測試晶片會因其錫球接腳受到導引定位孔的自然導引而快速且準確定位於頂撐膜片上。In this way, the top support film with guiding and positioning holes relative to the solder ball pins of the chip to be tested is combined with the bottom surface of the base. When the chip pusher sucks the chip to be tested to the accommodating hole, the chip to be tested will Because the solder ball pins are naturally guided by the guiding and positioning holes, they can be quickly and accurately positioned on the top support diaphragm.
首先,請參閱〔圖2〕~〔圖4〕所示,本發明係於一基座30內部具有一推壓空間31且樞設有一對彈力壓制件32,該推壓空間31底部具有一容置孔33,該基座30底面結合一頂撐膜片40,該頂撐膜片40相對待測試晶片20之錫球接腳21具有導引定位孔41:其中,該基座30底面具有數個結合柱34,該頂撐膜片40相對各該結合柱34具有數個結合孔42,各該結合柱34於各該結合孔42套入後熱壓成型出固定凸緣341。First, please refer to [FIG. 2] to [FIG. 4], in the present invention, a
基於如是之構成,本發明將相對待測試晶片20之錫球接腳21具有導引定位孔41之頂撐膜片40結合於基座30底面,當晶片推壓器將待測試晶片20吸移至容置孔33時,待測試晶片20會因其錫球接腳21受到導引定位孔41的自然導引而快速且準確定位於頂撐膜片40上,而該導引定位孔41頂端還可具有上倒角412,進一步強化該導引定位孔41的導引效果:是以,具有提升待測試晶片定位準確性之功效。Based on such a configuration, the present invention combines the
再者,該導引定位孔41底端還具有下倒角411,當待測試晶片20之錫球接腳21所接觸的測試電路板為橡膠插座類型(Rubber Socket Type)時,下倒角411可增加錫球接腳21與測試電路板的接觸面積,進一步具有提升測試正確性之功效;而當待測試晶片20之錫球接腳21所接觸的測試電路板為彈簧結構探針型(Pogo Type),下倒角411可讓錫球接腳21與測試電路板的接觸過程,具有退縮的空間避免錫球接腳21結構受到損傷,進一步具有避免待測試晶片結構受損之功效。Furthermore, the bottom end of the
綜上所述,本發明所揭示之構造,為昔所無,且確能達到功效之增進,並具可供產業利用性,完全符合發明專利要件,祈請 鈞局核賜專利,以勵創新,無任德感。To sum up, the structure disclosed in the present invention is unprecedented, and can indeed achieve the improvement of efficacy, and is available for industrial use, and fully complies with the requirements of an invention patent. , without any sense of virtue.
惟,上述所揭露之圖式、說明,僅為本發明之較佳實施例,大凡熟悉此項技藝人士,依本案精神範疇所作之修飾或等效變化,仍應包括在本案申請專利範圍內。However, the drawings and descriptions disclosed above are only preferred embodiments of the present invention, and modifications or equivalent changes made by those skilled in the art according to the spirit of the present case should still be included in the scope of the patent application of the present case.
10:基座 11:推壓空間 12:彈力壓制件 13:容置孔 14:頂撐凸緣 20:待測試晶片 21:錫球接腳 30:基座 31:推壓空間 32:彈力壓制件 33:容置孔 34:結合柱 341:固定凸緣 40:頂撐膜片 41:導引定位孔 411:下倒角 412:上倒角 42:結合孔10: Pedestal 11: Push the space 12: Elastic pressing parts 13: accommodating hole 14: Top support flange 20: Wafer to be tested 21: Solder Ball Pins 30: Pedestal 31: Push Space 32: Elastic pressing 33: accommodating hole 34: Binding column 341: Fixed flange 40: top support diaphragm 41: Guide positioning hole 411: Lower chamfer 412: Upper chamfer 42: binding hole
〔圖1〕係習知球柵陣列封裝晶片檢測治具之結構剖示圖。 〔圖2〕係本發明之結構剖示圖。 〔圖3〕係本發明之結構外觀圖(一)。 〔圖4〕係本發明之結構外觀圖(二)。[FIG. 1] is a cross-sectional view of the structure of a conventional ball grid array package chip inspection jig. [FIG. 2] is a cross-sectional view of the structure of the present invention. [Fig. 3] is a structural appearance view (1) of the present invention. [Fig. 4] is a structural appearance view (2) of the present invention.
20:待測試晶片20: Wafer to be tested
21:錫球接腳21: Solder Ball Pins
30:基座30: Pedestal
31:推壓空間31: Push Space
32:彈力壓制件32: Elastic pressing
33:容置孔33: accommodating hole
341:固定凸緣341: Fixed flange
40:頂撐膜片40: top support diaphragm
41:導引定位孔41: Guide positioning hole
411:下倒角411: Lower chamfer
412:上倒角412: Upper chamfer
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN114076880A (en) * | 2020-08-03 | 2022-02-22 | 东宸精密股份有限公司 | Inspection Fixture for Ball Grid Array Chips |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN114076880A (en) * | 2020-08-03 | 2022-02-22 | 东宸精密股份有限公司 | Inspection Fixture for Ball Grid Array Chips |
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