TW202141796A - Pixel structure - Google Patents

Abstract

The pixel electrode includes a substrate, at least one transistor, at least one interlayer dielectric layer, and at least one data line. The transistor is disposed on the substrate. The transistor has a drain, a gate, a gate insulator layer and a semiconductor layer. The gate partially overlaps the semiconductor layer. The inter-layer interlayer dielectric layer is disposed on the substrate and covers the gate and the semiconductor layer. The interlayer dielectric layer has a first opening and a second opening. The semiconductor layer has a first region and a neighboring second region. The first opening overlaps the first region. The second opening overlaps the second region. The first portion of the data line is disposed in the first opening and contacts the first region through the first opening to function as a source of the transistor. A normal projection of the first portion of the data line along the first direction on the substrate is within a normal projection of the first opening along the first direction on the substrate.

Description

Pixel structure

The present invention relates to a pixel structure, in particular to a pixel structure with data lines located in the openings of the interlayer dielectric layer.

A virtual reality (VR) display is a small display that sets a set of lens groups at a position very close to the eyes to view images, which actually enlarges the pixels for viewing. Therefore, the pixel aperture ratio of the virtual reality display is very important. If too much shading will affect the light transmittance in the bright state, but too little shading may cause light leakage in the dark state, resulting in low pixel contrast The problem.

The present invention provides a pixel structure, which can reduce light leakage in a dark state.

The pixel structure of the present invention includes a substrate, at least one transistor, at least one interlayer dielectric layer, and at least one data line. The transistor is arranged on the substrate. The transistor has a drain, a gate, a gate insulating layer and a semiconductor layer. The gate insulating layer is arranged between the gate and the semiconductor layer, and the gate and the semiconductor layer partially overlap. The interlayer dielectric layer is arranged on the substrate and covers the gate electrode and the semiconductor layer. The interlayer dielectric layer has a first opening and a second opening, the semiconductor layer has adjacent first and second regions, the first opening overlaps the first region, the second opening overlaps the second region, and the first opening The width along the first direction is 1.1 micrometers to 2.9 micrometers. The data line is arranged on the substrate, wherein the data line extends along the second direction, the first direction and the second direction intersect, the first part of the data line is arranged in the first opening, and the first part of the data line passes through the first The opening contacts the first region to serve as the source of the transistor. The vertical projection of the first part of the data line on the substrate along the first direction is located within the vertical projection of the first opening on the first substrate along the first direction, and the drain is connected to the second region of the semiconductor layer through the second opening.

In an embodiment of the present invention, the aforementioned pixel structure further includes a first light-shielding layer. The first shading layer is located between the substrate and the first part of the data line, the vertical projection of the first opening on the substrate overlaps the vertical projection of the first shading layer on the substrate, and the vertical projection of the first opening on the substrate is located in the first shading The layer is within the vertical projection of the substrate.

In an embodiment of the present invention, the shortest distance between the edge of the first light shielding layer and the edge of the first opening along the first direction is 0.25 μm to 1 μm.

In an embodiment of the present invention, the top surface of the first portion of the aforementioned data line is lower than or equal to the top surface of the interlayer insulating layer.

In an embodiment of the present invention, the aforementioned width is 1.9 μm to 2.5 μm.

In an embodiment of the present invention, the shortest distance along the second direction between the first region and the first opening of the above-mentioned semiconductor layer is greater than 0.5 micrometers.

In an embodiment of the present invention, the aforementioned gate electrode is located above the semiconductor layer.

In an embodiment of the present invention, the aforementioned gate electrode is located under the semiconductor layer.

In an embodiment of the present invention, the cross-sectional shape of the above-mentioned first opening along the first direction is wide at the top and narrow at the bottom.

In an embodiment of the present invention, the above-mentioned first part has a side wall and a bottom that are connected to each other. The side wall and the bottom together form a U-shaped cross-sectional shape along the first direction, and the top surface of the side wall is lower than or equal to the interlayer The top surface of the insulating layer.

Based on the above, the vertical projection of the first part of the data line of the pixel structure of the present invention on the substrate along the first direction is located within the vertical projection of the first opening on the first substrate, thereby preventing light from being affected by the data line. The relatively bright area of the display screen in the dark state caused by the scattering of the edge of the first part and the light leakage. In other words, the dark state light leakage caused by the first part of the data line can be avoided, and the light transmittance in the dark state can be reduced. Since the pixel contrast is the ratio of the light transmittance in the bright state and the dark state, and the light transmittance in the dark state is positively correlated with the light leakage in the dark state, the light leakage in the dark state is reduced, which can make the picture of the pixel structure The element contrast can be improved.

FIG. 1 is a schematic top view of a pixel structure 10 according to an embodiment of the invention. Figure 2 is a schematic cross-sectional view taken along the section line I-I' of Figure 1. Fig. 3 is a schematic cross-sectional view taken along the line II-II' of Fig. 1. Please refer to FIG. 1, FIG. 2 and FIG. 3 together. The pixel structure 10 includes a substrate 102, a transistor T, an interlayer dielectric layer 104, a data line 114, and a gate line 115. For the convenience of description, the first direction D1 and the second direction D2 are shown in Fig. 1, and the first direction D1 and the second direction D2 are different. For example, the first direction D1 and the second direction D2 are as shown in Fig. 1 respectively. The transverse direction and the longitudinal direction are orthogonal to each other. In one embodiment, the pixel structure 10 further includes a buffer layer 106, the buffer layer 106 is located on the substrate 102, and the material of the buffer layer 106 is, for example, oxide. However, the present invention is not limited to this. In other embodiments of the present invention, the buffer layer 106 may not be included. The gate line 115 and the data line 114 intersect. For example, the gate line 115 extends in the first direction D1, and the data line 114 extends in the second direction D2.

In this embodiment, the transistor T is disposed on the substrate 102, and the transistor T has a drain electrode DE, a gate electrode GE, a gate insulating layer GI, and a semiconductor layer 108. In this embodiment, the transistor T is a top gate type thin film transistor, and the gate GE is located above the semiconductor layer 108. In detail, the semiconductor layer 108 is disposed on the buffer layer 106, the gate insulating layer GI is disposed on the semiconductor layer 108 and the buffer layer 106, and the gate GE is disposed on the gate insulating layer GI. That is, the gate insulating layer GI is disposed between the gate GE and the semiconductor layer 108, and the gate GE and the semiconductor layer 108 partially overlap in the normal direction of the substrate 102.

The semiconductor layer 108 may be, for example, a polycrystalline silicon semiconductor layer. However, the material of the semiconductor layer 108 is not limited to polycrystalline silicon, but may be other suitable semiconductors, such as other semiconductor layers (such as amorphous silicon, microcrystalline silicon), and an oxide semiconductor layer such as Indium Gallium Zinc Oxide (IGZO) or other suitable semiconductor materials.

The data line 114 is disposed on the substrate 102. In some embodiments, the data line 114 includes metal, such as titanium, molybdenum, copper, aluminum, silver, or other metals or a combination of the foregoing metals. In this embodiment, the data line 114 includes a multilayer structure, such as a titanium/aluminum/titanium (Ti/Al/Ti) structure or a molybdenum/aluminum/molybdenum (Mo/Al/Mo) structure, but the present invention does not use this Is limited.

In this embodiment, the interlayer dielectric layer 104 is disposed on the substrate 102 and covers the gate GE, the semiconductor layer 108 and the gate insulating layer GI. The interlayer dielectric layer 104 has a first opening 110 and a second opening 112. The opening 110 and the second opening 112 also pass through the gate insulating layer GI. The semiconductor layer 108 has a first region 108a, a second region 108b, and a channel region 108c adjacent to each other. The first region 108a and the second region 108b are heavily doped so that the resistivity of the first region 108a and the second region 108b is smaller than that of the channel region.区108c.

The data line 114 has a first portion 1141. The first portion 1141 is disposed in the first opening 110. The first portion 1141 of the data line 114 contacts the first region 108a through the first opening 110 to serve as the source of the transistor T , And the drain DE is connected to the second region 108b of the semiconductor layer 108 through the second opening 112. That is, the first portion 1141 of the data line 114 located in the first opening 110 overlaps the first region 108a of the semiconductor layer 108, and the drain DE of the transistor T located in the second opening 112 and the semiconductor layer 108 The second area 108b overlaps, and the vertical projection of the first portion 1141 of the data line 114 on the substrate 102 along the first direction D1 is located within the vertical projection of the first opening 110 on the first substrate 102, thereby preventing light from being affected by the data. The edge of the first part 1141 of the line 114 scatters and leaks light, which is a relatively bright area of the display screen in the dark state. In other words, the dark state light leakage caused by the first portion 1141 of the data line 114 can be avoided, and the light transmittance in the dark state can be reduced. It is known that the pixel contrast is the ratio of the light transmittance in the bright state and the dark state, and the light transmittance in the dark state is positively correlated with the light leakage in the dark state. Since the light leakage in the dark state is reduced, the pixel structure 10 The pixel contrast can be improved.

The first opening 110 overlaps the first region 108a, and the second opening 112 overlaps the second region 108b. For example, the width 110w of the first opening 110 along the first direction D1 is 1.1 micrometers to 2.9 micrometers. In a preferred embodiment, the width 110w of the first opening 110 along the first direction D1 is 1.9 μm to 2.5 μm. In this way, the width 110w of the first opening 110 is sufficiently small without causing loss of the aperture ratio. Moreover, the width 110w of the first opening 110 is large enough to accommodate the first portion 1141 of the data line 114. In this embodiment, the width w1 of the first portion 1141 (or the source electrode) of the data line 114 along the first direction D1 is 1.1 μm to 2.1 μm. In this embodiment, the cross-sectional shape of the first opening 110 along the first direction D1 is wide at the top and narrow at the bottom. In other words, the cross-sectional shape of the first portion 1141 of the data line 114 along the first direction D1 is also wide at the top and narrow at the bottom, but it is not limited to this.

In this embodiment, the shortest distance S1 between the first region 108a of the semiconductor layer 108 and the first opening 110 along the second direction D2 needs to be greater than 0.5 microns. This can ensure that the interlayer dielectric layer 104 can climb to the top of the first region 108 a of the semiconductor layer 108.

The top surface of the first portion 1141 is lower than or equal to the top surface of the interlayer dielectric layer 104. For example, the first portion 1141 has a sidewall portion 1141A and a bottom portion 1141B that are connected to each other. The sidewall portion 1141A and the bottom portion 1141B together form a U-shaped cross-sectional shape. The top surface of the sidewall portion 1141A is lower than or equal to that of the interlayer dielectric layer 104. Top surface. In this way, it is possible to further reduce the risk of light being scattered by the edge of the first portion 1141 of the data line 114 (such as the side wall portion 1141A) and light leakage caused by the relatively bright area of the display screen in the dark state.

In this embodiment, the data line 114 and the drain DE are located in the same film layer. It can also be said that the data line 114 and the drain DE are formed by the same patterning process and are formed by the same conductive material. The invention is not limited to this.

In this embodiment, the pixel structure 10 further includes a flat layer 116, a pixel electrode PE, an insulating layer 118, and a common electrode CM stacked on the interlayer dielectric layer 104 in sequence. The insulating layer 118 has a contact hole TH to expose the drain electrode DE, the pixel electrode PE covers the contact hole TH and the flat layer 116, and the pixel electrode PE is electrically connected to the drain electrode DE of the transistor T through the contact hole TH. The common electrode CM is connected to a common voltage. The pixel electrode PE and the common electrode CM are used to form a storage capacitor of the pixel structure 10. In this embodiment, the pixel electrode PE and the common electrode CM may both be transparent electrodes, but the invention is not limited to this. The material of the transparent electrode includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the foregoing. The material of the insulating layer 118 may include inorganic materials (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), organic materials, or other suitable materials, or the above的组合。 The combination. In this embodiment, the pixel electrode PE has a slit ST, but the invention is not limited to this.

In this embodiment, the pixel structure 10 further includes a first light-shielding layer 120, the first light-shielding layer 120 is located on the substrate 102, and the first light-shielding layer 120 is located on the substrate 102 and the first portion 1141 of the data line 114 (or called Source). The vertical projection of the first opening 110 on the substrate 102 overlaps the vertical projection of the first light shielding layer 120 on the substrate 102, and the vertical projection of the first opening 110 on the substrate 102 is within the vertical projection of the first light shielding layer 120 on the substrate 102. In other words, the vertical projection of the first portion 1141 of the data line 114 on the substrate 102 is within the vertical projection of the first light shielding layer 120 on the substrate 102, so that the first light shielding layer 120 can further reduce the first portion 1141 of the data line 114 Light leaks in the dark state. The material of the first light-shielding layer 120 may include any light-shielding material known to those skilled in the art, such as opaque metal such as molybdenum, molybdenum aluminum molybdenum, or titanium aluminum titanium, or black resin. In other embodiments, the first light shielding layer 120 can also be selected not to be provided.

In this embodiment, the width 120w of the first light shielding layer 120 along the first direction D1 is 2.8 μm to 3.7 μm. In this embodiment, the shortest distance between the first light shielding layer 120 and the bottom of the first opening 110 along the first direction D1 is 0.25 μm to 1 μm. In detail, the shortest distance S2 between the right edge of the bottom of the first opening 110 and the right edge of the first light shielding layer 120 along the first direction D1 is 0.25 μm to 1 μm, and the left edge of the bottom of the first opening 110 The shortest distance S3 between the left edge of the first light-shielding layer 120 and the left edge of the first direction D1 is 0.25 μm to 1 μm. Therefore, one side (such as the right edge or the left edge) of the first part 1141 of the data line 114 can be avoided. ) Of light leakage in the dark state. Moreover, the width of the first light shielding layer 120 along the first direction D1 is sufficiently small without causing loss of aperture ratio.

In this embodiment, the pixel structure 10 may optionally include a second light-shielding layer 122. Therefore, the second light-shielding layer 122 is not shown in FIG. 1, and its outline is indicated by a dashed line in FIG. The second light shielding layer 122 is located on the substrate 102. In detail, the second light-shielding layer 122 is located between the channel region 108c and the substrate 102, and the second light-shielding layer 122, the channel region 108c, and the gate GE partially overlap in the normal direction of the substrate 102, so that the second light-shielding layer 122 The light can be shielded to prevent the channel area 108c from being illuminated by a backlight source (not shown). The material of the second light-shielding layer 122 can be similar to the material of the first light-shielding layer 120, so it will not be repeated here. In other embodiments, the second light-shielding layer 122 can also be selected not to be provided.

FIG. 4 is a schematic cross-sectional view of a pixel structure 10a according to another embodiment of the invention. The pixel structure 10a in FIG. 4 is similar to the pixel structure 10 in FIG. 2. Only the differences between the two are discussed below, and the same or similarities will not be repeated. In this embodiment, the transistor Ta is a bottom gate type transistor, and the gate GEa is located under the semiconductor layer 108. The pixel structure 10a of the present invention is not limited to bottom gate type transistors and top gate type transistors, and can achieve design flexibility.

Figure 5 is a partial cross-sectional image of a pixel structure 10b according to an embodiment of the present invention under a scanning electron microscope (SEM). The pixel structure 10b of Figure 5 corresponds to that of Figure 2. A cross-sectional image of the pixel structure 10 along the cross-sectional line BB', which shows that the first part 1141 of the data line 114 is located in the first opening 110 of the interlayer dielectric layer 104, and the first part of the data line 114 The vertical projection of the portion 1141 on the substrate 102 along the first direction D1 is located within the vertical projection of the first opening 110 on the first substrate 102, thereby preventing light from being scattered by the edge of the first portion 1141 of the data line 114 and leaking light The resulting relatively bright area of the display screen in the dark state. In other words, the dark state light leakage caused by the first portion 1141 of the data line 114 can be avoided, and the light transmittance in the dark state can be reduced. Fig. 6 is a schematic top view of the pixel structure 20 according to the comparative example. Fig. 7 is the cross-sectional image of Fig. 6 along the section line A-A' under a scanning electron microscope (SEM). Please refer to Fig. 6 In FIGS. 5, 6, and 7, the interlayer dielectric layer 204 is disposed on the semiconductor layer 208. The pixel structure 20 of the comparative example is similar to the pixel structure 10b of the present invention in FIG. 5. The difference between the two is: The first part 2141 of the data line 214 of the comparative example climbs along the first direction D1 to the outside of the first opening 210 and is located on the top surface of the interlayer dielectric layer 204. Because the edge of the first part 2141 of the data line 214 is easy Reflecting light causes the problem of light leakage in the dark state, that is, the light transmittance in the dark state is high. The light transmittance of the pixel structure 10b of the present invention in the dark state is about 80%, the light transmittance of the pixel structure 10b of the comparative example in the dark state, in other words, the pixel structure 10b of the present invention is in the dark state When the light transmittance is A, the light transmittance of the pixel structure 20 of the comparative example in the dark state is B, then (BA)/Bx100% is 20%, which shows that the pixel structure 10b of this embodiment The light transmittance in the dark state is low.

In summary, the vertical projection of the first part of the data line of the pixel structure on the substrate along the first direction in an embodiment of the present invention is located within the vertical projection of the first opening on the first substrate, thereby avoiding The light is scattered by the edge of the first part of the data line and the light is leaked, which causes the relatively bright area of the display screen in the dark state. In other words, the dark state light leakage caused by the first part of the data line can be avoided, and the light transmittance in the dark state can be reduced. It is known that the pixel contrast is the ratio of the light transmittance in the bright state and the dark state, and the light transmittance in the dark state is positively correlated with the light leakage in the dark state. Because the light leakage in the dark state is reduced, the pixel structure can be reduced. The pixel contrast has been improved. In addition, the vertical projection of the first opening on the substrate overlaps the vertical projection of the first light shielding layer on the substrate, and the vertical projection of the first opening on the substrate is within the vertical projection of the first light shielding layer on the substrate. In other words, the vertical projection of the first part of the data line on the substrate is within the vertical projection of the first light-shielding layer on the substrate, so that the first light-shielding layer can further reduce the dark-state light leakage of the first part of the data line.

10, 10a, 10b: pixel structure 20: Pixel structure 102: substrate 104: Interlayer dielectric layer 106: Buffer layer 108: semiconductor layer 108a: District 1 108b: District 2 108c: Passage area 110: first opening 110w: width 112: second opening 114: data line 115: gate line 116: flat layer 118: Insulation layer 120: first shading layer 120w: width 122: second shading layer 204: Interlayer dielectric layer 208: Semiconductor layer 210: first opening 214: Data Line 1141: Part One 1141A: side wall 1141B: bottom 2141: Part One A-A’: Sectional line B-B’: Cut line CM: Common electrode D1: First direction D2: second direction DE: Dip pole GE, GEa: Gate GI: Gate insulation layer I-I’: Sectional line II-II’: Sectional line S1: shortest distance S2: shortest distance S3: shortest distance ST: slit T, Ta: Transistor PE: pixel electrode TH: contact hole w1: width w2: width

Read the following detailed description and match the corresponding diagrams to understand many aspects of this disclosure. It should be noted that many features in the drawing are not drawn to actual scale in accordance with the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion. FIG. 1 is a schematic top view of a pixel structure according to an embodiment of the invention. Figure 2 is a schematic cross-sectional view taken along the section line I-I' of Figure 1. Fig. 3 is a schematic cross-sectional view taken along the line II-II' of Fig. 1. FIG. 4 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention. Fig. 5 is a cross-sectional image along the section line B-B' corresponding to the pixel structure of Fig. 2. Fig. 6 is a schematic top view of the pixel structure according to the comparative example. Figure 7 is a cross-sectional image of Figure 6 along the section line A-A' under a scanning electron microscope.

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10: Pixel structure

102: substrate

104: Interlayer dielectric layer

106: Buffer layer

108: semiconductor layer

108a: District 1

108b: District 2

108c: Passage area

110: first opening

110w: width

112: second opening

114: data line

116: flat layer

118: Insulation layer

120: first shading layer

122: second shading layer

1141: Part One

1141A: side wall

1141B: bottom

CM: Common electrode

DE: Dip pole

GE: Gate

GI: Gate insulation layer

I-I’: Sectional line

S2: shortest distance

S3: shortest distance

T: Transistor

PE: pixel electrode

TH: contact hole

w1: width

w2: width

Claims (10)

A pixel structure, including: A substrate; At least one transistor is arranged on the substrate, wherein the transistor has a drain, a gate, a gate insulating layer and a semiconductor layer, and the gate insulating layer is arranged between the gate and the semiconductor layer , And the gate electrode partially overlaps the semiconductor layer; At least one interlayer dielectric layer is disposed on the substrate and covers the gate and the semiconductor layer, wherein the interlayer dielectric layer has a first opening and a second opening, and the semiconductor layer has an adjacent first region And a second region, the first opening overlaps the first region, the second opening overlaps the second region, and a width of the first opening along a first direction is 1.1 micrometers to 2.9 micrometers; and At least one data line is disposed on the substrate, wherein the data line extends along a second direction, the first direction and the second direction intersect, and a first part of the data line is disposed in the first opening , The first part of the data line contacts the first area through the first opening to serve as the source of the transistor, and the first part of the data line is vertically projected on the substrate along the first direction The first opening is located within the vertical projection of the first substrate along the first direction, and the drain is connected to the second region of the semiconductor layer through the second opening. The pixel structure described in claim 1, further including: A first shading layer is located between the substrate and the first part of the data line, the vertical projection of the first opening on the substrate overlaps the vertical projection of the first shading layer on the substrate, and the first The vertical projection of the opening on the substrate is within the vertical projection of the first light shielding layer on the substrate. The pixel structure according to claim 2, wherein the shortest distance between the edge of the first light shielding layer and the edge of the bottom of the first opening along the first direction is 0.25 μm to 1 μm. The pixel structure according to claim 1, wherein the top surface of the first part of the data line is lower than or equal to the top surface of the interlayer insulating layer. The pixel structure according to claim 1, wherein the width is 1.9 μm to 2.5 μm. The pixel structure according to claim 1, wherein the shortest distance between the first region and the first opening of the semiconductor layer along the second direction is greater than 0.5 micrometers. The pixel structure according to claim 1, wherein the gate is located above the semiconductor layer. The pixel structure according to claim 1, wherein the gate is located under the semiconductor layer. The pixel structure according to claim 1, wherein the cross-sectional shape of the first opening along the first direction is wide at the top and narrow at the bottom. The pixel structure according to claim 1, wherein the first part has a side wall and a bottom that are connected to each other, and the side wall and the bottom together form a U-shaped cross-sectional shape along the first direction, and the side wall The top surface of is lower than or equal to the top surface of the interlayer insulating layer.

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