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TW202135244A - 電子封裝件 - Google Patents

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Publication number
TW202135244A
TW202135244A TW109107444A TW109107444A TW202135244A TW 202135244 A TW202135244 A TW 202135244A TW 109107444 A TW109107444 A TW 109107444A TW 109107444 A TW109107444 A TW 109107444A TW 202135244 A TW202135244 A TW 202135244A
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Taiwan
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layer
electronic
electronic components
scope
item
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TW109107444A
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English (en)
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TWI734401B (zh
Inventor
陳麒任
許智勛
潘嘉偉
林長甫
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW109107444A priority Critical patent/TWI734401B/zh
Priority to CN202010175389.9A priority patent/CN113363221B/zh
Priority to US16/876,460 priority patent/US20210280530A1/en
Application granted granted Critical
Publication of TWI734401B publication Critical patent/TWI734401B/zh
Publication of TW202135244A publication Critical patent/TW202135244A/zh

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Abstract

一種電子封裝件，係包括一包含有複數電子元件之多晶片封裝體以及一佈設於該多晶片封裝體上之應力緩衝層，且該應力緩衝層接觸該複數電子元件，使應力平均分散於該應力緩衝層而不會集中於特定區域，避免結構應力集中於該些電子元件之角落處。

Description

電子封裝件
本發明係有關一種封裝結構，尤指一種散熱型電子封裝件。
隨著科技的演進，電子產品需求趨勢朝向異質整合邁進，為此，多晶片封裝結構(MCM/MCP)逐漸興起。
如第1圖所示之多晶片封裝結構1，係將複數半導體晶片11藉由複數銲錫凸塊13結合至一封裝基板10上，並以底膠14包覆該些銲錫凸塊13及該複數半導體晶片11。俾藉由將多顆半導體晶片11封裝成一模組，使其具有較多的I/O數，且可以大幅增加處理器的運算能力，減少訊號傳遞的延遲時間，以應用於高密度線路/高傳輸速度/高疊層數/大尺寸設計之高階產品。
然而，如第1圖所示之多晶片封裝結構1(其圖中省略封裝膠體及散熱件)，隨著功能需求愈來愈多，該半導體晶片11之數量亦愈來愈多，因而該封裝基板10之整體平面封裝面積也愈來愈大，故於高溫時，整體結構會呈笑臉(如圖所示之虛線路徑L1)翹曲狀，而於室溫時，則呈哭臉(如圖所示之虛線路徑L2)翹曲狀，造成該多晶片封裝結構1多次拉伸(如圖所示之箭頭方向X1)或收縮(如圖所示之箭頭方向X2)之變化，以致於 因各該半導體晶片11之間的應力不連續之情況而導致於該半導體晶片11之角落處之應力會過大，致使各該半導體晶片11之間的底膠14之處容易發生斷裂，因而造成產品可靠度不佳及製程良率低的問題。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：多晶片封裝體，係包含有複數電子元件及結合該複數電子元件之包覆層；以及應力緩衝層，係佈設於該多晶片封裝體上以接觸該複數電子元件及該包覆層。
前述之電子封裝件中，該複數電子元件之至少二者係相互分離地配置。
前述之電子封裝件中，該包覆層係形成於任二該電子元件之間。
前述之電子封裝件中，該包覆層係為底膠。
前述之電子封裝件中，該多晶片封裝體復包含有承載及電性連接該複數電子元件之承載結構，且該包覆層形成於該承載結構上。例如，該承載結構係為無核心層形式線路結構。
前述之電子封裝件中，該多晶片封裝體復包含有包覆該複數電子元件及該包覆層之封裝層。例如，該應力緩衝層復接觸該封裝層。或者，該電子元件之一表面係齊平該封裝層之上表面。
前述之電子封裝件中，復包括結合至該複數電子元件上之散熱件。例如，該散熱件係藉由散熱材結合至該應力緩衝層上。或者，該應力緩衝層係設於該複數電子元件與該散熱件之間。
前述之電子封裝件中，該應力緩衝層係為金屬層。
由上可知，本發明之電子封裝件主要藉由該應力緩衝層佈設於該多晶片封裝體上，以連接各該電子元件之非作用面及包覆層之表面，使應力平均分散於該應力緩衝層而不會集中於特定區域，故相較於習知技術，本發明之電子封裝件能有效避免結構應力集中於該些電子元件之角落處，進而避免該些電子元件或包覆層發生碎裂而導致可靠性不佳及製程良率低之問題。
1:多晶片封裝結構
10,3:封裝基板
11:半導體晶片
13:銲錫凸塊
14,260:底膠
2:電子封裝件
2a:多晶片封裝體
20:承載結構
20a:第一側
20b:第二側
200:絕緣層
201:線路層
21,21’:電子元件
21a:作用面
21b:非作用面
21c:側面
210:電極墊
211:導電凸塊
212:包覆層
212a:上表面
22:封裝層
22a:第一表面
22b:第二表面
23:散熱件
230:散熱體
231:支撐腳
24:應力緩衝層
25:散熱材
26:導電體
27:黏著層
30:導電元件
L1,L2:虛線路徑
X1,X2:箭頭方向
第1圖係為習知多晶片封裝結構之剖視示意圖。
第2圖係為本發明之電子封裝件之剖視示意圖。
第2’圖係為第2圖之局部放大圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀， 並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「下」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2及2’圖係為本發明之電子封裝件2之剖面示意圖。如第2及2’圖所示，所述之電子封裝件2係包括：一多晶片封裝體2a(其包括一承載結構20、複數電子元件21,21’及封裝層22)、一應力緩衝層24、一散熱材25以及一散熱件23。
所述之承載結構20係為載板形式，其例如為具有核心層之封裝基板、無核心層(coreless)形式線路結構、具導電矽穿孔(Through-silicon via，簡稱TSV)之矽中介板(Through Silicon interposer，簡稱TSI)或其它板型。
於本實施例中，該承載結構20係為無核心層形式線路結構，其包含至少一絕緣層200及至少一結合該絕緣層200之線路層201，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該承載結構20亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等，並不限於上述。
再者，該承載結構20係具有相對之第一側20a與第二側20b，且於其第二側20b可形成複數導電體26，以供該電子封裝件2可藉由該些導 電體26接置一封裝基板3，並可由底膠260包覆該些導電體26。或者，該電子封裝件2可藉由該些導電體26接置一如電路板之電子裝置(圖略)。例如，該導電體26可為如銅柱之金屬柱、包覆有絕緣塊之金屬凸塊、銲球(solder ball)、具有核心銅球(Cu core ball)之銲球或其它導電構造等。
又，該承載結構20之載板製程方式繁多，例如，可採用晶圓製程製作線路層201，透過化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層200；或者，可採用一般非晶圓製程方式形成線路層201，即採用成本較低之高分子介電材作為絕緣層200，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。
所述之複數電子元件21,21’係相互分離地配置於該承載結構20之第一側20a，且該電子元件21,21’係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該些電子元件21,21’係為半導體晶片，其具有相對之作用面21a與非作用面21b，並使該作用面21a之電極墊210藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊211以覆晶方式設於該承載結構20之第一側20a之線路層201上並電性連接該線路層201，且以如底膠之包覆層212包覆該些導電凸塊211；或者，該電子元件21,21’可藉由複數銲線(圖未示)以打線方式電性連接該承載結構20之線路層201；亦或，該電子元件21,21’可直接接觸該承載結構20之線路層201。因此，可於 該承載結構20上接置所需類型及數量之電子元件，以提升其電性功能，且有關電子元件21,21’電性連接承載結構20之方式繁多，並不限於上述。
再者，該包覆層212復形成於各該電子元件21,21’之間，如沿該電子元件21,21’之側面21c延伸佈設，且各該電子元件21,21’之非作用面21b齊平該包覆層212之上表面212a。
所述之封裝層22係形成於該承載結構20之第一側20a上以包覆該電子元件21,21’與該包覆層212。
於本實施例中，該封裝層22係具有相對之第一表面22a與第二表面22b，並以該第一表面22a結合該承載結構20之第一側20a，且該電子元件21之非作用面21b齊平該封裝層22之第二表面22b，以令該些電子元件21外露於該封裝層22之第二表面22b。
再者，形成該封裝層22之材質係為絕緣材，如聚醯亞胺(PI)、環氧樹脂(epoxy)之封裝膠體或封裝材，其可用模壓(molding)、壓合(lamination)或塗佈(coating)之方式形成之。
所述之應力緩衝層24係佈設於該多晶片封裝體2a上以接觸該複數電子元件21,21’及該包覆層212。
於本實施例中，該應力緩衝層24係為金屬層，如銅，且以濺鍍(Sputter)或其它方式形成於各該電子元件21,21’之非作用面21b、該包覆層212之上表面212a及該封裝層22之第二表面22b上，以接觸該複數電子元件21,21’、該包覆層212及該封裝層22。
再者，以濺鍍方式形成該應力緩衝層24，不僅可降低製作成本，且製程簡單，因而易於大量製作。
所述之散熱材25係佈設於該應力緩衝層24上，且該散熱材25係為導熱介面材(Thermal Interface Material，簡稱TIM)，如高導熱金屬膠材。
所述之散熱件23係藉由該散熱材25結合至該應力緩衝層24上，以令該散熱件23、散熱材25與該應力緩衝層24作為該些電子元件21,21’之散熱機制。
於本實施例中，該散熱件23係具有一散熱體230與複數設於該散熱體230下側之支撐腳231，該散熱體230係為散熱片型式，並以下側接觸該散熱材25，且該支撐腳231係藉由黏著層27結合於該封裝基板3上或承載結構20之第一側20a上。應可理解地，有關該散熱件23之態樣繁多，如片體型(無支撐腳231)，並不限於上述。
再者，該應力緩衝層24係設於該複數電子元件21,21’與該散熱件23之間。
另外，於後續製程中，可植設複數導電元件30於該封裝基板3下側，以藉由該些導電元件30接置一如電路板之電子裝置(圖略)。例如，該導電元件30可為如銅柱之金屬柱、包覆有絕緣塊之金屬凸塊、銲球(solder ball)、具有核心銅球(Cu core ball)之銲球或其它導電構造等。
綜上所述，本發明之電子封裝件2，主要藉由該應力緩衝層24佈設於該多晶片封裝體2a上，以連接各該電子元件21,21’之非作用面21b及包覆層212之上表面212a，使應力平均分散於該應力緩衝層24而不會集中於特定區域，故相較於習知技術，本發明之電子封裝件2於該承載結構20之整體平面封裝面積愈大時，能有效避免結構應力集中於該些電子元件 21,21’之角落處，進而避免該些電子元件21,21’或包覆層212發生碎裂而導致可靠性不佳及製程良率低之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:多晶片封裝體
20:承載結構
20a:第一側
20b:第二側
200:絕緣層
201:線路層
21,21’:電子元件
21a:作用面
21b:非作用面
21c:側面
210:電極墊
211:導電凸塊
212:包覆層
212a:上表面
23:散熱件
24:應力緩衝層
25:散熱材

Claims (13)

  1. 一種電子封裝件，係包括：
    多晶片封裝體，係包含有複數電子元件及結合該複數電子元件之包覆層；以及
    應力緩衝層，係佈設於該多晶片封裝體上以接觸該複數電子元件及該包覆層。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該複數電子元件之至少二者係相互分離地配置。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層係形成於任二該電子元件之間。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層係為底膠。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該多晶片封裝體復包含有承載及電性連接該複數電子元件之承載結構，且該包覆層形成於該承載結構上。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該承載結構係為無核心層形式線路結構。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該多晶片封裝體復包含有包覆該複數電子元件及該包覆層之封裝層。
  8. 如申請專利範圍第7項所述之電子封裝件，其中，該應力緩衝層復接觸該封裝層。
  9. 如申請專利範圍第7項所述之電子封裝件，其中，該電子元件之一表面係齊平該封裝層之上表面。
  10. 如申請專利範圍第1項所述之電子封裝件，復包括結合至該複數電子元件上之散熱件。
  11. 如申請專利範圍第10項所述之電子封裝件，其中，該散熱件係藉由散熱材結合至該應力緩衝層上。
  12. 如申請專利範圍第10項所述之電子封裝件，其中，該應力緩衝層係設於該複數電子元件與該散熱件之間。
  13. 如申請專利範圍第1項所述之電子封裝件，其中，該應力緩衝層係為金屬層。
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