TW202133388A - Semiconductor storage device - Google Patents

Abstract

The present invention provides a semiconductor memory device capable of suppressing leakage current during data writing. In the semiconductor memory device 1, a plurality of anti-fuse memories M are arranged in a matrix. The anti-fuse memory M has a memory capacitor 10 and a MOS transistor 20. In the memory capacitor 10, the memory gate electrode 10a is connected to the source region 20b of the MOS transistor 20, and the diffusion region 10b is connected to the source line SL of each row. The gate electrode 20a of the MOS transistor 20 is connected to the word line WL of each row, and the drain region 20c is connected to the bit line BL of each column, so that the independently applied voltage is controlled.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device.

There is known an anti-fuse memory in which data can be written only once (for example, refer to Patent Document 1). In the anti-fuse memory, data is written by electrically insulating and destroying the insulating film of the memory capacitor, that is, the insulating film of the memory gate.

In Patent Document 1, a semiconductor memory device is described in which a plurality of anti-melting elements including an N-type MOS (Metal Oxide Semiconductor) transistor (rectifier element) connected to a diode and a memory capacitor is described. The silk memory is arranged in a matrix. The memory capacitor is a structure in which the memory gate insulating film and the memory gate electrode, which are insulated by the voltage difference between the word line and the bit line, are laminated on the active area. Corresponding to each column of the anti-fuse memory, the word line corresponds to each row with a bit line. The memory capacitor of each anti-fuse memory is connected to the bit line in the diffusion area arranged at one end of the active area, and the source area of the MOS transistor is connected to the gate electrode of the memory. In addition, the gate electrode and the drain region of the MOS transistor system are connected to each other and the diode is connected, and the gate electrode and the drain region are connected to the word line.

In the above-mentioned semiconductor memory device, when data is written into a specific anti-fuse memory in the anti-fuse memory arranged in a matrix, the bit line connected to the anti-fuse memory for writing the data is applied A voltage of 0 V is applied, and a voltage of 5 V is applied to the word line. Apply voltages of 3 V and 0 V to the other bit lines and word lines, respectively. In the anti-fuse memory through which data is written, a voltage difference that breaks the insulation of the memory gate insulating film is generated between the memory gate electrode and the diffusion region, and in the other anti-fuse memory, Set the voltage difference at which the insulating film of the memory gate will not be damaged. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2016/136604

[The problem to be solved by the invention]

In the anti-fuse memory structured as described above, the anti-fuse memory for writing data (hereinafter referred to as the selective anti-fuse memory) is connected to the same character line as the anti-fuse for not writing data In the memory (hereinafter referred to as non-selected anti-fuse memory), it is the same as the selected anti-fuse memory. The gate electrode and drain area of the MOS transistor are applied with 5 V for writing from the word line Voltage. As a result, in the non-selective anti-fuse memory, the MOS transistor is also turned on, and a voltage of 5 V is applied to the memory gate electrode of the memory capacitor. On the bit line connected to the non-selective anti-fuse memory, a voltage of 3 V is applied so that the memory gate insulating film is not damaged by the insulation, but about 2 V is generated between the memory gate electrode and the diffusion region Voltage difference. As a result, when the memory gate insulating film of the non-selective anti-fuse memory has been damaged by insulation, there is a problem that leakage current flows from the word line to the bit line through the non-selected anti-fuse memory.

The present invention was completed in view of the above circumstances, and its object is to provide a semiconductor memory device that can suppress leakage current during data writing. [Technical means to solve the problem]

The semiconductor memory device of the present invention includes: a memory array, which is arranged in a matrix with a plurality of anti-fuse memories, and the anti-fuse memory includes: a memory capacitor having an active area and formed on the active area The memory gate insulating film, the memory gate electrode formed on the above-mentioned memory gate insulating film, and the diffusion region formed in the above-mentioned active region; and a MOS transistor, which has a gate electrode, a source region, and The drain region, and the source region is connected to the gate electrode of the memory; a plurality of bit lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected in the row The above-mentioned drain region, and a bit line connected to the anti-fuse memory of the writing target in the above-mentioned plurality of anti-fuse memories, apply a voltage that breaks the insulation of the above-mentioned memory gate insulating film, namely The first selection column voltage; a plurality of word lines, which extend in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the gate electrodes in the rows, and are placed in the writing object A word line connected to the anti-fuse memory is applied with the voltage that sets the MOS transistor to the on-state, that is, the first selected row voltage; and a plurality of source lines, which are stored in accordance with the above-mentioned plurality of anti-fuse memory Each row of the body extends in the row direction, and is respectively connected to the above-mentioned diffusion region in the row, and is connected to a source line of the anti-fuse memory of the above-mentioned writing object. The above-mentioned MOS transistor is an N-type In this case, apply a first selected source line voltage higher than the well voltage applied to the well in which the active region is formed. When the MOS transistor is P-type, apply a first selected source line voltage lower than the well voltage , And to the source line of the anti-fuse memory that is not connected to the write target, apply the first non-selected source line voltage that is the middle voltage between the first selected source line voltage and the first selected column voltage .

The semiconductor memory device of the present invention includes: a memory array, which is arranged in a matrix with a plurality of anti-fuse memories, and the anti-fuse memory includes: a memory capacitor having an active area and formed on the active area The memory gate insulating film, the memory gate electrode formed on the above-mentioned memory gate insulating film, and the diffusion region formed in the above-mentioned active region; and a MOS transistor, which has a gate electrode, a source region, and The drain region, and the source region is connected to the gate electrode of the memory; a plurality of bit lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected in the row The above-mentioned drain region, and a bit line connected to the anti-fuse memory of the writing target in the above-mentioned plurality of anti-fuse memories, apply a voltage that breaks the insulation of the above-mentioned memory gate insulating film, namely The first selection column voltage; a plurality of word lines, which are arranged in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the gate electrodes in the rows, and in the writing object A word line connected to the anti-fuse memory is applied with the voltage that sets the MOS transistor to the on-state, that is, the first selected row voltage; and a plurality of source lines, which are stored in accordance with the above-mentioned plurality of anti-fuse memory Each row of the body extends along the row direction, and is respectively connected to the above-mentioned diffusion region in the row, and is connected to a source line of the anti-fuse memory of the above-mentioned writing object. The above-mentioned MOS transistor is an N-type In this case, the first selected source line voltage above the well voltage applied to the well where the active region is formed is applied, and when the MOS transistor is P-type, the first selected source line below the well voltage is applied The source line of the anti-fuse memory that is not connected to the above-mentioned writing object is set to a floating state.

The semiconductor memory device of the present invention includes: a memory array, which is arranged in a matrix with a plurality of anti-fuse memories, and the anti-fuse memory includes: a memory capacitor having an active area and formed on the active area The memory gate insulating film, the memory gate electrode formed on the above-mentioned memory gate insulating film, and the diffusion region formed in the above-mentioned active region; and a MOS transistor, which has a gate electrode, a source region, and The drain region, and the source region is connected to the gate electrode of the memory; a plurality of bit lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected in the row The above-mentioned drain region; a plurality of character lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned gate electrodes in the rows; a plurality of source lines, which The rows of the plurality of anti-fuse memories extend along the row direction, and are respectively connected to the above-mentioned diffusion regions in the rows; bit line drivers, which anti-fuse the above-mentioned plurality of bit lines among the above-mentioned plurality of bit lines. A bit line connected to the anti-fuse memory of the writing target in the silk memory is applied with a voltage that destroys the insulation of the above-mentioned memory gate insulating film, that is, the first selected column voltage; the word line driver is opposite to Among the plurality of word lines, one of the word lines connected to the anti-fuse memory of the writing target is applied with a voltage that turns the MOS transistor into a conductive state, that is, the first selected row voltage; and a source A line driver, which applies to one source line connected to the anti-fuse memory of the writing target among the plurality of source lines, when the MOS transistor is N-type, the active region is formed The first selected source line voltage above the well voltage to which the well is applied, and when the MOS transistor is P-type, the first selected source line voltage below the well voltage is applied, and the opposite of the above writing target The unconnected source line of the fuse memory is applied with an intermediate voltage between the first selected source line voltage and the first selected column voltage, that is, the first non-selected source line voltage.

The semiconductor memory device of the present invention includes: a memory array, which is arranged in a matrix with a plurality of anti-fuse memories, and the anti-fuse memory includes: a memory capacitor having an active area and formed on the active area The memory gate insulating film, the memory gate electrode formed on the above-mentioned memory gate insulating film, and the diffusion region formed in the above-mentioned active region; and a MOS transistor, which has a gate electrode, a source region, and The drain region, and the source region is connected to the gate electrode of the memory; a plurality of bit lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected in the row The above-mentioned drain region; a plurality of character lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned gate electrodes in the rows; a plurality of source lines, which The rows of the plurality of anti-fuse memories extend along the row direction, and are respectively connected to the above-mentioned diffusion regions in the rows; bit line drivers, which anti-fuse the above-mentioned plurality of bit lines among the above-mentioned plurality of bit lines. A bit line connected to the anti-fuse memory of the writing target in the silk memory is applied with a voltage that destroys the insulation of the above-mentioned memory gate insulating film, that is, the first selected column voltage; the word line driver is opposite to Among the plurality of word lines, one of the word lines connected to the anti-fuse memory of the writing target is applied with a voltage that turns the MOS transistor into a conductive state, that is, the first selected row voltage; and a source A line driver that applies to one source line connected to the anti-fuse memory of the writing target among the plurality of source lines, when the MOS transistor is N-type, and the active region is formed The first selected source line voltage above the well voltage to which the well is applied, and when the MOS transistor is P-type, the first selected source line voltage below the well voltage is applied, and the above write target The unconnected source line of the anti-fuse memory is set to a floating state. [Effects of Invention]

According to the present invention, to the source line that is not connected to the anti-fuse memory of the writing target, the first selected source line voltage applied to the source line that is connected to the anti-fuse memory of the writing target, and the pair The intermediate voltage between the first selected column voltage applied to the bit line of the write target anti-fuse memory is the first non-selected source line voltage, or the write target anti-fuse memory is not connected The source line is set to a floating state, which can suppress the leakage current of the anti-fuse memory.

[First Embodiment] In FIG. 1, the semiconductor memory device 1 includes a memory array CA, a bit line BL, a word line WL, and a source line SL. In the memory array CA, a plurality of anti-fuse memories (memory cells) M are arranged in a matrix. The bit line BL is arranged corresponding to each column of the anti-fuse memory M, and the word line WL and the source line SL are arranged corresponding to each row of the anti-fuse memory M. That is, the anti-fuse memories M arranged in the column direction share one bit line BL, and the anti-fuse memories M arranged in the row direction share one word line WL and one source line SL.

In addition, in the following, in the case of distinguishing each anti-fuse memory M, i and j are set to 1, 2, 3..., and the i-th row and j-th column are regarded as the anti-fuse memory Mij illustrate. In addition, the case where the word line WL and the source line SL are classified into specific rows, and the i-th row is described as the word line WLi and the source line SLi. The same applies to the bit line BL. When it is classified into a specific row, the j-th row is described as the bit line BLj.

Furthermore, in the case of distinguishing between the antifuse memory M which is the object of data writing and reading, and the antifuse memory M which is not the object, the former is called the selective antifuse memory M, and the The latter is called non-selective anti-fuse memory M description.

The anti-fuse memory M has the same structure as any one, and has a memory capacitor 10 and a MOS transistor 20 respectively. Each word line WL and each source line SL are respectively connected to each anti-fuse memory M in the corresponding row. Each bit line BL is connected to each anti-fuse memory M in the corresponding column. Therefore, the anti-fuse memory Mij in the i-th row and the j-th column is connected to the word line WLi, the source line SLi, and the bit line BLj, respectively. In addition, as described later, the bit line BL extends in the column direction, and the word line WL and the source line SL extend in the row direction and are orthogonal to each other.

In addition, the semiconductor memory device 1 includes a row selection circuit 25, a column selection circuit 26, and a sense amplifier 27. The bit line BL is connected to the column selection circuit 26 and the sense amplifier 27, respectively, and the word line WL and the source line SL are connected to the row selection circuit 25, respectively.

The anti-fuse memory M connects the gate electrode 20a of the MOS transistor 20 to the word line WL, the source region 20b is connected to the memory gate electrode 10a of the memory capacitor 10, and the drain region 20c is connected to the position Element line BL. In addition, the diffusion region 10b of the memory capacitor 10 is connected to the source line SL. The anti-fuse memory M uses the row selection circuit 25 and the column selection circuit 26 to control the voltages of the connected bit line BL, source line SL, and word line WL, thereby performing data writing and reading.

The memory capacitor 10 has a memory gate electrode 10a, a diffusion region 10b, and a memory gate insulating film 10c (refer to FIG. 3), and the memory gate insulating film 10c is non-volatilely maintained by the presence or absence of insulation breakdown of the memory gate insulating film 10c 1-bit data. That is, the memory capacitor 10 is an insulating state in which the memory gate insulating film 10c is not dielectrically destroyed but the memory gate electrode 10a and the diffusion region 10b are electrically insulated from each other, and the memory gate insulating film 10c is insulated from the memory gate insulating film 10c. The short circuit state that the memory gate electrode 10a and the diffusion region 10b are electrically short-circuited corresponds to "0" and "1" of the 1-bit data. In addition, in this example, the case where the insulation of the memory gate insulating film 10c is broken and the state is short-circuited is referred to as the writing of data in the anti-fuse memory M. In addition, data reading means detecting that the memory capacitor 10 is in an insulated state or a short-circuit state.

When data is written and read, the row selection circuit 25 applies voltage to the word line WL and the source line SL, and the column selection circuit 26 applies voltage to the bit line BL. As voltages applied to the word line WL, there are a first selected row voltage and a first non-selected row voltage during writing, and a second selected row voltage and a second non-selected row voltage during reading. In addition, as the voltage applied to the source line SL, there are a first source line voltage at the time of writing and a second source line voltage at the time of reading. As the voltage applied to the bit line BL, there are the first selected column voltage and the first non-selected column voltage during writing, and the second selected column voltage and the second non-selected column voltage during reading.

Therefore, as shown in FIG. 2, the row selection circuit 25 is provided with various voltages supplied from the power supply PS during writing, and selectively applies the first selected row voltage and the first non-selected row voltage to the word line WL. The cell line driver 25a, and the source line driver 25b that applies the first source line voltage to the source line SL, the column selection circuit 26 is provided with various voltages supplied from the power supply PS during writing, and applies to the bit line BL The bit line driver 26a selectively applies the first selected column voltage and the first non-selected column voltage. In this example, the voltage of the first selected column is 5 V, the voltage of the first selected row is 6 V, the voltage of the first non-selected row, the voltage of the first non-selected column, and the voltage of the first source line are 0 V. These 3 This voltage is supplied as a writing voltage from the power supply section PS to the word line driver 25a, the source line driver 25b, and the bit line driver 26a. In addition, in the well S2 (refer to FIG. 3), at the time of writing, 0 V from the power supply unit PS is supplied by the well voltage applying unit 28, and the voltage of the well S2 is set to 0 V. The details of these voltages will be described later.

In addition, the above-mentioned power supply unit PS has, for example, a plurality of voltage generating circuits that generate voltages for writing, and outputs the voltages generated by the respective voltage generating circuits. In this example, there are three voltage generating circuits that generate 0 V, 5 V, and 6 V. The voltage generating circuits only need to be set according to the required voltage for writing. In addition, in fact, the voltage that should be applied to the word line WL, source line SL, bit line BL, and well S2 during reading, and the voltage used to drive the row selection circuit 25 itself, the column selection circuit 26, and the well voltage respectively The driving voltage of the application unit 28 itself is supplied from the power supply unit PS to the row selection circuit 25, the column selection circuit 26, and the well voltage application unit 28, but their illustrations are omitted in FIG. 2.

When reading data, pre-charging is used. The sense amplifier 27 obtains 1-bit data written into the anti-fuse memory M based on the change in the potential of the bit line BL pre-charged to the second selected column voltage. For example, the sense amplifier 27 detects whether the power of the bit line BL is lower than a certain threshold potential within a certain period of time. In addition, in this example, the pre-charge method is used for data reading, but the data reading method is not particularly limited.

FIG. 3 shows an example of the cross-sectional structure of the anti-fuse memory M. In addition, the anti-fuse memories M adjacent to each other in the column direction are arranged line-symmetrically with respect to the row direction. Therefore, the anti-fuse memory M has the configuration shown in FIG. 3 and the configuration that is line-symmetrical with it. The anti-fuse memory M is formed in the P-type well S2 on the semiconductor substrate S1. In the P-type well S2, a first active region 31 and a second active region 32 separated in the column direction by an element separation film IL formed of an insulating material are provided.

In the first active area 31, a memory capacitor 10 is formed. In the first active region 31, a diffusion region 10b doped with an N-type dopant at a high concentration is formed at a specific interval from the element isolation film IL. As described later, the diffusion region 10b functions as a source line SL. A memory gate insulating film 10c is formed on the first active region 31 between the element isolation film IL and the diffusion region 10b. A memory gate electrode 10a is provided across each upper surface of the memory gate insulating film 10c and the element separation film IL. On both sidewalls of the memory gate electrode 10a, sidewalls SW1 formed of insulating materials are provided.

In the second active region 32, a MOS transistor 20 is formed. In the second active region 32, a source region 20b doped with an N-type dopant at a high concentration is formed adjacent to the element isolation film IL. In addition, in the second active region 32, a drain region 20c doped with a high concentration of N-type dopant is formed at a specific interval from the source region 20b. A gate insulating film 20d is formed on the second active region 32 between the source region 20b and the drain region 20c, and a gate electrode 20a is formed on the gate insulating film 20d. As described later, the gate electrode 20a functions as a word line WL. On both sidewalls of the gate electrode 20a, sidewalls SW2 formed of insulating materials are provided. In order to prevent insulation breakdown during data writing, the gate insulating film 20d has a thickness that is determined according to the first selected row voltage and is set to be larger than that of the memory gate insulating film 10c.

A contact point C1 is provided across the source region 20b of the MOS transistor 20 and the memory gate electrode 10a of the memory capacitor 10. Through the contact C1, the memory gate electrode 10a of the memory capacitor 10 and the source region 20b of the MOS transistor 20 are connected. It is also possible to provide contact points on the memory gate electrode 10a and the source region 20b respectively, and connect the contact points with wires instead of connecting the memory gate electrode 10a and the source region 20b through the contact point C1.

A contact point C2 is provided in the drain region 20c, and the contact point C2 is connected to the bit line BL including the metal wiring layer provided on the upper layer of the gate electrode 20a. In this example, the contact C2 includes a contact C2a formed on the same layer as the contact C1, and a contact C2b formed on the upper portion of the contact C2a. It is also possible to form the contact C2 with one contact. The bit line BL extends along the column direction. The memory gate electrode 10a, the gate electrode 20a, the contact point C1, the contact point C2, and the bit line BL are covered with an interlayer insulating film. The memory gate electrode 10a of the memory capacitor 10 and the gate electrode 20a of the MOS transistor 20 are wirings of the same wiring layer (same layer) formed in the same step.

FIG. 4 shows an example of the planar layout of the anti-fuse memory M. A plurality of anti-fuse memories M are arranged in a matrix to form a memory array CA. The arrangement of the elements of the anti-fuse memory M adjacent in the column direction is line-symmetrical with respect to the row direction as described above. In addition, the configuration of each element of the anti-fuse memory M in each row is the same.

A plurality of first active regions 31 extending in the row direction are formed in the well S2. The first active region 31 is doped with an N-type dopant at a high concentration to form a source line SL. A contact point C3 is formed on the first active region 31 at the end of the memory array, and the source line SL is connected to the row selection circuit 25 via the contact point C3, metal wiring (not shown), etc., and is given the first source line voltage, The second source line voltage. The source line SL extends in the row direction and is shared by adjacent anti-fuse memories M in the column direction.

In the well S2 between the first active regions 31 adjacent to each other, a plurality of rectangular second active regions 32 long in the column direction are arranged along the row direction with specific intervals. The second active area 32 is integrated with the anti-fuse memory M adjacent in the column direction.

The memory gate electrode 10 a of the memory capacitor 10 is formed in a rectangular shape long in the column direction, and one end thereof extends into the first active region 31. The other end is located between the first active area 31 and the second active area 32, but it may also extend into the second active area 32. The contact point C1 is formed across the memory gate electrode 10 a and the second active region 32, and the memory gate electrode 10 a is electrically connected to the source region 20 b of the MOS transistor 20 provided in the second active region 32.

As described above, in the memory capacitor 10, one end of the memory gate electrode 10 a extends to the first active region 31, and the gate edge on the one end side is arranged on the first active region 31. The edge of the gate becomes the shape of itself or its corners being bent or turned. Therefore, when the first selected column voltage is applied to the memory gate electrode 10a, the electric field in the gate edge at one end side of the memory gate electrode 10a becomes stronger, which promotes the insulation breakdown of the memory gate insulating film 10c . Therefore, this configuration can reduce the voltage of the first selected column. In addition, when the memory capacitor is a transistor type capacitor, since the memory gate electrode passes through the active area, only the straight part of the memory gate electrode is arranged on the active area, and there is no bending or turning shape. The edge of the gate.

In addition, as described above, one end side of the memory gate electrode 10 a is a gate edge disposed on the first active region 31 and does not pass through the first active region 31. With respect to the layout where one end side of the memory gate electrode passes through the first active area, as shown in this example, the gate edge on one end side of the memory gate electrode 10a is arranged on the first active area 31 in the layout , The cell size of the anti-fuse memory M becomes smaller. In addition, in the case of a layout where the gate edge on one end side of the memory gate electrode 10a is arranged on the first active area 31, the diffusion area of a memory capacitor 10 can be set as a diffusion area 10b, and only 1 Only one contact point for supplying power to the diffusion region 10b functioning as the source line SL can reduce the number of contact points per cell and reduce the cell size of the anti-fuse memory M.

As wirings shared by the anti-fuse memories M arranged in the row direction, word lines WL extending in the row direction are provided for each row. Each word line WL is arranged to cross the second active region 32 in the row direction. The portion on the second active region 32 of the word line WL becomes the gate electrode 20a of the MOS transistor 20. A contact C4 is formed on the word line WL at the end of the memory array, and the word line WL is connected to the row selection circuit 25 via the contact C4, metal wiring (not shown), etc., and is given the first selected row voltage and the first Non-selected row voltage, second selected row voltage, second non-selected row voltage.

A contact point C2 is formed in the center of the second active area 32 in the column direction. The contact C2 is shared by adjacent anti-fuse memories M in the column direction. As wiring shared by the anti-fuse memories M arranged in the column direction, bit lines BL are provided for each column. The bit line BL extends in the column direction and is orthogonal to the word line WL and the source line SL. The bit line BL is connected to the drain region 20c of the MOS transistor 20 provided in the second active region 32 through the contact C2. The bit line BL is connected to the column selection circuit 26, and is provided with a first selected column voltage, a first non-selected column voltage, a second selected column voltage, and a second non-selected column voltage.

In the following, the writing and reading of the above-mentioned data will be described. When an anti-fuse memory M is selected and data is written to the anti-fuse memory M, the first selected row voltage is applied to the selected anti-fuse memory M to be connected to become the word of the selected word line The cell line WL, and the first non-selected row voltage is applied to the other non-selected word lines WL. In addition, the first selected column voltage is applied to the bit line BL which is the selected bit line connected to the selective antifuse memory M, and the first non-selected column is applied to the other bit lines BL which become non-selected bit lines Voltage. Furthermore, the first source line voltage is applied to any one of the source line SL that becomes the selected source line and the other source line SL that becomes the non-selected source line connected to the selective anti-fuse memory M .

The first selected row voltage is a gate voltage that can set the MOS transistor 20 to which the first selected column voltage is applied as the drain voltage to the ON state, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20. The first non-selected row voltage is the gate voltage at which the MOS transistor 20 is turned off.

The first selected column voltage and the first non-selected column voltage are applied as the drain voltage of the MOS transistor 20. The voltage of the first selected column is set to cause insulation breakdown of the memory gate insulating film 10c between the memory gate electrode 10a to which the voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first source line voltage is applied The voltage of the voltage difference. The first selected column voltage is set to be higher than the first source line voltage.

The first non-selected column voltage is set to be the same as the first non-selected column voltage in order to prevent the insulation breakdown of the memory gate insulating film 10c and prevent leakage current from flowing from the bit line BL to the source line SL through the non-selected anti-fuse memory M. The source line voltage is the same.

In this example, the voltage of the first selected column is 5 V, and the voltage of the first selected row is 6 V. In addition, the first non-selected row voltage, the first non-selected column voltage, and the first source line voltage are the same as the well voltage (potential) of 0V.

In the selective anti-fuse memory M, the first selected row voltage from the word line WL is applied to the gate electrode 20a, and the first selected column voltage from the bit line BL is applied to the drain region 20c. Thereby, the MOS transistor 20 is turned on, and the first selected column voltage of the bit line BL is applied to the memory gate electrode 10a via the MOS transistor 20. In addition, the first source line voltage is applied to the diffusion region 10b of the memory capacitor 10 from the source line SL.

In this way, in the selected anti-fuse memory M, because the first selected column voltage (=5 V) is applied to the memory gate electrode 10a of the memory capacitor 10, and the first source line voltage (=0 V) Since it is applied to the diffusion region 10b, a channel (not shown) is formed on the surface of the first active region 31 directly below the memory gate electrode 10a and becomes a conductive state, and the channel potential is the same as the potential of the source line SL. Thereby, in the selective anti-fuse memory M, since the potential difference between the channel and the memory gate electrode 10a is 5 V, the memory gate insulating film 10c under the memory gate electrode 10a is dielectrically damaged. In this way, the memory gate electrode 10a and the diffusion region 10b become a low-resistance conduction state through the channel, and become a state where data is written.

For example, in the case of writing data into the anti-fuse memory M11, as shown in Figure 5, set the word line WL1 to the first selected row voltage (=6 V), and set the word lines WL2, WL3... .. Set the first non-selected row voltage (=0 V), set the bit line BL1 to the first selected column voltage (=5 V), set the bit lines BL2, BL3... 1 Non-selected column voltage (=0 V).

6 V is applied to the gate electrode 20a of the MOS transistor 20 of the anti-fuse memory M11 from the word line WL1, and 5 V is applied to the drain region 20c from the bit line BL1. Thereby, the MOS transistor 20 is turned on, and the 5 V applied to the drain region 20c is applied to the memory gate electrode 10a via the source region 20b of the MOS transistor 20.

In the anti-fuse memory M11, the diffusion region 10b of the memory capacitor 10 is set to the first source line voltage (=0 V) of the source line SL1. As a result, in the anti-fuse memory M11, as described above, the channel between the memory gate electrode 10a and the first active region 31 formed directly below the memory gate electrode 10a generates a memory The voltage difference of 5 V for the insulation breakdown of the body gate insulating film 10c. As a result, the memory gate insulating film 10c is dielectrically broken, the memory capacitor 10 is in a short-circuit state, and data is written in the anti-fuse memory M11.

On the other hand, in the non-selected anti-fuse memory M, the first non-selected row voltage is applied to the gate electrode 20a from the word line WL, and the MOS transistor 20 is turned off, or from the bit line BL. Either or both of the first non-selected row voltages are applied to the drain region 20c of the MOS transistor 20.

In the former case, the voltage from the bit line BL is not applied to the memory gate electrode 10a by the MOS transistor 20, and in the latter case, it is applied to the first non-selection of the memory gate electrode 10a via the MOS transistor 20 The column voltage is the same as the first source line voltage applied from the source line SL to the diffusion region 10b. Therefore, in either case, in the non-selective anti-fuse memory M, no insulation failure occurs between the memory gate electrode 10a and the first active region 31 directly below it. Due to the voltage difference, the memory gate insulating film 10c is not damaged by insulation and remains in an insulated state, maintaining a state where no data has been written. In addition, leakage current is prevented from flowing from the bit line BL to the source line SL via the non-selective anti-fuse memory M.

Hereinafter, (A) will describe the non-selected anti-fuse memory M in the same column as the selected anti-fuse memory M, and (B) the non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M M is described, (C) the non-selected anti-fuse memory M in a row and row different from the selected anti-fuse memory M is described.

(A) The non-selected anti-fuse memory M in the same column as the selected anti-fuse memory M, that is, the anti-fuse memory M21, M31 connected to the same bit line BL1 as the anti-fuse memory M11. In ...., the first selected column voltage (=5 V) is applied to the drain region 20c of the MOS transistor 20 from the bit line BL1, but to the memory gate electrode 10a, from the word line WL2, WL3...Apply the first non-selected row voltage (=0 V). As a result, the MOS transistors 20 of the anti-fuse memories M21, M31, etc. are turned off. As a result, in the anti-fuse memory M21, M31..., the memory gate electrode 10a of the memory capacitor 10 and the first source line voltage (=0 V) Between the diffusion regions 10b, there is no voltage difference that would break the insulation of the memory gate insulating film 10c. Therefore, no data is written in the anti-fuse memory M21, M31...

Some or all of the anti-fuse memory M21, M31... has written data and the memory capacitor 10 is in a short-circuit state. As described above, in the previous semiconductor memory device composed of the previous anti-fuse memory connecting the gate electrode of the MOS transistor and the drain region, it is in the same row as the selective anti-fuse memory of the shared word line The MOS transistors of the non-selected anti-fuse memory are turned on, so there is a problem that leakage current flows from the word line to the bit line through the memory capacitor in the short-circuit state. In the semiconductor memory device 1, if the MOS transistors 20 of the anti-fuse memories M21, M31... become conductive, the leakage current flows from the bit line BL1 through the MOS transistor 20 and the memory capacitor 10. It flows to the source lines SL2, SL3... However, in the semiconductor memory device 1, voltages can be independently applied to the bit line BL and the word line WL, and the first non-selected row voltage can be applied to one of the anti-fuse memories M21, M31... The gate electrode 20a of the MOS transistor 20 is set to an off state, so that no such leakage current is generated.

However, when writing data to the selected anti-fuse memory M, if an excessive voltage difference or excessive current flows between the memory gate electrode 10a and the diffusion region 10b, the memory capacitor 10 may be damaged. The situation spread to the inside of well S2. At this time, in addition to the usual leakage current path that flows through the memory gate electrode 10a, the memory gate insulating film 10c, and the surface of the well S2 to the source line SL, it also forms a path from the memory gate electrode 10a through the memory The gate insulating film 10c flows to the leakage path of the well S2. The leakage current flowing to the source line SL can be prevented by adjusting the voltage of the source line SL, but since the well potential needs to be set to 0 V, the leakage current flowing to the well S2 cannot be prevented.

As described above, in the previous semiconductor memory device, since the MOS transistors of the non-selected anti-fuse memory in the same column as the selected anti-fuse memory are turned on, there is a leakage path to the well. There is a problem that leakage current flows from the character line to the well through the memory capacitor in the short-circuit state. Therefore, in the previous semiconductor memory device, in order to avoid excessive damage of the memory capacitor and perform proper insulation damage, it is indispensable to precisely adjust and control the applied voltage for writing data.

In contrast, in the semiconductor memory device 1, voltages can be independently applied to the bit line BL and the word line WL, and the first non-selected row voltage can be applied to the anti-fuse memories M21, M31... The gate electrode 20a of the MOS transistor 20 is set to an off state, so even if there is a leakage path that flows to the well S2, the leakage current does not flow through the leakage path. This situation means that the leakage path to the well S2 is allowed to be formed during data writing, which is advantageous in terms of easily determining the data writing conditions such as the first selected row voltage and the first selected row voltage, and performing reliable insulation breakdown. .

In addition, because part or all of the anti-fuse memory M21, M31... flows to the source lines SL2, SL3... the leakage current is changed from the off-state MOS circuit as described above. The crystal 20 suppresses, so it is not necessary to set the voltage set for the source lines SL2, SL3... to be higher than 0 V to suppress the leakage current. Therefore, because the non-selective anti-fuse memory M connected to the source lines SL2, SL3..., that is, the anti-fuse memory M22, M32..., M23, M33... ...The potential of the diffusion region 10b rises, so it can prevent other anti-fuse memories M22, M32..., M23, M33 connected to the source lines SL2, SL3... ...Wait for error writing.

(B) The non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M, that is, the anti-fuse memory connected to the same character line WL1 and source line SL1 as the anti-fuse memory M11 In the bodies M12, M13,..., the MOS transistors 20 of them apply the first selected row voltage from the word line WL1 to the gate electrode 20a to be turned on. However, in the anti-fuse memories M12, M13..., the first non-selection from the bit lines BL2, BL3... is applied to the drain region 20c of the MOS transistor 20 Column voltage (=0 V). In addition, the first source line voltage (=0 V) is applied to the diffusion region 10b of the memory capacitor 10 from the source line SL1. Therefore, between the memory gate electrode 10a to which the first non-selected column voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first source line voltage is applied, no memory gate insulating film 10c is formed. The voltage difference of insulation breakdown. Therefore, no data is written to the anti-fuse memory M12, M13... In addition, the bit lines BL2, BL3... and the source line SL1 have the same voltage, so the leakage current does not pass through the memory capacitor 10 and becomes the anti-fuse memory M12, M13... It flows between the source line SL1 and the bit lines BL2, BL3...

In addition, to the gate insulating film 20d of the MOS transistor 20 of the anti-fuse memory M12, M13..., the first selected row voltage ( =6 V), but since the gate insulating film 20d is set thicker than the memory gate insulating film 10c according to the first selected row voltage, the gate insulating film 20d is not damaged by insulation.

(C) The non-selected anti-fuse memory M in a row and row different from the selected anti-fuse memory M, that is, any one of the connected bit line BL, word line WL, source line SL and the opposite In the anti-fuse memory M22, M32..., M23, M33... etc. which are different from the fuse memory M11, the gate electrode 20a of the MOS transistor 20 is applied with The first non-selected row voltage (=0 V) of the word lines WL2, WL3... Therefore, since the MOS transistor 20 maintains an off state, it is the same as in the case of the anti-fuse memory M21, M31 described above, but not in the anti-fuse memory M22, M32..., M23, M33... ...And so on to write data.

In addition, the leakage current does not flow through the source lines SL2, SL3, etc. of the anti-fuse memories M22, M32..., M23, M33... etc. which have not been short-circuited through the memory capacitor 10. .... Between the bit lines BL2, BL3... In addition, the bit lines BL2, BL3... connected to the anti-fuse memory M22, M32..., M23, M33..., etc. are applied with the first non-selected column Voltage (=0 V), therefore, no data is written due to the voltage of the bit lines BL2, BL3..., and no leakage current flows.

Next, the data reading operation will be described. When reading data, first set the second source line voltage to each source line SL. In this way, in the state of setting the second source line voltage, the second selected column voltage is applied to the bit line BL connected to the selected anti-fuse memory M, and the bit line BL is precharged to the second selected column voltage . In addition, the other bit lines BL are not precharged to the second non-selected column voltage.

After the precharge is completed, the bit line BL is set to a state of being electrically cut off from the column selection circuit 26. After that, the second selected row voltage is set for the word line WL connected to the selected antifuse memory M, and the second non-selected row voltage is set for the other word lines WL. Next, the sense amplifier 27 detects the change in the potential of the bit line BL at this time.

The second selected row voltage is set to be the gate voltage at which the MOS transistor 20 is turned on, and is set to be equal to or higher than the threshold voltage of the MOS transistor 20. In this example, the second selected row voltage is set to be lower than the first selected row voltage. The second non-selected column voltage is the gate voltage for turning the MOS transistor 20 into an off state. The second non-selected column voltage is set to the same voltage as the second source line voltage. In this example, the second selected column voltage and the second selected row voltage are 3 V, and the second non-selected column voltage, the second non-selected row voltage, the second source line voltage and the well voltage are the same 0 V.

For example, when reading the data of the anti-fuse memory M11, as shown in Figure 6, set the source lines SL1, SL2, SL3... as the second source line voltage (=0 V) In this state, the bit line BL1 is precharged to the second selected column voltage (=3 V). After the precharge is over, set the word line WL1 to the second selected row voltage (=3 V), and set the other word lines WL2, WL3... to the second non-selected row voltage (=0 V ).

The MOS transistor 20 of the anti-fuse memory M11 is turned on by applying 3 V from the word line WL1 to the gate electrode 20a. As a result, the voltage of the bit line BL1 is applied to the memory gate electrode 10a via the MOS transistor 20.

When data is not written into the anti-fuse memory M11, that is, when the memory capacitor 10 is in an insulated state, the current does not flow from the memory capacitor 10 to the source line SL1. Therefore, the bit line BL1 continues to maintain the pre-charged 3 V. On the other hand, when data has been written into the anti-fuse memory M11, that is, when the memory capacitor 10 is in a short-circuit state, the current flows from the bit line BL1 through the MOS transistor 20 and the memory capacitor 10 along the source line SL1 The direction flows, and the potential of the bit line drops.

Among other anti-fuse memories M21, M31... connected to the bit line BL1, from the word lines WL2, WL3... the memory gates of their MOS transistors 20 0 V is applied to the pole electrode 10a. As a result, the MOS transistors 20 of the anti-fuse memories M21, M31,... are maintained in an off state. Therefore, current does not flow from the bit line BL1 through the anti-fuse memories M21, M31...

As described above, the potential of the bit line BL1 is determined according to whether the memory capacitor 10 of the anti-fuse memory M, that is, the anti-fuse memory M11, is in a short-circuit state. If the memory capacitor 10 of the anti-fuse memory M11 is in a short-circuit state, the potential of the bit line BL1 decreases with the passage of time since the second selected column voltage is applied.

By detecting the change in the potential of the bit line BL1 with the sense amplifier 27, it can be determined whether the anti-fuse memory M11 is written, that is, the 1-bit data held by the anti-fuse memory M11.

As described above, when writing data to the selected anti-fuse memory M, the damage of the memory capacitor 10 spreads to the inside of the well S2, which is formed from the memory gate electrode 10a through the memory gate insulating film 10c The leakage path of the current flowing to the well S2.

In the previous semiconductor memory device, a sense amplifier is used to detect and read the potential of the bit line connected to the diffusion region of the memory capacitor. Specifically, if the memory capacitor is in a short-circuit state, the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifier element), and the current flows through the memory capacitor and the bit line The potential rises. If the memory capacitor is in an insulated state, even if the voltage applied to the word line is applied to the memory gate electrode of the memory capacitor through the MOS transistor (rectifier element), the current does not flow in the memory capacitor. There is no change in potential.

If a leakage path of current flowing from the memory gate electrode to the well through the memory gate insulating film is formed in the memory capacitor, the current flows from the memory gate electrode to the well, and does not flow to the diffusion area of the memory capacitor. In this way, in the previous semiconductor memory device, even if the memory capacitor is in a short-circuit state, the potential of the bit line does not rise, and it becomes unreadable.

In contrast, in the semiconductor memory device 1, when the memory capacitor 10 is in a short-circuit state, there is a leakage path for the current flowing from the memory gate electrode 10a to the well S2 through the memory gate insulating film 10c, even if the current is not Since the bit line BL1 flows in the direction of the source line SL1 through the MOS transistor 20 and the memory capacitor 10 to flow to the well S2, the potential of the bit line BL1 also drops. Therefore, when writing data to the selected anti-fuse memory M, the damage range of the memory capacitor 10 spreads to the inside of the well S2, and the formation is formed from the memory gate electrode 10a and flows to the well S2 through the memory gate insulating film 10c. In the case of the current leakage path, the sense amplifier 27 can also be used to detect the change in the potential of the bit line BL1 to determine whether to write data in the anti-fuse memory M11.

In the above example, in the data writing operation, the first non-selected row voltage is set to be the same as the well voltage (=0 V), but it can also be set to the middle between the well voltage and the first selected row voltage Voltage. For example, when the first source line voltage and well voltage are 0 V, and the first selected column voltage is 6 V, the first non-selected column voltage can be set to about 3 V. In this way, by setting the first non-selected column voltage to the intermediate voltage, the voltage applied to the gate insulating film 20d can be reduced. That is, the gate electrode 20a to which the first selection row voltage is applied from the word line WL and the surface of the second active region 32 formed directly under the gate electrode 20a from the bit line through the drain region 20c The voltage difference of the channel to which the first non-selected column voltage (intermediate voltage) is applied to the BL is set to be smaller than the above example. Therefore, the thickness of the gate insulating film 20d can be reduced. For example, the memory gate insulating film 10c and the gate insulating film 20d can be made the same thickness. In addition, in the case where the voltage of the first non-selected column is set as the intermediate voltage, the voltage difference between the intermediate voltage and the well voltage is set to be lower than the voltage that breaks the insulation of the memory gate insulating film 10c.

Also, in the above example, in the data writing operation, each source line SL is set to 0 V as the first source line voltage, but it is not connected to each source line of the selective anti-fuse memory M The voltage of SL is not limited to this. For example, the voltage of each source line SL not connected to the selective anti-fuse memory M may be set to an intermediate voltage higher than 0 V and lower than the voltage of the first selected column. At this time, the voltage of the first selected column can be set to 5 V, and the voltage of each source line SL not connected to the selected anti-fuse memory M can be set to, for example, about 3 V. At this time, for example, when the turn-off characteristic of the MOS transistor 20 is not sufficient, a part of the voltage of the first selected column of the bit line BL is applied to the memory gate electrode 10a of the memory capacitor 10. The voltage difference between the gate electrode 10a and the source line SL becomes smaller, so the leakage current flowing through the memory capacitor 10 in the short-circuit state can be reduced. In addition, in the case of controlling the voltage applied to the source line SL for each row as described above, it goes without saying that, for example, the first active region 31 extending in the row direction is formed for each row, and the first active region 31 is formed as the source line SL.

In the case where the voltage of each source line SL not connected to the selective anti-fuse memory M is set to an intermediate voltage as described above, the first non-selected row voltage can also be set to be higher than 0 V and lower than the first Select the voltage of the row voltage, and generate a voltage drop in the MOS transistor 20 so that the voltage applied to the memory gate electrode 10a through the MOS transistor 20 from the bit line BL to which the first selected row voltage is applied is below the intermediate voltage , Set the first non-selected row voltage in this way. For example, the first selected row voltage may be set to 6 V, the first selected column voltage may be set to 5 V, the intermediate voltage may be set to 3 V, and the first non-selected row voltage may be set to, for example, 3 V or less. At this time, as shown in the previous semiconductor memory device, the MOS transistor 20 of the non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M is turned on, but because it is applied to the memory gate electrode 10a The voltage difference between the voltage and the intermediate voltage of the source line SL is small, so the leakage current in the non-selected anti-fuse memory M connected to the same bit line BL as the selected anti-fuse memory M can be suppressed.

Furthermore, in the data reading operation, the second selected row voltage and the second selected column voltage are set to be the same, but it is not limited to this, and may be set to different voltages. For example, the second selected row voltage can also be set higher than the second selected column voltage, the second selected column voltage can be set to 3 V, and the second selected row voltage can be set to 5 V. By setting the second selected row voltage to be higher, the conduction current of the MOS transistor 20 can be increased, and the voltage drop speed of the bit line BL when the memory capacitor 10 is in a short-circuit state can be increased, and data can be read Speed up the action.

As described above, in the semiconductor memory device 1, even if the voltage of all the source lines SL is set to 0 V, data can be written and read. Therefore, as shown in the semiconductor memory device 1A having the circuit configuration shown in FIG. 7, the diffusion region 10b of the memory capacitor 10 and the well S2 may be of equal potential. At this time, for example, it is only necessary to form a diffusion region doped with a high concentration of P-type dopants instead of the diffusion region 10b of the memory capacitor 10. Or, it is only necessary to form a diffusion region in the first active region 31. When writing data with such a structure, the voltage difference between the memory gate electrode 10a and the first active region 31 (well S2) destroys the memory gate insulating film 10c, and the memory gate insulating film 10c is damaged during reading. The current of the cell line BL1 flows from the memory gate electrode 10a to the first active region 31 through the memory gate insulating film 10c whose insulation is broken. According to this semiconductor memory device 1A, the source line SL can be eliminated, and the circuit scale can be reduced.

In the above example, an N-type memory capacitor in which a memory gate insulating film and a memory gate electrode are laminated on the P-well (first active region), and on the P-well (second active region) The laminated gate insulating film and the N-type MOS transistor of the gate electrode constitute an anti-fuse memory, but the present invention is not limited to this, and a P-type memory capacitor and a P-type MOS transistor may also be used to constitute an anti-fuse memory. At this time, the P-type memory capacitor only needs to be constructed such that a memory gate insulating film and a memory gate electrode are stacked on the first active region provided in the N-well, and the first active region is doped with a high concentration of P-type dopant. Impurities and form a diffusion area. Regarding the diffusion region of the P-type memory capacitor, as in the above example, in addition to high-concentration doping with P-type dopants, it can also be configured as high-concentration doping with N-type dopants, or it can be configured to not form diffusion regions. . The P-type MOS transistor only needs to be set in the gate insulating film and the gate electrode of the N-type well build-up layer, and the drain region and the source region of the P-type dopant are doped with high concentration.

[Second Embodiment] In the semiconductor memory device of the second embodiment, the voltage applied to the non-selected source line during data writing is set to an intermediate voltage between the voltage applied to the selected source line and the voltage applied to the selected bit line. The semiconductor memory device of the second embodiment is the same as the first embodiment except for the details described below. In the following description, components that are substantially the same as those of the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted. Hereinafter, the case where the anti-fuse memory is formed by an N-type memory capacitor and an N-type MOS transistor will be described.

In this example, as shown in FIG. 8, the power supply unit PS supplies the word line driver 25a of the row selection circuit 25, the source line driver 25b, the bit line driver 26a of the column selection circuit 26, and the well voltage application unit 28 for writing Input voltage. The word line driver 25a is supplied with the first selected row voltage (V _SWL ) and the first non-selected row voltage (V _UWL ). In addition, the first selected source line voltage (V _SSL ) and the first non-selected source line voltage (V _USL ) are supplied to the source line driver 25b. The first selected source line voltage is the voltage applied to the source line SL connected to the selected anti-fuse memory M when writing data, that is, the selected source line voltage, and the first non-selected source line voltage is applied to the selected anti-fuse The unconnected source line SL of the silk memory M is the voltage of the non-selected source line.

The bit line driver 26a is supplied with the first selected column voltage (V _SBL ) and the first non-selected column voltage (V _UBL ). In addition, the well voltage applying part 28 is supplied with the well voltage (V _WEL ) applied to the well S2 from the power supply part PS. The well voltage applying unit 28 applies the well voltage to the well S2 when writing data.

In addition, various voltages for applying to the word line WL, source line SL, bit line BL, and well S2 are supplied from the power supply PS during reading, or used to drive the row selection circuit 25, column selection circuit 26, Although the voltage of the well voltage applying unit 28 itself is not shown in FIG. 8. The same applies to Fig. 12 described later.

In the semiconductor memory device 1 of this example, the first selected source line voltage is set to the same voltage as the first non-selected column voltage (V _SSL =V _UBL ). In addition, the first non-selected source line voltage is higher than the first selected source line voltage and lower than the first selected column voltage (V _SSL <V _USL <V _SBL ). That is, let the first non-selected source line voltage be an intermediate voltage between the first selected source line voltage and the first selected column voltage. Although the well voltage is set to be _{equal to or lower than the first selected source line voltage (V WEL} ≦V _SSL ), it is preferable to make the well voltage lower than the first selected source line voltage. Although the first non-selected row voltage is set _{to be higher than the first selected source line voltage (V SSL} ≦V _UWL ), it is preferable to set the first non-selected row voltage to a voltage higher than the first selected source line voltage. In addition, although the first selected row voltage is set to be _{equal to or higher than the first selected column voltage (V SBL} ≦V SWL ), it is preferable to set the first selected row voltage to a voltage higher than the first selected column voltage. Make the first non-selected row voltage lower than the first selected column voltage and lower than the first selected row voltage (V _UWL <V _SBL , V _UWL <V _SWL ).

The first selected column voltage is generated between the memory gate electrode 10a to which the voltage is applied via the MOS transistor 20 and the diffusion region 10b to which the first selected source line voltage is applied, thereby insulating the memory gate insulating film 10c The voltage of the broken voltage difference is set to be higher than the first selected source line voltage (V _SSL <V _SBL ).

Table 1 shows a specific example (voltage example) of the combination of the above-mentioned writing voltage. In any of the voltage examples N1 to N8 shown in Table 1, the first non-selected source line voltage is set as an intermediate voltage between the first selected source line voltage and the first selected column voltage. In addition, in the voltage examples N1 to N8, the first selected source line voltage and the first non-selected column voltage are the same. In addition, the voltage example N2 and the voltage example N4 have different voltages, but the relative high-low relationship of each voltage is set to be the same. Similarly, in the voltage example N6 and the voltage example N8, each voltage is different, but the relative high-low relationship of each voltage is set to be the same.

[Table 1]

The voltage examples N1 to N4 in the voltage examples N1 to N8 are the ones that set the first selected source line voltage and the first non-selected row voltage to be the same. The voltage examples N5 to N8 make the first selected source line voltage lower than the first selected source line voltage. 1 Non-selection of line voltage. In voltage examples N1, N2, N4 to N6, and N8, set the first selected source line voltage to be the same as the well voltage, but in voltage examples N3 and N7, make the well voltage lower than the first selected source line voltage . Also, in the voltage examples N1 and N5, the first selected column voltage and the first selected row voltage are set to be the same, but in the voltage examples N2 to N4, N6 to N8, the first selected row voltage is higher than the first selected row voltage Voltage.

Hereinafter, the details of the writing voltage will be described by taking the case of the voltage example N3 as an example. In voltage example N3, the well voltage is the lowest -2 V, and the first selection row voltage is the highest 6 V. The voltage of the first selected source line and the voltage of the first non-selected column are the same at 0 V, and the well voltage is set lower than the voltage of the first selected source line. In addition, the first non-selected row voltage is 0 V, and the first non-selected row voltage is the same as the first selected source line voltage. The voltage of the first selected column is 5 V, and the voltage of the first selected row is higher than the voltage of the first selected column. The first non-selected source line voltage is 3 V, that is, the intermediate voltage between the first selected source line voltage and the first selected column voltage set as described above. As described above, the voltage of the first non-selected row is 0 V, which is lower than the voltage of the first selected column of 5 V and the voltage of the first selected row of 6 V.

In the case of writing data into the anti-fuse memory M, such as when writing data into the anti-fuse memory M11, as shown in Figure 9, set the well S2 to the well voltage, which is -2 V, and set the character The line WL1 is set to the first selected row voltage, which is 6 V, and the word lines WL2, WL3,... Are set to the first non-selected row voltage, which is 0 V. In addition, the bit line BL1 is set to 5 V, which is the first selected column voltage, and the bit lines BL2, BL3, ... are set to 0 V, which is the first non-selected column voltage. Furthermore, the source line SL1 is set to 0 V, which is the first selected source line voltage, and the source lines SL2, 3, ... are set to 3 V, which is the first non-selected source line voltage.

By applying the voltage as described above, the anti-fuse memory M11 is the same as in the first embodiment, and the first selected column voltage is applied to the memory gate electrode 10a from the bit line BL1 via the MOS transistor 20 in the conductive state. , And a state where the first selected source line voltage of the source line SL1 is applied to the diffusion region 10b of the anti-fuse memory M11. Thereby, in the anti-fuse memory M11, between the memory gate electrode 10a and the channel of the first active region 31 formed directly under the memory gate electrode 10a, the memory gate is insulated The 5 V voltage difference of the insulation breakdown of the film 10c causes the insulation breakdown of the memory gate insulating film 10c, and data is written to the anti-fuse memory M11.

On the other hand, in the non-selected anti-fuse memory M, since the first non-selected row voltage is applied to the gate electrode 20a from the word line WL, the MOS transistor 20 is turned off, and the bit line BL responds to the MOS Either or both of the first non-selected row voltages are applied to the drain region 20c of the transistor 20. In the non-selected anti-fuse memory M in a row different from the selected anti-fuse memory M (hereinafter referred to as a non-selected row), since the MOS transistor 20 is in an off state, the voltage of the first selected column is not It is applied to the memory gate electrode 10a, so the memory gate insulating film 10c is not damaged by insulation. On the other hand, in the non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M, the MOS transistor 20 is turned on, and a signal from the bit line BL is applied to the memory gate electrode 10a. The first non-selected column voltage (0 V), but the first source line voltage (0 V) from the source line SL is applied to the diffusion region 10b of the memory capacitor 10. Therefore, between the memory gate electrode 10a and the diffusion region 10b, there is no voltage difference that causes the insulation breakdown of the memory gate insulating film 10c. Therefore, the memory gate insulating film 10c is not damaged by insulation.

As described above, the first non-selected source line voltage is set to 3 V, and it is set to an intermediate voltage between the first selected source line voltage of 0 V and the first selected column voltage of 5 V. As a result, in the non-selected anti-fuse memory M in which data in the non-selected row is written, if the disconnection characteristic of the MOS transistor 20 is insufficient, the first selected column voltage is applied through the MOS transistor 20 The voltage difference between a part of the memory gate electrode 10a and the source line SL also becomes smaller. As a result, the leakage current flowing between the source line SL and the bit line BL through the memory capacitor 10 and the MOS transistor 20 in the short-circuit state is reduced.

In addition, in the case of the other voltage examples N1, N2, N4~N8 of the voltage example N3, the first non-selected source line voltage is also set as the middle between the first selected source line voltage and the first selected column voltage Therefore, the same as the above, the leakage current is reduced.

The voltage of the first non-selected column is 0 V which is the same as the voltage of the first selected source line. In this way, by setting the voltage of the first non-selected column and the voltage of the first selected source line to the same voltage, the memory in the non-selected anti-fuse memory M in the same row as the selected anti-fuse memory M is prevented The insulation of the body gate insulating film 10c is broken, and leakage current is prevented from flowing from the bit line BL to the source line SL via the non-selective anti-fuse memory M. In addition, in the other voltage examples N1, N2, N4 to N8 of the voltage example N3, since the first non-selected column voltage and the first selected source line voltage are set to be the same, the leakage current is prevented from flowing.

Set the first selected source line voltage to 0 V, set the well voltage to -2 V, and set the well voltage to be lower than the first selected source line voltage. Thereby, the first selected source line voltage and the well voltage cause the MOS transistor 20 to be reverse biased. Therefore, due to the substrate bias effect, the threshold voltage of the MOS transistor 20 becomes higher, and the turn-off characteristic is improved. As a result, the leakage current between the bit line BL and the source line SL in the non-selected anti-fuse memory M in the non-selected row is reduced. In addition, the voltage example N7 also obtains the same effect.

In the voltage example N3, according to the above-mentioned relationship between the first selected source line voltage and the well voltage, the first selected source line voltage becomes the intermediate voltage between the well voltage and the first non-selected source line voltage. In addition, the first non-selected source line voltage is an intermediate voltage between the first selected source line voltage and the first selected column voltage. Therefore, the well voltage, the first selected source line voltage, the first non-selected source line voltage, and the first selected column voltage have a voltage relationship that sequentially increases in voltage (V _WEL ＜V _SSL ＜V _USL ＜V _SBL ) .

Relative to the first selected column voltage of 5 V, the first selected row voltage is set to 6 V, and the first selected row voltage is set to be higher than the first selected column voltage. Thereby, the voltage drop when the first selected column voltage is applied to the memory gate electrode 10a of the memory capacitor 10 through the MOS transistor 20 is reduced. In addition, regarding the voltage examples N2, N4, and N6 to N8, since the voltage of the first selected row is set higher than the voltage of the first selected column, the same effect can be obtained.

Use the combination of the writing voltage shown in the voltage example N7, for example, in the case of writing data into the anti-fuse memory M11, as shown in Figure 10, set the word lines WL2, WL3... The first non-selected row voltage is 1.5 V. The voltages applied to the other word lines WL1, source lines SL1, 2..., bit lines BL1, BL2..., and well voltages are the same as in the case of voltage example N3.

As in the voltage example N7, by setting the first non-selected row voltage to 1.5 V, the first non-selected row voltage is set to be higher than the first selected source line voltage. In this way, by setting the first non-selected row voltage higher than the first selected source line voltage, the MOS in the non-selected anti-fuse memory M in the same column as the selected anti-fuse memory M can be reduced. The electric field at the end of the drain region 20c under the gate electrode 20a of the transistor 20 reduces the junction leakage current (GIDL: Gate-Induced Drain Leakage). Regarding the voltage examples N5, N6, and N8, since the first non-selected row voltage is set to be higher than the first selected source line voltage, the same effect is obtained.

In addition, the first non-selected row voltage is set to be lower than the first selected column voltage and the first selected row voltage. Therefore, in voltage examples N5 to N8, the first non-selected row voltage is the intermediate voltage between the first selected source line voltage and the first selected column voltage, and is the first selected source line voltage and the first selected row voltage. The intermediate voltage between voltages. Of course, the first non-selected row voltage is the voltage at which the MOS transistor 20 is turned off.

In the voltage example N7, as in the voltage example N3, the first selected source line voltage becomes an intermediate voltage between the well voltage and the first non-selected source line voltage. In addition, the first non-selected source line voltage is an intermediate voltage between the first selected source line voltage and the first selected column voltage. Therefore, the well voltage, the first selected source line voltage, the first non-selected source line voltage, and the first selected column voltage have a voltage relationship that sequentially increases in voltage (V _WEL ＜V _SSL ＜V _USL ＜V _SBL ) .

Furthermore, in voltage example N7, as described above, the first non-selected row voltage is the intermediate voltage between the first selected source line voltage of 1.5 V, or 0 V, and the first non-selected source line voltage of 3 V . Therefore, the well voltage, the first selected source line voltage, the first non-selected row voltage, the first non-selected source line voltage, and the first selected column voltage have a voltage relationship (V _WEL ＜V _SSL ＜V _UWL ＜V _USL ＜V _SBL ).

When using the above-mentioned writing voltage for data writing in the anti-fuse memory M, for example, in the case of using six writing voltages as in voltage example N7, an example is shown in Figure 11, and the corresponding power supply PS can be used. There are six types of voltages for writing, and the voltage generating units Pa to Pf are provided. The voltage generating units Pa to Pf output voltages Va to Vf. The voltages Va, Vb, Vc, Vd, Ve, and Vf are sequentially reduced (Va>Vb>Vc>Vd>Ve>Vf).

In the case of voltage application N7, the voltage Va is 6 V, the voltage Vb is 5 V, the voltage Vc is 3 V, the voltage Vd is 1.5 V, the voltage Ve is 0 V, and the voltage Vf is -2 V. In addition, the voltage generating unit Pa and the voltage generating unit Pd are connected to the word line driver 25a, and the voltage Va from the voltage generating unit Pa is supplied as the first selected row voltage, and the voltage Vd from the voltage generating unit Pd is supplied as the first non- Select the row voltage supply. The voltage generating part Pc and the voltage generating part Pe are connected to the source line driver 25b, the voltage Ve from the voltage generating part Pe is supplied as the first selected source line voltage, and the voltage Vc from the voltage generating part Pc is supplied as the first non- Select the source line voltage supply. The voltage generating part Pb and the voltage generating part Pe are connected to the bit line driver 26a, and the voltage Vb from the voltage generating part Pb is supplied as the first selected column voltage, and the voltage Ve from the voltage generating part Pe is supplied as the first non-selected column Voltage supply. The voltage generating unit Pf is connected to the well voltage applying unit 28, and the voltage Vf is supplied as the well voltage.

In the case of using three types of writing voltages such as the voltage example N1, it is sufficient to use the power supply part PS that is provided with the voltage generating parts Pb, Pc, and Pe and outputting the three types of writing voltages. At this time, the voltage generating unit Pb and the voltage generating unit Pe are connected to the word line driver 25a, and the voltage Vb from the voltage generating unit Pb is supplied as the first selected row voltage, and the voltage Ve from the voltage generating unit Pe is supplied as the first Non-selected row voltage supply. In addition, the source line driver 25b is connected to the voltage generating unit Pc and the voltage generating unit Pe, and the voltage Ve from the voltage generating unit Pe is supplied as the first selected source line voltage, and the voltage Vc from the voltage generating unit Pc is supplied as the first selected source line voltage. 1 Non-select source line voltage supply. Furthermore, the voltage generating part Pb and the voltage generating part Pe are connected to the bit line driver 26a, the voltage Vb from the voltage generating part Pb is supplied as the first selected column voltage, and the voltage Ve from the voltage generating part Pe is supplied as the first Non-selected column voltage supply. The voltage generating unit Pe is connected to the well voltage applying unit 28, and the voltage Ve is supplied as the well voltage. In addition, in the voltage example N1, the voltages Vb, Vc, and Ve are set to 5 V, 3 V, and 0 V.

In the case of using 4 types of writing voltages such as voltage examples N2 and N4, it is sufficient to use the power supply unit PS which is provided with the voltage generating units Pa, Pb, Pc, and Pe and outputs 4 types of writing voltages. At this time, the voltage generating unit Pa and the voltage generating unit Pe are connected to the character line driver 25a, and the voltage Va from the voltage generating unit Pa is supplied as the first selected row voltage, and the voltage Ve from the voltage generating unit Pe is supplied as the first Non-selected row voltage supply. In addition, it is the same as the case of voltage example N1. In addition, the voltages Va, Vb, Vc, and Ve are set to 6 V, 5 V, 3 V, and 0 V in the voltage example N2, and 3 V, 2 V, 0 V, and -3 V in the voltage example N4.

In the case of using five types of writing voltages such as voltage example N3, it is sufficient to use the power supply part PS that sets the voltage generating parts Pa, Pb, Pc, Pe, and Pf to output the five types of writing voltages. At this time, the voltage generating unit Pe is connected to the well voltage applying unit 28 and the voltage Ve is supplied as the well voltage. In addition, it is the same as the case of voltage example N2. In addition, in the voltage example N3, the voltages Va, Vb, Vc, Ve, and Vf are set to 6 V, 5 V, 3 V, 0 V, and -2 V.

In the case of using four types of writing voltages such as voltage example N5, it is sufficient to use the power supply part PS that sets the voltage generating parts Pb, Pc, Pd, and Pe and outputs four types of writing voltages. At this time, the voltage generating part Pb and the voltage generating part Pd are connected to the word line driver 25a, the voltage Vb from the voltage generating part Pb is supplied as the first selected row voltage, and the voltage Vd from the voltage generating part Pd is supplied as the first non- Select the row voltage supply. In addition, it is the same as the case of voltage example N1. In addition, in the voltage example N5, the voltages Vb, Vc, Vd, and Ve are set to 5 V, 3 V, 1.5 V, and 0 V.

In the case of using five types of writing voltages such as voltage examples N6 and N8, it is sufficient to use the power supply part PS that is provided with the voltage generating parts Pa, Pb, Pc, Pd, and Pe and outputting five types of writing voltages. The voltage generating part Pa and the voltage generating part Pd are connected to the word line driver 25a, the voltage Va from the voltage generating part Pa is supplied as the first selected row voltage, and the voltage Vd from the voltage generating part Pd is supplied as the first non-selected row voltage supply. In addition, it is the same as the case of voltage example N2. In addition, the voltages Va, Vb, Vc, Vd, and Ve are set to 6 V, 5 V, 3 V, 1.5 V, and 0 V in the voltage example N6, and 3 V, 2 V, and 0 V in the voltage example N8. , -1.5 V, -3 V.

When using P-type memory capacitors and MOS transistors to form an anti-fuse memory, just set the writing voltage to the same as the above situation when using N-type memory capacitors and MOS transistors to form an anti-fuse memory. The opposite is fine. Therefore, it is only necessary to reverse the relationship between the high and low voltages Va to Vf output from the power supply unit.

In the case of using P-type memory capacitors and MOS transistors to form an anti-fuse memory, set the first selected source line voltage to the same voltage as the first non-selected column voltage (V _SSL =V _UBL ). Make the first non-selected source line voltage lower than the first selected source line voltage and higher than the first selected column voltage (V _SSL >V _USL >V _SBL ). That is, the first non-selected source line voltage is set to an intermediate voltage between the first selected source line voltage and the first selected column voltage. Although the well voltage is set to be equal to or higher than the first selected source line voltage (V _{WEL ≧V SSL} ), it is preferable to make the well voltage higher than the first selected source line voltage. Although the first non-selected row voltage is set to be _{equal to or lower than the first selected source line voltage (V SSL} ≧V _UWL ), it is preferable to set the first non-selected row voltage to a voltage lower than the first selected source line voltage. The voltage of the first non-selected row is higher than the voltage of the first selected column and is higher than the voltage of the first selected row (V _UWL > V _SBL , V _UWL > V _SWL ). Furthermore, it is preferable to set the voltage of _{the first selected row to be lower than the voltage of the first selected column (V SBL} ≧V _SWL ), and it is also preferable to set the voltage of the first selected row to be lower than the voltage of the first selected column (V _SBL ＞V _SWL ).

As the well voltage, the first selected source line voltage, the first non-selected source line voltage, the first selected row voltage, and the first non-selected when the anti-fuse memory is composed of P-type memory capacitors and MOS transistors The specific voltage combination examples of row voltage, first selected column voltage, and first non-selected column voltage are shown in Table 2 for voltage examples P1 to P6.

[Table 2]

The voltage examples P1 to P6 all set the first non-selected source line voltage to the intermediate voltage between the first selected source line voltage and the first selected column voltage. In the voltage examples P2 and P5 of the voltage examples P1 to P6, the first selection source line voltage is set lower than the well voltage (the well voltage is set higher than the first selection source line voltage). In addition, in the voltage examples P4 to P6, the first non-selected row voltage is set to be lower than the first selected source line voltage.

In the first and second embodiments, the voltage applied to the source line SL of the non-connected selective anti-fuse memory M during data writing is set to one type, but it is also possible to apply a different voltage according to the row Set to 2 types.

[Third Embodiment] In the semiconductor memory device of the third embodiment, the non-selected source line is set to float during data writing. Except for the details described below, it is the same as in the second embodiment, so constituent members that are substantially the same as those in the second embodiment are assigned the same reference numerals, and detailed descriptions thereof are omitted. In addition, the case where the anti-fuse memory is formed by an N-type memory capacitor and an N-type MOS transistor will be described.

In this example, as shown in FIG. 12, as the voltage for data writing, the first selected row voltage (V _SWL ) and the first non-selected row voltage are supplied from the power supply section PS to the word line driver 25a of the row selection circuit 25 (V _UWL ), and the first selected source line voltage (V _SSL ) is supplied to the source line driver 25b. In addition, the bit line driver 26a of the column selection circuit 26 is supplied with the first selected column voltage (V _SBL ) and the first non-selected column voltage (V _UBL ) from the power supply section PS. _{In addition, regarding the well S2, the well voltage (V WEL} ) is also supplied from the power supply unit PS to the well voltage application unit 28. The source line driver 25b applies the first selected source line voltage to the source line SL connected with the selective antifuse memory M, and sets the source line SL to which the selective antifuse memory M is not connected as a self-contained power supply The voltage source of the PS is electrically cut off in a floating state.

The voltage used for writing in this example is set to the following high-low relationship. The first selected source line voltage and the first non-selected column voltage are set to the same voltage, and these and the first non-selected row voltage are set to the same voltage (V _SSL =V _UBL =V _UWL ). Although the well voltage is set to be _{equal to or lower than the first selected source line voltage (V WEL} ≦V _SSL ), it is preferable to make the well voltage lower than the first selected source line voltage. In addition, although the first selected row voltage is set to be _{equal to or higher than the first selected column voltage (V SBL} ≦V SWL ), it is preferable to set the first selected row voltage to a voltage higher than the first selected column voltage. Make the first non-selected row voltage lower than the first selected column voltage and lower than the first selected row voltage (V _UWL <V _SBL , V _UWL <V _SWL ).

The source line driver 25b is provided with a switch unit 41 for each source line SL. The switch section 41 is composed of, for example, one or a plurality of switching elements such as MOS transistors. The part PS is electrically cut off, and the source line SL is set to any one of the disconnected ones in the floating state.

Table 3 shows a specific example (voltage example) of the combination of the above-mentioned writing voltages. The voltage examples N9 to N11 in Table 3 all set the source line SL of the unconnected selective anti-fuse memory M to a floating state, and set the first selected source line voltage, the first non-selected column voltage, and the first 1 Non-selected row voltages are set to be the same. In the voltage examples N9 and N10, the well voltage and the first selected source line voltage are set to be the same, and in the voltage example N11, the well voltage is set to be lower than the first selected source line voltage. In addition, in the voltage example N9, the first selected row voltage and the first selected column voltage are set to be the same, and in the voltage examples N10 and N11, the first selected row voltage is set to be higher than the first selected column voltage.

[table 3]

For example, using the voltage for writing in the voltage example N11 to write data into the anti-fuse memory M11, as shown in Figure 13, set the well S2 to the well voltage, which is -2 V, and set the word line WL1 to For the first selected row voltage, which is 6 V, set the word lines WL2, WL3... to the first non-selected row voltage, which is 3 V, and set the bit line BL1 to the first selected column voltage, which is 5 V. , Set the bit lines BL2, BL3... to the first non-selected column voltage, which is 0 V. In addition, the switch section 41 connected to the source line SL1 is turned on, the source line SL1 is set to the first selected source line voltage, which is 0 V, and the source lines SL2, 3... Each of the switch parts 41 is turned off, and the source lines SL2, 3... are set to a floating state.

As described above, by setting the source line SL to which the selective anti-fuse memory M is not connected to a floating state, the leakage current between the bit line BL and the source line SL is suppressed. That is, in the case where the off characteristic of the MOS transistor 20 is insufficient, the source line SL connected to the memory capacitor 10 becomes floating in the non-selected anti-fuse memory M in which the data in the non-selected row is written Therefore, the leakage current does not flow between the bit line BL and the source line SL through the MOS transistor 20 and the memory capacitor 10 in the short-circuit state.

In addition, regarding the first non-selected row voltage, by setting it to the same voltage as the first selected source line voltage, each non-selected row in the same column as the selected anti-fuse memory M (hereinafter referred to as the selected column) In the anti-fuse memory M, the MOS transistor 20 is not turned on. In the non-selective anti-fuse memory M in which the data in the selected row is written, if the MOS transistor 20 becomes conductive, the leakage current is automatically charged by the capacitive component of the source line SL set to the floating state The bit line BL flows to the source line SL which is set in a floating state. However, in this example, since the MOS transistor 20 is not turned on, the leakage current does not pass through the non-selective anti-fuse memory M in which data in the selected row is written, from the bit line BL to the source which is set to a floating state. Line SL flows.

The first non-selected column voltage is set to the same voltage as the first selected source line voltage, so as in the second embodiment, the non-selected anti-fuse memory in the same row as the selected anti-fuse memory M is prevented The insulation of the memory gate insulating film 10c in the body M is broken, and leakage current is prevented from flowing from the bit line BL to the source line SL via the non-selective anti-fuse memory M.

The effects of preventing leakage current from flowing as described above are the same for voltage examples N9 and N10, except for voltage example N11.

Furthermore, in voltage example 11, the MOS transistor 20 is reverse-biased by making the well voltage lower than the first selected source line voltage, and the threshold voltage of the MOS transistor 20 is made by the substrate bias effect. Go higher and improve cutoff characteristics. Furthermore, in the voltage examples N10 and N11, since the first selected row voltage is higher than the first selected column voltage, the first selected column voltage is applied to the memory gate electrode of the memory capacitor 10 through the MOS transistor 20 The voltage drop at 10a is reduced.

In the case of P-type memory transistors and MOS transistors constituting the anti-fuse memory, the source line of the unconnected selective anti-fuse memory can also be set to a floating state. When using P-type memory capacitors and MOS transistors to form an anti-fuse memory, the relationship between the writing voltage and the above-mentioned N-type memory capacitors and MOS transistors to form an anti-fuse memory can be reversed. .

Therefore, the first selected source line voltage and the first non-selected column voltage are set to the same voltage, and these are set to be the same as the first non-selected row voltage (V _SSL =V _UBL =V _UWL ). Although the well voltage is set to be equal to or higher than the first selected source line voltage (V _{WEL ≧V SSL} ), it is preferable to make the well voltage higher than the first selected source line voltage. Make the first non-selected row voltage higher than the first selected column voltage and higher than the first selected row voltage (V _UWL > V _SBL , V _UWL > V _SWL ). In addition, the first selected row voltage is set to be the same as the first selected column voltage.

As the well voltage, the first selected source line voltage, the first non-selected source line voltage, the first selected row voltage, and the first non-selected when the anti-fuse memory is composed of P-type memory capacitors and MOS transistors Table 4 shows voltage examples P7 and P8 for specific voltage combinations of row voltage, first selected column voltage, and first non-selected column voltage. In the voltage example P7, the first selected source line voltage is the same as the well voltage, and in the voltage example P8, the first selected source line voltage is set to the well voltage or lower.

[Table 4]

In each of the above-mentioned embodiments, a plurality of anti-fuse memories are arranged in a matrix of plural columns and plural rows, but as long as the number of columns and the number of rows is 1 or more, for example, it can also be set as 1 column and plural rows. Matrix-like, a matrix with a complex number of columns and 1 row.

1: Semiconductor memory device 1A: Semiconductor memory device 10: Memory capacitor 10a: Memory gate electrode 10b: Diffusion region 10c: Memory gate insulating film 20: MOS transistor 20a: Gate electrode 20b: Source region 20c : Drain region 20d: Gate insulating film 25: Row selection circuit 25a: Word line driver 25b: Source line driver 26: Column selection circuit 26a: Bit line driver 27: Sense amplifier 28: Well voltage applying section 31 : Active area 32: Active area 41: Switch part BL: Bit line BL1: Bit line BL2: Bit line BL3: Bit line C1: Contact C2: Contact C2a: Contact C2b: Contact C3: Contact Point C4: contact CA: memory array IL: component separation film M: anti-fuse memory M11: anti-fuse memory M12: anti-fuse memory M13: anti-fuse memory M21: anti-fuse memory M22: Anti-fuse memory M23: Anti-fuse memory M31: Anti-fuse memory M32: Anti-fuse memory M33: Anti-fuse memory Mij: Anti-fuse memory Pa～Pf: Voltage generating part PS : Power supply section S1: Semiconductor substrate S2: Well SL: Source line SL1: Source line SL2: Source line SL3: Source line SLi: Source line SW1: Side wall SW2: Side wall Va to Vf: Voltage V _SBL : No. 1Selected column voltage V _SSL : 1st selected source line voltage V _SWL : 1st selected row voltage V _UBL : 1st non-selected column voltage V _USL : 1st non-selected source line voltage V _UWL : 1st non-selected row Voltage V _WEL : Well voltage WL: Character line WL1: Character line WL2: Character line WL3: Character line WLi: Character line

FIG. 1 is a schematic diagram showing the circuit configuration of the semiconductor memory device of the first embodiment. Fig. 2 is an explanatory diagram showing the supply of the writing voltage from the power supply unit to the row selection circuit and the column selection circuit. FIG. 3 is a cross-sectional view showing the structure of the anti-fuse memory. FIG. 4 is an explanatory diagram showing the planar layout of each active area, source line, word line, and bit line of the memory array. FIG. 5 is an explanatory diagram showing an example of the voltage application state to each source line, each word line, and each bit line during the write operation. FIG. 6 is an explanatory diagram showing an example of the voltage application state to each source line, each word line, and each bit line during the reading operation. FIG. 7 is a schematic diagram of the circuit configuration of a semiconductor memory device showing an example of electrically connecting the diffusion regions of the memory capacitors to the wells in an equal potential manner. FIG. 8 is an explanatory diagram showing the supply of the writing voltage from the power supply unit to the row selection circuit and the column selection circuit of the second embodiment. FIG. 9 is an explanatory diagram showing an example of the voltage application state to each source line, each word line, and each bit line during the write operation in the second embodiment. FIG. 10 is an explanatory diagram showing an example in which the voltage of the first non-selected row is higher than the voltage of the first selected source line. FIG. 11 is a block diagram showing an example of the structure of the power supply unit. FIG. 12 is an explanatory diagram showing the supply of the writing voltage from the power supply unit to the row selection circuit and the column selection circuit of the third embodiment. FIG. 13 is an explanatory diagram showing an example of the state of voltage application to each source line, each word line, and each bit line during the write operation in the third embodiment.

1: Semiconductor memory device

10: Memory capacitor

10a: Memory gate electrode

10b: Diffusion area

20: MOS transistor

20a: gate electrode

20b: source region

20c: Drain area

25: Row selection circuit

26: column selection circuit

27: Sense amplifier

BL: bit line

CA: Memory Array

M: Anti-fuse memory

SL: source line

WL: Character line

Claims (6)

A semiconductor memory device, characterized by comprising: A memory array is composed of a plurality of anti-fuse memories arranged in a matrix, and the anti-fuse memory includes: a memory capacitor having an active area, a memory gate insulating film formed on the active area, and A memory gate electrode on the above-mentioned memory gate insulating film, and a diffusion region formed in the above-mentioned active region; and a MOS transistor having a gate electrode, a source region, and a drain region, the above-mentioned source The area is connected to the above-mentioned memory gate electrode; A plurality of bit lines, which extend in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned drain regions in the rows, and among the above-mentioned plurality of anti-fuse memories A bit line connected to the anti-fuse memory of the writing target is applied with a voltage that breaks the insulation of the above-mentioned memory gate insulating film, that is, the first selected column voltage; A plurality of character lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the above-mentioned gate electrodes in the rows, and located in the anti-fuse memories of the above-mentioned writing object For one word line connected, apply the voltage that sets the MOS transistor to the on state, that is, the first selected row voltage; and A plurality of source lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the above-mentioned diffusion regions in the rows, and connected to the anti-fuse memories of the above-mentioned writing object For one source line, when the MOS transistor is N-type, the first selected source line voltage above the well voltage applied to the well where the active region is formed is applied, and the MOS transistor is P In the case of type, apply the first selected source line voltage below the well voltage, and apply the first selected source line voltage and the first Select the intermediate voltage between the column voltages, that is, the first non-selected source line voltage. The semiconductor memory device of claim 1, wherein the first selected source line voltage is lower than the first non-selected row voltage when the MOS transistor is N-type when the MOS transistor is P-type When the voltage is higher than the first non-selected row voltage mentioned above. A semiconductor memory device, characterized by comprising: A memory array is composed of a plurality of anti-fuse memories arranged in a matrix, and the anti-fuse memory includes: a memory capacitor having an active area, a memory gate insulating film formed on the active area, and A memory gate electrode on the above-mentioned memory gate insulating film, and a diffusion region formed in the above-mentioned active region; and a MOS transistor having a gate electrode, a source region and a drain region, the above-mentioned source region Connected to the gate electrode of the memory; A plurality of bit lines, which extend in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned drain regions in the rows, and among the above-mentioned plurality of anti-fuse memories A bit line connected to the anti-fuse memory of the writing target is applied with a voltage that breaks the insulation of the above-mentioned memory gate insulating film, that is, the first selected column voltage; A plurality of character lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the above-mentioned gate electrodes in the rows, and located in the anti-fuse memories of the above-mentioned writing object For one word line connected, apply the voltage that sets the MOS transistor to the on state, that is, the first selected row voltage; and A plurality of source lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the above-mentioned diffusion regions in the rows, and connected to the anti-fuse memories of the above-mentioned writing object For one source line, when the MOS transistor is N-type, the first selected source line voltage above the well voltage applied to the well where the active region is formed is applied, and the MOS transistor is P In the case of the type, the first selected source line voltage below the well voltage is applied, and the unconnected source line of the anti-fuse memory of the writing target is set to a floating state. The semiconductor memory device according to any one of claims 1 to 3, wherein the first selected row voltage is higher than the first selected row voltage when the MOS transistor is N-type. A semiconductor memory device, characterized by comprising: A memory array is composed of a plurality of anti-fuse memories arranged in a matrix, and the anti-fuse memory includes: a memory capacitor having an active area, a memory gate insulating film formed on the active area, and A memory gate electrode on the above-mentioned memory gate insulating film, and a diffusion region formed in the above-mentioned active region; and a MOS transistor having a gate electrode, a source region, and a drain region, the above-mentioned source The area is connected to the above-mentioned memory gate electrode; A plurality of bit lines, which extend in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the drain regions in the rows; A plurality of character lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the gate electrodes in the rows; A plurality of source lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned diffusion regions in the rows; A bit line driver, which applies the memory gate to one bit line connected to the antifuse memory of the plurality of antifuse memories among the plurality of bit lines and the antifuse memory of the plurality of antifuse memories The voltage at which the insulation breakdown of the polar insulating film is the first selected column voltage; A character line driver, which applies a voltage that turns the MOS transistor into a conductive state, that is, the first one of the plurality of character lines connected to the antifuse memory of the writing target Select the row voltage; and The source line driver applies to one source line connected to the anti-fuse memory of the writing target among the plurality of source lines, when the MOS transistor is N-type, the above-mentioned The first selected source line voltage above the well voltage applied to the well of the active region, and when the MOS transistor is P-type, apply the first selected source line voltage below the well voltage and write to the above To the source line of the target anti-fuse memory that is not connected, an intermediate voltage between the first selected source line voltage and the first selected column voltage, that is, the first non-selected source line voltage is applied. A semiconductor memory device, characterized by comprising: A memory array is composed of a plurality of anti-fuse memories arranged in a matrix, and the anti-fuse memory includes: a memory capacitor having an active area, a memory gate insulating film formed on the active area, and A memory gate electrode on the above-mentioned memory gate insulating film, and a diffusion region formed in the above-mentioned active region; and a MOS transistor having a gate electrode, a source region, and a drain region, the above-mentioned source The area is connected to the above-mentioned memory gate electrode; A plurality of bit lines, which extend in the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the drain regions in the rows; A plurality of character lines extending in the row direction according to the rows of the plurality of anti-fuse memories, and respectively connected to the gate electrodes in the rows; A plurality of source lines, which are arranged along the row direction according to the rows of the plurality of anti-fuse memories, and are respectively connected to the above-mentioned diffusion regions in the rows; A bit line driver, which applies the memory gate to one bit line connected to the antifuse memory of the plurality of antifuse memories among the plurality of bit lines and the antifuse memory of the plurality of antifuse memories The voltage at which the insulation breakdown of the polar insulating film is the first selected column voltage; A character line driver, which applies a voltage that turns the MOS transistor into a conductive state, that is, the first one of the plurality of character lines connected to the antifuse memory of the writing target Select the row voltage; and The source line driver applies to one source line connected to the anti-fuse memory of the writing target among the plurality of source lines, when the MOS transistor is N-type, the above-mentioned The first selected source line voltage above the well voltage applied to the well of the active region, and when the above MOS transistor is P-type, apply the first selected source line voltage below the well voltage and write the above The unconnected source line of the target's anti-fuse memory is set to a floating state.

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