TW202127511A - Method of forming semiconductor device - Google Patents

Abstract

An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.

Description

Method for forming semiconductor device

The content of the embodiments of the present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a wraparound gate field effect transistor (GAA FET) device, so as to improve the performance of the manufactured semiconductor device.

As the semiconductor industry evolves to the nanotechnology process node, in pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs. For example, multi-gate field effect transistors (FETs) include fin field effect transistors (FinFET) and gate-all-around (GAA) field effect transistors. In the fin-type field effect transistor, a gate electrode is adjacent to three sides of a channel region, and a gate dielectric layer is arranged between them. Since the gate structure surrounds (wraps) on the three sides of the fin, the transistor basically has three gates to control the current through the fin or the channel area. The fourth side of the fin, that is, the bottom of the channel, is not substantially controlled by the gate. In contrast, in a wrap-around gate field effect transistor, all sides of the channel region are surrounded by gate electrodes, which allows more depletion in the channel region, and because of the steeper subcritical current swing (sub-threshold current swing) and a smaller drain lead to drain induced barrier lowering, resulting in less short-channel effects. As the size of transistors continues to shrink, there is a real need to further improve the surrounding gate field effect transistors (GAA FinFET).

Some embodiments of the present invention provide a method of forming a semiconductor device. The forming method includes: forming an insulating layer on a semiconductor substrate; forming a semiconductor-containing substrate on the insulating layer; forming a semiconductor-containing substrate on the semiconductor-containing substrate; A stack of second semiconductor layers, where the first semiconductor layers and the second semiconductor layers have different material compositions and are alternately arranged in the stack; for the insulating layer, the semiconductor-containing substrate, and the The aforementioned stack of the first semiconductor layers and the second semiconductor layers is patterned to form a fin structure. The fin structure includes sacrificial layers containing the first semiconductor layers. ) And channel layers containing these second semiconductor layers; forming source/drain features (source/drain features) on the channel layers adjacent to the aforementioned fin structure; removing these of the aforementioned fin structure The sacrificial layer exposes the channel layers of the aforementioned fin structure. The forming method further includes forming a gate structure around the exposed channel layers, wherein a bottom surface of the semiconductor-containing substrate physically contacts a top surface of the insulating layer, wherein the insulating layer and the aforementioned insulating layer The substrate containing the semiconductor is disposed between a bottommost portion of the aforementioned gate structure and the aforementioned semiconductor substrate.

Some embodiments of the present invention provide a method for forming a semiconductor device. The forming method includes forming a dielectric-containing substrate on a semiconductor substrate; forming a plurality of first semiconductor layers and a second semiconductor layer in a first direction above the semiconductor substrate. Between the first semiconductor layers; the first semiconductor layers and the second semiconductor layers are patterned to form a fin structure, so that the fin structure includes the first semiconductor layers Sacrificial layers of the semiconductor layer and a channel layer containing the aforementioned second semiconductor layer; a sacrificial gate structure is formed on the aforementioned fin structure, so that the aforementioned sacrificial gate structure Cover a part of the aforementioned fin structure, while the remaining part of the aforementioned fin structure remains exposed; remove the remaining part of the aforementioned fin structure; at least form a recessed surface on the sacrificial layer Inner spacer; forming a source/drain region adjacent to the inner spacer and the channel layer; removing the sacrificial gate structure; removing the sacrificial gate structure after removing the sacrificial gate structure The sacrificial layers in the aforementioned fin structure expose the aforementioned channel layer and are suspended over the aforementioned dielectric-containing substrate; and form a gate dielectric layer and a gate A gate electrode layer surrounds the exposed channel layer, wherein a bottom surface of the dielectric-containing substrate physically contacts a top surface of the semiconductor substrate, wherein in the first direction, the The gate dielectric layer and the gate electrode layer are arranged between the substrate containing the dielectric and the channel layer.

Some embodiments of the present invention provide a semiconductor device, including: a dielectric-containing substrate is located on a semiconductor substrate; and channel layers are vertically suspended on the aforementioned dielectric-containing substrate. On the substrate, a bottom channel layer is vertically separated from the substrate containing the dielectric by a space; a first source/drain region (first source/drain region) is located on the semiconductor substrate Above, and the first source/drain region is in contact with the first ends of the aforementioned channel layer; a second source/drain region (second source/drain region) is located on the aforementioned semiconductor substrate, and The second source/drain region contacts the second ends of the aforementioned channel layer; a gate dielectric layer is located on the aforementioned channel layer and surrounds each channel layer; and a gate electrode layer The gate electrode layer is located on the gate dielectric layer, and the gate electrode layer surrounds each channel layer, wherein the gate dielectric layer and the gate electrode layer surrounding the bottommost channel layer are located on the dielectric layer. In the space between the substrate and the bottommost channel layer, the substrate containing the dielectric is in physical contact with the semiconductor substrate.

The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if it is mentioned in the description that a first characteristic component is formed above or on a second characteristic component, it may include the embodiment in which the first and second characteristic components are in direct contact, or it may include additional features. An embodiment in which a component is formed between the above-mentioned first feature and the above-mentioned second feature component so that the first and second feature components do not directly contact. In addition, the embodiment of the present invention may repeat component symbols and/or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed.

In addition, in the following disclosure, forming a feature on, connecting to, and/or coupling to another feature may include embodiments in which these features are formed in direct contact, and may also include The embodiments of other features are arranged between the features, so that these features are not in direct contact. In addition, spatially related terms may be used here, such as "lower", "higher", "horizontal", "vertical", "above", "above", "in "...Below", "below", "above", "below", "top", "bottom", etc., and other similar terms can be used here to describe an element or part as shown in the figure The relationship with other elements or components. The related terms in this space include not only the orientation shown in the diagram, but also the different orientations of the device in use or operation. The device can be rotated to other orientations, and the relative description of the space used here can also be interpreted according to the rotated orientation. Furthermore, when a value or a range of values is described by words such as "about", "approximately", "approximately", unless otherwise specified, these words are intended to make the described value include the positive or negative of the value Ten percent (±10%) range. For example, the term "about 5nm" encompasses the numerical range from 4.5nm to 5.5nm.

This disclosure is related to, but not limited to, a multi-gate field effect transistor (multi-gate field effect transistor). One example is a wrap-around gate field effect transistor (GAA FET). In a wrap-around gate field-effect transistor, a plurality of semiconductor channel layers are vertically suspended on a semiconductor substrate below. A gate structure (including a gate electrode layer and a gate dielectric layer) is formed in the space between vertically adjacent semiconductor channels. The embodiment of the present disclosure proposes that at least one insulating layer is disposed between the bottommost gate structure and the underlying semiconductor substrate, where the bottommost gate structure refers to the gate closest to the underlying semiconductor substrate structure. The aforementioned at least one insulating layer disposed between the bottommost gate structure and the semiconductor substrate below can reduce the leakage current in the wrap-around gate field-effect transistor, and minimize the semiconductor substrate and the surrounding gate field-effect transistor. The size of a parasitic PN junction between the source/drain region and the ratio of the turn-on current to the turn-off current of the wrap-around gate field effect transistor (I _ON /I _OFF ratio) are improved.

Figures 1-22C show an exemplary continuous process for manufacturing a wrap-around gate field effect transistor (GAA FET) device according to an embodiment of the present disclosure. It is understandable that some additional steps may be provided before, during, and after each stage of the process described in Figs. 1-22C. Some steps described below can be replaced or eliminated in the method of some other embodiments. The sequence of steps/processes may be interchangeable.

FIG. 1 shows an implantation process performed on a semiconductor substrate 10, in which impurity ions (dopant) 12 are implanted in the semiconductor substrate 10 to form a well region. This well area can be an N-type well area or a P-type well area. Implementing this ion implantation can avoid punch-through effects. In one embodiment, the semiconductor substrate 10 includes at least a single crystalline semiconductor layer on a surface portion thereof. The semiconductor substrate 10 may include a single crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide ( GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In this embodiment, the semiconductor substrate 10 includes silicon (Si).

The semiconductor substrate 10 may include one or more buffer layers (not shown) in its surface area. The buffer layer can provide a lattice constant that gradually changes from the semiconductor substrate to the source/drain regions. The buffer layer can be formed by epitaxial growth of a single crystal semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), and indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), gallium indium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), Gallium nitride (GaN), gallium phosphide (GaP) and indium phosphide (InP). In a specific embodiment, the semiconductor substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the semiconductor substrate 10. The germanium concentration of the silicon germanium buffer layer can be increased from 30 atomic% germanium in the bottom-most buffer layer to 70 atomic% germanium in the top-most buffer layer. The semiconductor substrate 10 may include a plurality of regions formed by appropriately doping with impurities (for example, impurities having a p-type or n-type conductivity). The dopant 12 is, for example, boron (BF ₂ ) of an n-type Fin FET, or phosphorous (p-type Fin FET) of a p-type Fin FET. P).

In FIG. 2, an insulating layer 14 is formed (for example, directly formed) on the semiconductor substrate 10. The insulating layer 14 includes or is an electrical insulating material, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), silicon carbide nitride (SiCN), fluorine doped silicate glass (fluorine doped silicate). glass, FSG), or a low-k dielectric material. The insulating layer 14 can be deposited by low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (plasma-CVD), or flowable CVD (FCVD). And formed on the semiconductor substrate 10.

In FIG. 3, a semiconductor-containing layer 16 is formed (for example, directly formed) on the insulating layer 14. The semiconductor-containing layer may have a composition different from that of the insulating layer 14. For example, the semiconductor-containing layer 16 may be a semiconductor-on-insulator (SOI) substrate (for example, a completely depleted SOI substrate or a partially depleted SOI substrate), which includes a semiconductor material formed on the semiconductor substrate (for example, (Silicon) layer. The insulator layer containing the semiconductor layer 16 can be, for example, a buried oxide (BOX) layer, a silicon monoxide layer, or the like. In some embodiments, the semiconductor material of the semiconductor-containing layer 16 may not be doped. However, in other embodiments, the semiconductor material of the semiconductor-containing layer 16 may be doped so as to be compatible with the channel layer formed on the semiconductor-containing layer 16 (for example, the second semiconductor material described below with reference to FIG. 4). Layer 25) has different conductivity types. In some embodiments, the thickness T1 (for example, measured along the Z direction) of the semiconductor-containing layer 16 can range from about 0.4 times the gate length of the transistor device to about 0.4 times the gate length of the transistor device. Within the range of 0.6 times (for example, about 0.5 times the gate length of the transistor device). The gate length is shown in Figure 9 and is denoted as length L _G. As an example, the thickness T1 of the semiconductor-containing layer 16 may range from about 3 nanometers to about 7 nanometers (for example, about 5 nanometers) to achieve high device performance, such as higher The current and the faster current speed.

In FIG. 4, a stacked semiconductor layer is formed on the above-mentioned semiconductor layer-containing substrate 10 in a staggered or alternately arranged manner. The stacked semiconductor layers extend perpendicularly (for example, along the Z direction) from the semiconductor-containing layer 16. For example, a first semiconductor layer 20 is disposed above the semiconductor-containing layer 16, the second semiconductor layer 25 is disposed above the first semiconductor layer 20, and the other first semiconductor layer 20 is disposed above the second semiconductor layer 25 to And so on and continue to set. Furthermore, a mask layer 15 is formed on the aforementioned stacked layers. The first semiconductor layer 20 and the second semiconductor layer 25 include materials with different lattice constants, and may include one or more layers of silicon (Si), germanium (Ge), silicon germanium (SiGe), and gallium arsenide (GaAs) , Indium Antimonide (InSb), Gallium Phosphide (GaP), Gallium Antimonide (GaSb), Indium Aluminum Arsenide (InAlAs), Indium Gallium Arsenide (InGaAs), Gallium Antimony Phosphide (GaSbP), Gallium Antimony Arsenide (GaAsSb), or indium phosphide (InP).

In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 include silicon, a silicon compound, silicon germanium (SiGe), germanium, or a germanium compound. In one embodiment, the first semiconductor layer 20 includes Si _(1-x) Ge _x , where x is greater than about 0.3. For example, when x=1.0, the first semiconductor layer 20 includes Ge. And the second semiconductor layer 25 includes silicon or Si _(1-y) Ge _y , where y is less than about 0.4, and x is greater than y.

In other embodiments, the second semiconductor layer 25 includes Si _(1-y) Ge _y , where y is greater than about 0.3, and in this embodiment, the first semiconductor layer 20 includes Si or Si _(1-x) Ge _x , where x is less than about 0.4 and x is less than y (x<y). In some other embodiments, the first semiconductor layer 20 includes Si _(1-x) Ge _x , where x is in a range from about 0.3 to about 0.8, and the second semiconductor layer 25 includes Si _(1-x) Ge _x , where x is in the range from about 0.1 to about 0.4.

In Fig. 4, five layers of the first semiconductor layer 20 and five layers of the second semiconductor layer 25 are provided. However, the number of layers of the first semiconductor layer 20 and/or the second semiconductor layer 25 is not limited to five layers, but can be as small as one layer, and in some embodiments, each of the first semiconductor layer and the second semiconductor layer can be Form two to ten layers. It should be noted that the first semiconductor layer 20 is a sacrificial layer that will be partially removed later, and the second semiconductor layer 25 will be fabricated into a channel layer of a wrap-around gate field-effect transistor (GAA FET) later. By adjusting the number of stacked layers, the driving current of the wrap-around gate field effect transistor device can be adjusted. It should also be noted that in some embodiments, the second semiconductor layer 25 may be doped to have a different conductivity type from the semiconductor material of the underlying semiconductor layer 16.

The bottom first semiconductor layer 20 (for example, the first semiconductor layer 20 closest to the semiconductor-containing layer 16 in the Z direction and/or in physical contact with the semiconductor-containing layer 16) is epitaxially formed on the semiconductor-containing layer 16 above. The second semiconductor layer 25 at the bottom (for example, the first semiconductor layer 20 closest to the bottom in the Z direction and/or the second semiconductor layer 25 that is in physical contact with the first semiconductor layer 20 at the bottom) is epitaxially ) Is formed on the first semiconductor layer 20 at the bottom. The aforementioned epitaxial process is repeated to form the stacked semiconductor layers 20 and 25 as shown in FIG. 4. The thickness of each first semiconductor layer 20 may be equal or different. The thickness of the first semiconductor layer 20 may be equal to or greater than the thickness of the second semiconductor layer 25. In some embodiments, the thickness of each first semiconductor layer 20 is in the range of about 5 nanometers to about 50 nanometers. In some other embodiments, the thickness of each first semiconductor layer 20 ranges from about 10 nanometers to about 30 nanometers. The thickness of the second semiconductor layer 25 in some embodiments ranges from about 5 nanometers to about 30 nanometers. In some other embodiments, the thickness of the second semiconductor layer 25 is in the range of about 10 nanometers to about 20 nanometers. In some embodiments, the thickness of the bottom first semiconductor layer 20 may be thicker than the remaining first semiconductor layers 20. In these embodiments, the thickness of the first semiconductor layer 20 at the bottom is in the range of about 10 nanometers to about 50 nanometers (for example, in the range of about 20 nanometers to about 40 nanometers).

In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of silicon oxide, and can be formed through thermal oxidation. The second mask layer 15B may include a different material from the first mask layer 15A. For example, in one example, the second mask layer 15B contains silicon nitride (SiN), and can be deposited by chemical vapor deposition (CVD), low pressure CVD (LPCVD), and electrical It is formed by plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. Through a patterning step including photo-lithography and etching processes, the mask layer 15 can be patterned to form a mask pattern. It is noted that, in some embodiments, at least one layer of the first mask layer 15A or the second mask layer 15B may include a light absorbing material.

Next, as shown in FIG. 5, the stacked layers of the first semiconductor layer 20 and the second semiconductor layer 25 are patterned. In one example, the mask layer 15 is patterned to form a patterned mask layer 15'. Then, the pattern of the patterned mask layer 15' is transferred to the stacked layer of the first semiconductor layer 20 and the second semiconductor layer 25, thereby forming fin structures 30 extending along the X direction. In some embodiments, an anisotropic etching process is used to form the fin structure 30. In the example of FIG. 5, the fin structures 30 are laterally separated from each other in the Y direction. Note that the number of fin structures is not limited to two, and can be reduced to, for example, one fin structure, or as many as three or more fin structures. In some embodiments, one or more dummy fin structures are formed on one or both sides of the fin structure 30 to improve the pattern fidelity in the patterning step.

As shown in FIG. 5, the fin structure 30 has a portion formed by stacked semiconductor layers 20 and 25, a patterned semiconductor-containing layer 16', a patterned insulating layer 14', and a well region 10'. Note that the well region 10' is formed by patterning the semiconductor substrate 10 (for example, by transferring the pattern of the patterned mask layer 15' to the semiconductor substrate 10). In some embodiments, the width W1 (for example, measured along the Y direction) of the upper portion of the fin structure 30 may be in the range of about 10 nm to about 40 nm (for example, at about Between 20 nanometers and approximately 30 nanometers). The height H1 of the fin structure 30 (for example, measured along the Z direction) may be in the range of about 100 nanometers to about 200 nanometers.

Referring to FIG. 6, after the fin structure 30 is formed, an insulating material layer 41 (including one or more insulating materials) is formed on the semiconductor substrate 10, so that the fin structure 30 is completely buried in the insulating material layer 41 . The insulating material of the insulating material layer 41 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxynitride (SiOCN), silicon carbide nitride (SiCN), fluorinated silicate glass (FSG) or Low-k dielectric materials, and the insulating material layer 41 can be deposited by low-pressure chemical vapor deposition (LPCVD), plasma-CVD or flowable chemical vapor deposition (flowable chemical vapor deposition). CVD) and formed. After the insulating material layer 41 is formed, one or more annealing steps may be performed (for example, to drive out free carbon and/or free nitrogen in the material of the insulating material layer 41). Then, a planarization step is performed, such as a chemical mechanical polishing (CMP) process and/or an etch-back process, so that the upper surface of the uppermost second semiconductor layer 25 is exposed from the insulating material layer 41, As shown in Figure 6. In some embodiments, before the insulating material layer 41 is formed, a first liner layer 35 is formed on the structure shown in FIG. 5. The first liner layer 35 may include silicon nitride (SiN) or other silicon nitride-based materials (such as silicon oxynitride (SiON), silicon carbide oxynitride (SiCN), or silicon oxynitride (SiOCN)).

Next, referring to FIG. 7, the insulating material layer 41 is recessed to form an isolation insulating layer 40, so that the upper portions of the fin structure 30 are exposed. Through this step, the fin structure 30 is electrically isolated from each other by the isolation insulating layer 40, which is also called shallow trench isolation (STI). In the embodiment shown in FIG. 7, the insulating material layer 41 is recessed until the bottom of the first semiconductor layer 20 is exposed. In some other embodiments, at least the upper portion of the patterned semiconductor-containing layer 16' is also exposed. In the example shown in FIG. 7, the first liner layer 35 is also recessed to expose the upper part of the fin structure 30.

As shown in FIG. 8, after the isolation insulating layer 40 is formed, a sacrificial gate dielectric layer 52 is formed. The sacrificial gate dielectric layer 52 includes one or more layers of insulating materials, such as silicon oxide-based materials. In one embodiment, the sacrificial gate dielectric layer 52 includes silicon oxide formed by chemical vapor deposition (CVD). In some embodiments, the thickness of the sacrificial gate dielectric layer 52 is in the range of about 1 nanometer to about 5 nanometers.

FIG. 9 shows the structure after a sacrificial gate structure 50 is formed on the fin structure 30. The sacrificial gate structure 50 includes a sacrificial gate electrode layer 54 and a sacrificial gate dielectric layer 52. The sacrificial gate structure 50 is formed on a part of the fin structure which is later used as the channel region. The sacrificial gate structure defines the channel area of the surrounding gate field effect transistor. The gate length (gate length) relative to the thickness T1 of the patterned semiconductor-containing layer 16' is shown in FIG. 9, and is denoted as the length L _G.

As shown in FIG. 8, the sacrificial gate structure 50 is formed by first blanket depositing a sacrificial gate dielectric layer 52 on the fin structure. Then, the sacrificial gate electrode layer 54 is blanket deposited on the sacrificial gate dielectric layer 52 and on the fin structure 30 so that the fin structure 30 is completely buried in the sacrificial gate electrode layer 54. The sacrificial gate electrode layer 54 includes silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer 54 is in the range of about 100 nanometers to about 200 nanometers. In some embodiments, the sacrificial gate electrode layer 54 undergoes a planarization step. The sacrificial gate dielectric layer 52 and the sacrificial gate electrode layer 54 are formed by chemical vapor deposition (CVD) including low pressure chemical vapor deposition (LPCVD) and plasma assisted chemical vapor deposition (PECVD), or physical gas It is formed by phase deposition (PVD), atomic layer deposition (ALD) or other suitable processes. Next, a mask layer is formed on the sacrificial gate electrode layer 54. The mask layer includes a pad SiN layer 56 and a pad SiN layer 56 on the pad SiN layer. A silicon oxide mask layer 58.

Then, a patterning step is performed on the mask layer. As shown in FIG. 9, the pattern of the mask layer is transferred to the sacrificial gate electrode layer 54 to form a sacrificial gate structure 50. The sacrificial gate structure 50 includes a sacrificial gate dielectric layer 52, a sacrificial gate electrode layer 54 (for example, polysilicon), a pad silicon nitride layer 56 and a silicon oxide mask layer 58. By patterning the sacrificial gate structure, the stacked layers of the first semiconductor layer and the second semiconductor layer are partially exposed on the opposite side of the sacrificial gate structure 50, thereby defining source/drain regions ( source/drain regions), as shown in Figure 9. In this disclosure, the terms source and drain can be used interchangeably, and their structures are roughly the same. In Figure 9, one sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged along the X direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve the pattern fidelity.

As shown in FIG. 10, after the sacrificial gate structure is formed, a blanket layer 53 containing an insulating material is formed by chemical vapor deposition (CVD) or other suitable processes. After that, the carpet layer 53 is patterned to form sidewall spacers 55 (refer to FIGS. 11A and 11C). The blanket layer 53 is deposited in a conformal manner so that it has substantially the same thickness on the vertical surfaces of the sacrificial gate structure 50, such as the sidewalls, the horizontal surface, and the top. In some embodiments, the blanket layer 53 is deposited to a thickness ranging from about 2 nanometers to about 10 nanometers. In one embodiment, the insulating material of the blanket layer 53 is a silicon nitride-based material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxynitride (SiOCN) or silicon carbide nitride (SiCN) and the aforementioned combination.

Furthermore, as shown in FIGS. 11A-11C, sidewall spacers 55 are formed on the opposite sidewalls of the sacrificial gate structure 50, and then the fin structure of the source/drain (S/D) region is recessed downward To below the upper surface of the isolation insulating layer 40. FIG. 11B is a cross-sectional view corresponding to the area A1 and line segment X1-X1 in FIG. 11A, and FIG. 11C is a cross-sectional view corresponding to the line segment Y1-Y1 in FIG. 11A. In FIG. 11B, a cross-sectional view of the bottom portion of a sacrificial gate structure 50 is shown.

After the blanket layer 53 is formed (for example, as shown in FIG. 10), etching (anisotropic etching) is performed on the blanket layer 53 by using, for example, reactive ion etching (RIE). During the etching process, most of the insulating material is removed from the horizontal surface, leaving a dielectric spacer layer on the vertical surface, such as on the sidewalls of the sacrificial gate structure 50 and the exposed fin structure Leave the dielectric spacer layer. The mask layer 58 may be exposed from the sidewall spacers. In some embodiments, isotropic etching may be performed to remove the insulating material from the upper portion of the source/drain (S/D) region of the exposed fin structure 30.

Then, the fin structure of the source/drain (S/D) region is recessed below the upper surface of the isolation insulating layer 40 by dry etching and/or wet etching . As shown in FIGS. 11A and 11C, the sidewall spacer 55 formed on the source/drain (S/D) region of the exposed fin structure is partially left. However, in some other embodiments, the sidewall spacers 55 formed on the source/drain (S/D) regions of the exposed fin structure are all removed. In this step, as shown in FIG. 11B, the end portions of the stacked layers of the first semiconductor layer 20 and the second semiconductor layer 25 under the sacrificial gate structure 50 have end portions flush with the sidewall spacers 55 Its roughly flat surface. In some embodiments, the end portions of the stacked layers of the first semiconductor layer 20 and the second semiconductor layer 25 are slightly horizontally etched.

Next, as shown in FIGS. 12A-12C, the first semiconductor layer 20 is horizontally recessed (e.g., etched), so that the edges of the first semiconductor 20 are substantially located on one side surface of the sacrificial gate electrode layer 54 Down. As shown in FIG. 12B, the end portion (eg, edge) of the first semiconductor layer 20 under the sacrificial gate structure is substantially flush with the side surface of the sacrificial gate electrode layer 54.

As shown in FIG. 12B, during the recess etching of the first semiconductor layer 20 and/or the recess etching of the first semiconductor layer and the second semiconductor layer described in FIGS. 11A-11C, the first The end portion of the second semiconductor layer 25 is also etched horizontally. The recessed amount of the first semiconductor layer 20 is greater than the recessed amount of the second semiconductor layer 25.

In some embodiments, the recessed depth D1 of the first semiconductor layer 20 is between about 5 nanometers and about 10 nanometers from the plane containing one sidewall spacer 55, and self-contains one sidewall spacer 55 From the plane, the recessed depth D2 of the second semiconductor layer 25 is in the range of about 1 nanometer to about 4 nanometers. In some embodiments, the difference D3 between the depth D1 and the depth D2 is in the range of about 1 nanometer to about 9 nanometers. Note that in some specific embodiments, the first and second semiconductor layers are not etched (recessed horizontally). In some other embodiments, the etching amount of the first semiconductor layer and the second semiconductor layer are substantially the same (the difference is less than about 0.5 nm).

As shown in FIGS. 13A-13C, after the first semiconductor layer 20 is recessed horizontally, an inner spacer 69 is formed on the recessed surface of the first semiconductor layer 20. The aforementioned inner spacer 69 is formed by conformally forming an insulating layer on the etched side ends of the first semiconductor layer 20 and the second semiconductor layer 25 and on the sacrificial gate structure 50. The aforementioned insulating layer includes one or more of silicon nitride and silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide oxynitride (SiCN), silicon oxynitride (SiOCN), or any other suitable Dielectric materials. The insulating layer of the aforementioned inner spacer 69 is made of a different material from the sidewall spacer 55. The insulating layer can be formed by atomic layer deposition or any other suitable method. After forming the aforementioned insulating layer, an etching step is performed to partially remove the insulating layer, thereby forming inner spacers 69, as shown in FIG. 13B. The inner spacer 69 has a thickness in the range of about 1.0 nm to about 10.0 nm. In other embodiments, the inner spacer 69 has a thickness in the range of about 2.0 nm to about 5.0 nm.

As shown in FIGS. 13A-13C, in some embodiments, a liner epitaxial layer 70 is also formed on the sidewall of the inner spacer 69 and on the recessed surface of the second semiconductor layer 25. The liner epitaxial layer 70 is used to optimize the short channel effect and performance of the transistor. The liner epitaxial layer 70 is also formed on the recessed fin structure in the source/drain (S/D) region. In some embodiments, the liner epitaxial layer 70 is selectively grown on the semiconductor layer and includes undoped silicon. In some other embodiments, the liner epitaxial layer 70 includes one or more layers of silicon, silicon phosphide (SiP), and silicon carbide phosphide (SiCP). In some specific embodiments, the liner epitaxial layer 70 includes one or more layers of silicon germanium (SiGe) and germanium. In some embodiments, the thickness of the liner epitaxial layer 70 on the recessed surface of the first semiconductor layer 20 is in the range of about 5 nm to about 10 nm. The thickness of the liner epitaxial layer 70 on the recessed surface of the second semiconductor layer 25 is in the range of about 1 nm to about 4 nm. The thickness of the liner epitaxial layer 70 on the recessed surface of the second semiconductor layer 25 is about 20% to about 60% of the thickness of the liner epitaxial layer 70 on the recessed surface of the first semiconductor layer 20.

As shown in FIG. 14, after forming the liner epitaxial layer 70, source/drain epitaxial layers 80 are formed. In an n-channel FET, the source/drain (S/D) epitaxial layer 80 includes one or more layers of silicon, silicon phosphide (SiP), silicon carbide (SiC) and Silicon carbide phosphide (SiCP); or, in a p-channel FET (p-channel FET), the source/drain (S/D) epitaxial layer 80 includes one or more layers of silicon, silicon germanium ( SiGe), germanium. The source/drain epitaxy layer 80 can be formed by an epitaxial growth method using chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). As shown in FIG. 14, the source/drain epitaxial layer 80 grows from the liner epitaxial layer 70 formed on the corresponding bottom surface of the two fin structure. In some embodiments, the aforementioned grown epitaxial layer is merged on the isolation insulating layer, and a void 82 is formed. The source/drain epitaxial layer 80 and the liner epitaxial layer 70 together form the source/drain S/D features of the wrap-around gate field effect transistor device (GAA FET device).

Next, as shown in FIG. 15, a second liner layer (second liner layer) 90 is formed, and then an interlayer dielectric (ILD) layer 95 is formed. The second liner layer 90 includes a silicon nitride-based material, such as silicon nitride, and serves as a contact etch stop layer in the next etching step. The material of the interlayer dielectric layer 95 includes compounds including silicon, oxygen, carbon, and/or hydrogen, such as silicon oxide, silicon oxycarbide (SiCOH), and silicon oxycarbide (SiOC). Organic materials, such as polymers, can be used for the interlayer dielectric layer 95. After forming the interlayer dielectric layer 95, a planarization step, such as chemical mechanical polishing (CMP), is performed to expose the top portion of the sacrificial gate electrode layer 54.

Next, as shown in FIG. 16, the sacrificial gate electrode layer 54 and the sacrificial gate dielectric layer 52 are removed, thereby exposing the fin structure. In the process of removing the sacrificial gate structure, the interlayer dielectric layer 95 protects the source/drain epitaxial layer 80. The sacrificial gate structure can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer 54 is polysilicon and the interlayer dielectric layer 95 is silicon oxide, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 54. The sacrificial gate dielectric layer 52 is then removed using a plasma dry process and/or a wet process.

As shown in Figures 17A and 17B, Figure 17B is a cross-sectional view along the fin structure. After the sacrificial gate structure is removed, the first semiconductor layer 20 in the fin structure is removed, thereby forming a second semiconductor layer 25 of the semiconductor channel layer. This step of removing the first semiconductor layer 20 can also be referred to as a wire release step or a sheet formation step (for example, a nanosheet formation step). An etchant that can selectively etch the first semiconductor layer 20 with respect to the second semiconductor layer 25 is used to remove or etch the first semiconductor layer 20. When the first semiconductor layer 20 includes germanium or silicon germanium (SiGe), and the second semiconductor layer 25 includes silicon, the first semiconductor layer 20 can be selectively removed by a wet etchant, such as But it is not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP) or potassium hydroxide (KOH) solutions. In another embodiment, when the first semiconductor layer 20 includes silicon and the second semiconductor layer 25 includes germanium or silicon germanium (SiGe), the first semiconductor layer 20 can be selectively treated with a wet etchant, such as but It is not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP) or potassium hydroxide (KOH) solution. .

In this embodiment, since the liner epitaxial layer 70 (for example, silicon) is formed, the etching of the first semiconductor layer 20 (for example, silicon germanium (SiGe)) stops at the liner epitaxial layer 70. When the first semiconductor layer 20 includes silicon, the pad epitaxial layer 70 may include silicon germanium (SiGe) or germanium. Since the etching of the first semiconductor layer 20 stops at the liner epitaxial layer 70, contact or bridging between the gate electrode and the source/drain (S/D) epitaxial layer can be avoided. After the semiconductor channel layer of the second semiconductor layer 25 is formed, a gate dielectric layer 102 is formed around each semiconductor channel layer, and a gate electrode layer 104 is formed on the gate dielectric layer 102 , As shown in Figure 18.

In some specific embodiments, the gate dielectric layer 102 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, and other suitable dielectric materials. Materials, and/or combinations of the foregoing. Examples of high dielectric constant dielectric materials include hafnium dioxide (HfO ₂ ), hafnium silicate (HfSiO), hafnium oxycarbide silicide (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanide (HfTiO), Hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃ ) alloy, other suitable high-permittivity dielectric materials, and/or the foregoing的组合。 The combination. In some embodiments, the gate dielectric layer 102 includes an interfacial layer formed between the channel layer and the dielectric material.

The gate dielectric layer 102 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable processes. In one embodiment, the gate dielectric layer 102 is formed using a highly conformal deposition process such as atomic layer deposition (ALD) to ensure that the formed gate dielectric layer has a uniform shape around each channel layer. thickness. In one embodiment, the thickness of the gate dielectric layer 102 is in the range of about 1 nm to about 6 nm.

The gate electrode layer 104 is formed on the gate dielectric layer 102 and surrounds each channel layer. The gate electrode layer 104 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicide (TaSiN), metal alloys, other suitable materials, and/or The aforementioned combination.

The gate electrode layer 104 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), electro-plating, or other suitable processes. The gate electrode layer is also deposited on the upper surface of the interlayer dielectric layer 95. Then, using, for example, chemical mechanical polishing (CMP), the gate dielectric layer and the gate electrode layer formed on the interlayer dielectric layer 95 are planarized until the top surface of the interlayer dielectric layer 95 is exposed.

As shown in FIG. 18, after the planarization step, the gate electrode layer 104 is recessed, and a cap insulating layer 106 is formed on the recessed gate electrode layer 104. The cover insulating layer 106 includes one or more layers of a material mainly made of silicon nitride, such as silicon nitride. The cover insulating layer 106 can be formed by depositing an insulating material and then performing a planarization step.

In some specific embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 102 and the gate electrode layer 104. The work function adjustment layer is made of conductive materials, such as a single layer of titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium carbide (TiC), tantalum carbide (TaC), cobalt ( Co), aluminum (Al), titanium aluminum (TiAl), hafnium titanium (HfTi), titanium silicide (TiSi), tantalum silicide (TaSi) or titanium aluminum carbide (TiAlC), or multiple layers of two or more of the foregoing Material. In n-channel field effect transistors, tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN), titanium carbide (TiC), cobalt (Co), titanium aluminum (TiAl), One or more of hafnium titanium (HfTi), titanium silicide (TiSi), and tantalum silicide (TaSi) serves as a work function adjustment layer. In the p-channel field effect transistor, titanium aluminum carbide (TiAlC), aluminum (Al), titanium aluminum (TiAl), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), titanium nitride (TiN) are used ), one or more of titanium carbide (TiC) and cobalt (Co) as the work function adjustment layer. The work function adjustment layer can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), e-beam evaporation, or other suitable processes. Furthermore, the work function adjustment layer can be separately formed in the n-type channel field effect transistor and the p-type channel field effect transistor using different metal layers.

Next, as shown in FIG. 19, dry etching is used to form contact holes 110 in the interlayer dielectric layer 95. In some embodiments, the upper portion of the source/drain epitaxial layer 80 is etched. As shown in FIG. 20, a silicide layer 120 is formed on the source/drain epitaxial layer 80. The aforementioned silicide layer 120 includes one or more of silicon tungsten (WSi), silicon cobalt (CoSi), silicon nickel (NiSi), silicon titanium (TiSi), silicon molybdenum (MoSi), and silicon tantalum (TaSi). Next, as shown in FIG. 21, a conductive material 130 is formed in the contact hole. The conductive material 130 includes one or more of cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), titanium nitride (TiN) And tantalum nitride (TaN).

Figures 22A-22C show cross-sectional views of the structure shown in Figure 21. FIG. 22A shows a cross-sectional view of the gate cut along the Y direction, FIG. 22B shows a cross-sectional view of the gate cut along the X direction, and FIG. 22C shows a cross-sectional view of the source/drain region cut along the Y direction.

As shown in FIG. 22A, the semiconductor channel layer made of the second semiconductor layer 25 is stacked in the Z direction. The aforementioned semiconductor channel layer can also be referred to as a multi-bridge channel, multiple nanoslabs, multiple nanosheets, multiple wires (e.g., having round, square, Hexagonal or other cross-sectional shapes). It is understandable that when the first semiconductor layer 20 is removed, the second semiconductor layer 25 will also be etched, so the corners of the second semiconductor layer 25 are rounded. The interface layer 102A wraps around each wire, and the gate dielectric layer 102B covers the interface layer 102A. Although the gate dielectric layer 102B surrounding a wire in Figure 22A is in contact with the gate dielectric layer 102B of an adjacent wire, the structure is not limited to Figure 22A. In some other embodiments, the gate electrode 104 also wraps around each wire covered by the interface layer 102A and the gate dielectric layer 102B.

As shown in FIG. 22B, the pad epitaxial layer 70 is formed between the source/drain epitaxial layer 80 and the wire (the second semiconductor layer 25). In some embodiments, the thickness T1 of the pad epitaxial layer 70 at the part between the wires is in the range of about 5 nm to about 10 nm, and the pad epitaxial layer 70 at the end of the wire is recessed The thickness T2 is in the range of about 1 nanometer to about 4 nanometers. In some embodiments, the difference T3 between the thickness T1 and the thickness T2 is in the range of about 1 nanometer to about 9 nanometers. In some specific embodiments, the thickness T2 is about 20% to about 60% of the thickness T1, and in some other embodiments, the thickness T2 is about less than 40% of the thickness T1.

In the embodiment of the process shown in FIGS. 1 to 22C, a wrap-around gate field effect transistor (GAA FET) includes a patterned insulating layer 14' and a patterned semiconductor-containing layer 16' (such as an SOI substrate). However, in some other embodiments, the patterned semiconductor-containing layer 16' (such as an SOI substrate) may be omitted. In these embodiments, for example, as shown in FIGS. 23A to 23C, the formed wrap-around gate field effect transistor (GAA FET) includes a patterned insulating layer 14', but no patterned semiconductor-containing layer 16' ( Such as SOI substrate). Regardless of the foregoing embodiments, the formed wrap-around gate field effect transistor has many advantages. For example, the present disclosure relates to but is not limited to a multi-gate field effect transistor. One example is a wrap-around gate field effect transistor. In a wrap-around gate field effect transistor, a plurality of semiconductor channel layers are vertically suspended on a semiconductor substrate below. A gate structure (including a gate electrode layer and a gate dielectric layer) is formed in the space between vertically adjacent semiconductor channels. The embodiment of the present disclosure proposes that at least one insulating layer is disposed between the bottommost gate structure and the underlying semiconductor substrate, where the bottommost gate structure refers to the gate closest to the underlying semiconductor substrate structure. The aforementioned at least one insulating layer disposed between the bottommost gate structure and the semiconductor substrate below can reduce the leakage current in the wrap-around gate field-effect transistor, and minimize the semiconductor substrate and the surrounding gate field-effect transistor. The size of a parasitic PN junction between the source/drain region and the ratio of the turn-on current to the turn-off current of the wrap-around gate field effect transistor (I _ON /I _OFF ratio) are improved. It is understandable that the wrap-around gate field effect transistor will subsequently go through more complementary metal oxide semiconductor (CMOS) processes to form different features, such as contacts/vias and interconnections. Interconnect metal layer, dielectric layer, passivation layer, etc.

FIG. 24 shows a flowchart of a method for forming a multi-gate FET (multi-gate FET) according to an embodiment of the disclosure. As shown in FIG. 24, this forming method includes a step 240 of forming an insulating layer on a semiconductor substrate, and a step 242 of forming a semiconductor-containing substrate on the aforementioned insulating layer. The forming method further includes a step 244 of forming a stack on the aforementioned semiconductor-containing substrate. The stack includes a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layers and the second semiconductor layers have different The material composition is arranged alternately with each other in the stack. In step 246 of the forming method shown in FIG. 24, it includes patterning the aforementioned insulating layer, the aforementioned semiconductor-containing substrate, and the aforementioned stack including the first semiconductor layer and the second semiconductor layer to form a fin. A fin structure. The fin structure includes sacrificial layers containing these first semiconductor layers and channel layers containing these second semiconductor layers. The forming method further includes a step 248 of forming source/drain features on the channel layers adjacent to the fin structure, and removing the sacrificial layers of the fin structure, so that the fin structure Step 250 of exposing the channel layers. Step 252 of the forming method shown in FIG. 24 includes forming a gate structure around the exposed channel layers, wherein a bottom surface of the semiconductor-containing substrate physically contacts the insulating layer A top surface of the above-mentioned insulating layer and the above-mentioned semiconductor-containing substrate are disposed between a bottommost portion of the above-mentioned gate structure and the above-mentioned semiconductor substrate.

In one embodiment, the present disclosure provides a method for forming a semiconductor device. The method includes forming an insulating layer on a semiconductor substrate; forming a semiconductor-containing substrate on the insulating layer; forming a semiconductor-containing substrate on the semiconductor-containing substrate; A stack of semiconductor layers, in which the first semiconductor layers and the second semiconductor layers have different material compositions and are alternately arranged in the foregoing stack; for the foregoing insulating layer, the foregoing semiconductor-containing substrate, and the foregoing The foregoing stack of the first semiconductor layer and the second semiconductor layers is patterned to form a fin structure. The fin structure includes sacrificial layers containing the first semiconductor layers and Channel layers containing these second semiconductor layers; forming source/drain features (source/drain features) on the channel layers adjacent to the aforementioned fin structure; removing these sacrificial layers of the aforementioned fin structure , Exposing the channel layers of the aforementioned fin structure; and forming a gate structure (gate structure) surrounding the exposed channel layers, wherein a bottom surface of the aforementioned semiconductor-containing substrate is in physical contact with a portion of the aforementioned insulating layer On the top surface, the insulating layer and the semiconductor-containing substrate are disposed between a bottommost portion of the gate structure and the semiconductor substrate.

In one embodiment, the aforementioned semiconductor-containing substrate includes a semiconductor-on-insulator (SOI) substrate. In one embodiment, a dielectric layer of the aforementioned semiconductor-on-insulator (SOI) substrate has a different composition from the aforementioned insulating layer. In one embodiment, the insulating layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbon nitride. ), fluorine-doped silicate glass, and the aforementioned combination. In one embodiment, the bottom portions of the source/drain features (bottom portions of the source/drain features) physically contact the sidewalls of the aforementioned insulating layer and the aforementioned sidewalls of the semiconductor-containing substrate. In one embodiment, the first one of the source/drain components is laterally separated from the second one of the source/drain components by a separation distance, wherein the aforementioned The thickness of the semiconductor-containing substrate is in the range of about 0.4 times the aforementioned separation distance to about 0.6 times the aforementioned separation distance. In one embodiment, the separation distance is a gate length of a transistor device, and the transistor device includes the fin structure and the gate structure. In one embodiment, the step of forming the source/drain features in the channel layers adjacent to the fin structure in the foregoing method includes: forming a sacrificial gate structure on the fin structure , So that the sacrificial gate structure covers a first part of the fin structure, while the second part of the fin structure remains exposed; the fins that are not covered by the sacrificial gate structure are removed For these second parts of the structure, the aforementioned removal is to expose the part of the aforementioned semiconductor substrate; the sacrificial layers are recessed horizontally so that the edges of the sacrificial layers are located below the aforementioned sacrificial gate structure; here An inner spacer is formed on the recessed surfaces of the sacrificial layers; a liner epitaxial layer is formed on the exposed portions of the semiconductor substrate; and the liner epitaxial layer is formed on the liner These source/drain components are formed on the epitaxial layer. In one embodiment, in the method for forming a semiconductor device, the liner epitaxial layer includes undoped silicon.

In another embodiment, the present disclosure provides a method for forming a semiconductor device. The method includes: forming a dielectric-containing substrate on a semiconductor substrate; forming a plurality of first semiconductor layers and a second semiconductor layer in a first direction above the semiconductor substrate. Between the first semiconductor layers; the first semiconductor layers and the second semiconductor layer are patterned to form a fin structure, so that the fin structure includes the first semiconductor layers Sacrificial layers of the semiconductor layer and a channel layer containing the aforementioned second semiconductor layer; a sacrificial gate structure is formed on the aforementioned fin structure, so that the aforementioned sacrificial gate structure Cover a part of the aforementioned fin structure, while the remaining part of the aforementioned fin structure remains exposed; remove the remaining part of the aforementioned fin structure; at least form a recessed surface on the sacrificial layer Inner spacer; forming a source/drain region adjacent to the inner spacer and the channel layer; removing the sacrificial gate structure; removing the sacrificial gate structure after removing the sacrificial gate structure The sacrificial layers in the aforementioned fin structure expose the aforementioned channel layer and are suspended over the aforementioned dielectric-containing substrate; and form a gate dielectric layer and a gate A gate electrode layer surrounds the exposed channel layer, wherein a bottom surface of the dielectric-containing substrate physically contacts a top surface of the semiconductor substrate, wherein in the first direction, the The gate dielectric layer and the gate electrode layer are arranged between the substrate containing the dielectric and the channel layer.

In one embodiment, the substrate containing the dielectric includes a first layer and a second layer located on the first layer. The first layer physically contacts the semiconductor substrate, and the first layer And the aforementioned second layer has a different composition. In one embodiment, the aforementioned first layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride. Nitride, fluorine-doped silicate glass, and a combination of the foregoing. In one embodiment, the aforementioned second layer includes a semiconductor-on-insulator (SOI) substrate. In one embodiment, a thickness of the second layer in the first direction is about 0.4 times the size of the gate electrode layer in a second direction to a thickness of the gate electrode layer in the second direction. In the range of about 0.6 times the size, the second direction is perpendicular to the first direction. In an embodiment, a thickness of the aforementioned second layer in the first direction is in the range of 3 nanometers to 7 nanometers. In one embodiment, the aforementioned inner spacer includes a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), carbon nitride A group consisting of silicon oxide (SiOCN) and the aforementioned combination.

In another embodiment, the present disclosure provides a semiconductor device. The semiconductor device includes: a dielectric-containing substrate on a semiconductor substrate; channel layers are vertically suspended on the aforementioned dielectric-containing substrate, and a bottommost channel The layer is vertically separated from the aforementioned dielectric-containing substrate by a space; a first source/drain region (first source/drain region) is located on the aforementioned semiconductor substrate, and the first source The electrode/drain region is in contact with the first ends of the aforementioned channel layer; a second source/drain region (second source/drain region) is located on the aforementioned semiconductor substrate, and the second source/drain region The region is in contact with the second ends of the aforementioned channel layer; a gate dielectric layer is located on the aforementioned channel layer and surrounds each channel layer; and a gate electrode layer is located on the aforementioned gate On the dielectric layer, and the gate electrode layer surrounds each channel layer, wherein the gate dielectric layer and the gate electrode layer surrounding the bottommost channel layer are located on the substrate containing the dielectric substance and the bottommost channel In the aforementioned space between the layers, the aforementioned dielectric-containing substrate is in physical contact with the aforementioned semiconductor substrate.

In one embodiment, the aforementioned dielectric-containing substrate includes a first material selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. , Silicon carbon nitride, fluorine-doped silicate glass, fluorine-doped silicate glass, and a combination of the foregoing. In one embodiment, the aforementioned dielectric-containing substrate further includes a semiconductor-on-insulator (SOI) substrate disposed on the aforementioned first material, and the semiconductor-on-insulator (SOI) substrate is in physical contact with the aforementioned first material. In one embodiment, the aforementioned channel layer includes silicon or a Si-based compound.

The components of several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. . Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can do various things without departing from the spirit and scope of the present invention. Such changes, substitutions and replacements. Therefore, the scope of protection of the present invention shall be subject to the definition of the attached patent scope.

10: semiconductor substrate 10': well 12: impurity ions 14: insulating layer 14': patterned insulating layer 15: mask layer 15A: first mask layer 15B: second mask layer 15': patterned mask Layer 16: semiconductor-containing layer 16': patterned semiconductor-containing layer 20: first semiconductor layer 25: second semiconductor layer 30: fin structure 35: first liner layer 40: isolation insulating layer 41: insulating material layer 50: Sacrificial gate structure 52: sacrificial gate dielectric layer 53: blanket layer 54: sacrificial gate electrode layer 55: sidewall spacer 56: pad silicon nitride layer 58: (silicon oxide) mask layer 69: inner spacer Object 70: liner epitaxial layer 80: source/drain epitaxial layer 82: hole 90: second liner layer 95: interlayer dielectric layer 102: gate dielectric layer 102A: interface layer 104: gate electrode Layer 106: cover insulating layer 110: contact hole 120: silicide layer 130: conductive material X1-X1, Y1-Y1: profile line segment L _G : length T1, T2, T3: thickness (thickness difference) W1: width H: Height D1, D2, D3: depth (depth difference) X, Y, Z: direction 240, 242, 244, 246, 248, 250, 252: step

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practices, many features are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14, 15, 16, 17A, 17B, 18 , 19, 20, 21, 22A, 22B, and 22C show an exemplary continuous process for manufacturing a wrap-around gate field effect transistor (GAA FET) device according to an embodiment of the present disclosure. Figures 23A, 23B, and 23C show a wrap-around gate field effect transistor (GAA FET) device according to another embodiment of the present disclosure. FIG. 24 shows a flowchart of a method for forming a multi-gate FET (multi-gate FET) according to an embodiment of the disclosure.

240,242,244,246,248,250,252: steps

Claims (1)

A method for forming a semiconductor device includes: Forming an insulating layer on a semiconductor substrate; A semiconductor-containing substrate is formed on the insulating layer; A stack including a first semiconductor layer and a second semiconductor layer is formed on the semiconductor-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with each other in the stack set up; The insulating layer, the semiconductor-containing substrate, and the stack including the first semiconductor layers and the second semiconductor layers are patterned to form a fin structure, the fin structure including Sacrificial layers containing the first semiconductor layers and channel layers containing the second semiconductor layers; Forming source/drain features (source/drain features) on the channel layers adjacent to the fin structure; Removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and A gate structure is formed to surround the exposed channel layers, wherein a bottom surface of the semiconductor-containing substrate physically contacts a top surface of the insulating layer, wherein the insulating layer and the semiconductor-containing substrate are It is arranged between a bottommost portion of the gate structure and the semiconductor substrate.

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