TW202114269A - Display panel and display panel menufacturing method - Google Patents

Abstract

A display panel includes a substrate, a film layer, a seed pattern layer, a first conductive structure, a pattern film and a second conductive structure. The film layer with a plurality of openings is disposed on a first surface of the substrate. A plurality of blind holes penetrating the substrate respectively communicate with the openings. The seed pattern layer disposed on the film layer fills the openings. The first conductive structure disposed on the seed pattern layer fills the openings. The blind holes are overlapped with the first conductive structure. The pattern film overlaps the second surface of the substrate and the blind holes. The second conductive structure disposed on the pattern film fills the blind holes so as to be electrically connected to the first conductive structure or the seed pattern layer, which serves as a stopper layer of the second conductive structure.

Description

Display panel and display panel manufacturing method

The present invention relates to an electronic device and a manufacturing method of the electronic device, and more particularly to a display panel and a manufacturing method of the display panel.

Generally speaking, the display panel may have a display area and a non-display area located around the display area. The non-display area may include a wiring area to provide wiring and a drive circuit area to provide a drive circuit for driving active elements in the display panel, such as a source drive circuit or a gate drive circuit. Therefore, the non-display area of the display panel cannot Display images, and affect the appearance design of the display panel.

Specifically, when the area of the non-display area is reduced, the display area occupies a larger area of the display panel, and correspondingly more pixels are provided, so the resolution of the display panel can be improved. When the area of the non-display area is reduced, the boundary of the display area is closer to the outer edge of the display panel, so a narrow frame design can be realized. For large-scale display panels formed by splicing, the non-display area forms a splicing gap that cannot display images, causing discontinuity of the overall image and affecting the display quality. Therefore, the existing display panel still needs to be improved.

In an embodiment of the present invention, a display panel is provided, the structure of which helps reduce the size of the display panel and can improve the yield rate.

An embodiment of the present invention provides a display panel including a substrate, a film layer, a seed pattern layer, a first conductive structure, a pattern coating, and a second conductive structure. The substrate has a first surface and a second surface. The film layer is disposed above the first surface of the substrate, the film layer has a plurality of openings, and a plurality of blind holes penetrating the substrate are respectively communicated with the openings. The seed pattern layer is arranged above the film layer, and the seed pattern layer fills the opening. The first conductive structure is disposed above the seed pattern layer, the first conductive structure fills the opening, and the blind hole overlaps the first conductive structure. The pattern coating is overlapped on the second surface of the substrate and the blind hole. The second conductive structure is disposed above the pattern coating, and the second conductive structure is filled in the blind hole to be electrically connected to the first conductive structure.

An embodiment of the present invention provides a method for manufacturing a display panel, including forming a film layer above a first surface of a substrate, forming a seed layer above the film layer, forming a first conductive structure above the seed layer, A plurality of blind holes are formed, a surface treatment film is formed, a second conductive structure is formed above the surface treatment film, and the seed layer and the surface treatment film are patterned to form a seed pattern layer and a pattern film. The film layer has a plurality of openings. The seed layer fills the opening. The first conductive structure fills the opening. The blind holes penetrate the substrate and communicate with the openings respectively. The blind hole overlaps the first conductive structure. The surface treatment film covers a second surface of the substrate and the blind hole. The second conductive structure is filled in the blind hole to be electrically connected to the first conductive structure.

In the display panel of the embodiment of the present invention, the first conductive structure can be coupled to the second conductive structure by the blind hole penetrating through the substrate. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the lower surface of the substrate. In this way, components can be miniaturized in size. The first conductive structure and the support layer of the display panel are formed before the blind hole. Therefore, the first conductive structure and the support layer can improve the structural strength of the substrate, which is beneficial to the drilling of the blind hole and can improve the yield. In addition, since the support layer and the substrate cover the elements and film layers located in the display area on the first surface of the substrate, the subsequent process can prevent the elements and film layers located in the display area from being damaged, and the yield can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The directional terms mentioned in the embodiments, for example: "up", "down", "front", "rear", "left", "right", etc., are only directions with reference to the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention. In the drawings, each drawing depicts the general features of methods, structures, and/or materials used in specific exemplary embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these exemplary embodiments. For example, for the sake of clarity, the relative size, thickness, and position of each film layer, region, and/or structure may be reduced or enlarged.

In the embodiments, the same or similar elements will use the same or similar reference numerals, and the redundant description will be omitted. In addition, the features in different exemplary embodiments can be combined without conflict, and simple equivalent changes and modifications made in accordance with this specification or the scope of the patent application still fall within the scope of this patent. In addition, the terms "first" and "second" mentioned in this specification or the scope of the patent application are only used to name discrete elements or to distinguish different embodiments or ranges, and are not used to limit the number of elements. The upper limit or lower limit is not used to limit the manufacturing order or the arrangement order of the components.

FIGS. 1A to 17 are schematic diagrams of a manufacturing process of a partial area of a display panel 10 according to an embodiment of the present invention, in which FIGS. 1A, 2, 3, and 5 to 17 are schematic cross-sectional views, and FIG. 1B is a diagram A schematic top view of the display panel 10 in the manufacturing stage of 1A, and FIG. 4 is a schematic top view of the display panel 10 in another manufacturing stage.

1A and 1B, in this embodiment, a carrier substrate 100S is provided first, and then a substrate 100 is disposed on the carrier substrate 100S. In some embodiments, the arrangement of the carrier substrate 100S can also be omitted, and the substrate 100 can be provided directly. The substrate 100 is suitable for carrying other components. It may have a first surface 100T and a second surface 100B opposite to each other, and the normal direction of the first surface 100T and the second surface 100B of the substrate 100 may be parallel to the direction Z. In some embodiments, the substrate 100 may be a flexible substrate, for example, it may be a flexible substrate such as a polyimide (PI) substrate; in other embodiments, the substrate 100 may also be a rigid substrate. In some embodiments, the carrier substrate 100S may be a rigid substrate, such as a glass substrate or a plastic steel substrate, to provide a smooth surface. In some embodiments, as shown in FIG. 1B, the size of the carrier substrate 100S may be larger than the size of the substrate 100, and the substrate 100 may be divided into a display area AA and a non-display area NAA located around the display area AA.

As shown in FIG. 1A, thereafter, a pixel array structure layer 110 is formed on the first surface 100T of the substrate 100. In some embodiments, the pixel array structure layer 110 is located in the display area AA, but not limited to this. The pixel array structure layer 110 may include film layers 111 to 115, an active device T1, a conductor pattern CP1, and a connecting conductor layer 116. The active device T1 may include a semiconductor layer SE1, a source pattern S1, a drain pattern D1, and a gate pattern G1. In some embodiments, the formation process of the pixel array structure layer 110 may include sequentially forming the film layer 111, the semiconductor layer SE1, the film layer 112, the gate pattern G1, and the film layer 113, and then, forming the source electrode in sequence or sequentially. The pattern S1, the drain pattern D1, and the conductor pattern CP1, and then the film layers 114, 115 and the connecting conductor layer 116 are sequentially formed, but not limited to this. In some embodiments, the method for forming the pixel array structure layer 110 may involve a physical vapor deposition method or a chemical vapor deposition method; in some embodiments, the method for forming the pixel array structure layer 110 may involve a patterning process. In addition, the number of film layers or elements of the present invention is not limited to this, but can be appropriately adjusted according to different design considerations, and the film layers or elements can be a single-layer structure or a composite structure of multiple layers.

The film layer 111 is disposed on the substrate 100 and may be a buffer layer. The material constituting the buffer layer may generally be an insulating material, and may be an inorganic thin film composed of an inorganic material. The film layer 112 is disposed on the film layer 111, which may be a gate insulator (GI), and the material of the gate insulator layer is, for example, silicon oxide, silicon nitride or other insulating materials. The film layer 113 is disposed on the film layer 112, and it may be an inter-layer dielectric (ILD), and the material of the inter-layer dielectric layer may include an inorganic material, an organic material, or a combination thereof.

The film layer 114 is disposed on the film layer 113, which may be a planarization layer (PL), and the material constituting the planarization layer may include various suitable organic materials. The film layer 115 is disposed on the film layer 114, and its material may include various suitable inorganic materials to improve the degree of bonding with subsequent conductive materials or metal materials. The film layer 114 has a plurality of openings PG1 and PG2 to expose the film layer 111, and the film layer 114 has a plurality of contact holes HL1 to HL3 to expose the conductor pattern CP1, the source pattern S1 and the drain pattern D1. The material used to form the film layer 115 fills the openings PG1, PG2 and the contact holes HL1~HL3, but does not fill the openings PG1, PG2 and the contact holes HL1~HL3, that is, part of the film layer 115 is located in the openings PG1, PG2 And the contact holes HL1~HL3. In some embodiments, the sidewalls of the openings PG1 and PG2 defined by the film layer 114 can be inclined surfaces, so the cross-sectional areas of the openings PG1 and PG2 in the parallel XY plane can be changed; in some embodiments, the openings PG1 and PG2 extend from the top to the The bottom end is tapered, meaning that it is tapered toward the direction closer to the substrate 100 or fanned out toward the direction away from the substrate 100 (ie, direction Z); in some embodiments, the openings PG1, PG2 It is cone-shaped or a horn hole.

The active devices (such as the active devices T1) are disposed on the first surface 100T of the substrate 100 and arranged in an array. The active element T1 can be a bottom gate TFT, a top gate TFT, or other suitable types of thin film transistors. The semiconductor layer SE1 is disposed on the film layer 111, and the material of the semiconductor layer SE1 is, for example, polysilicon (such as low temperature crystalline silicon (LTPS)), amorphous silicon (amorphous silicon), and metal oxide semiconductor (such as indium gallium zinc). Oxide (Indium Gallium Zinc Oxide, IGZO) or other semiconductor materials. A part of the source pattern S1 and the drain pattern D1 are disposed on the film layer 113, and the other parts of the source pattern S1 and the drain pattern D1 penetrate the film layers 112 and 113 and contact the semiconductor layer SE1, respectively.

In some embodiments, the material of the conductor pattern CP1, the source pattern S1, the drain pattern D1, and the gate pattern G1 may be a single-layer or multilayer stacked conductive material; in some embodiments, based on the consideration of conductivity, the conductor The materials of the pattern CP1, the source pattern S1, the drain pattern D1, and the gate pattern G1 are generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, and oxynitride of metal materials. The connecting conductor layer 116 is disposed on the film layer 115, and is electrically connected to the conductor pattern CP1, the source pattern S1, and the drain pattern D1 through a plurality of contact holes HL1 to HL3, respectively.

Next, referring to FIG. 2, a seed layer 220 is comprehensively formed on the first surface 100T of the substrate 100, that is, the seed layer 220 completely overlaps the substrate 100 or the carrier substrate 100S. The seed layer 220 covers the film layers 111 and 115 and the connecting conductor layer 116. The material forming the seed layer 220 fills the openings PG1, PG2, but does not fill the openings PG1, PG2, that is, part of the seed layer 220 is located in the openings PG1, PG2. In some embodiments, the seed layer 220 may be a conductive material layer; in some embodiments, the material of the seed layer 220 is generally a metal material or alloy, a nitride of a metal material, an oxide of a metal material, or a metal material. Other conductive materials such as oxynitride. In some embodiments, the method for forming the seed layer 220 may include a physical vapor deposition method or a chemical vapor deposition method. In some embodiments, the seed layer 220 is located at least in the display area AA; in some embodiments, the seed layer 220 is located in the display area AA and the non-display area NAA. In some embodiments, the thickness of the seed layer 220 is approximately between 1 μm and 2 μm.

Next, referring to FIG. 3, a first photoresist pattern 330 is formed on the seed layer 220. In other words, the first photoresist pattern 330 is located above the first surface 100T of the substrate 100. In some embodiments, the material of the first photoresist pattern 330 can be positive photoresist or negative photoresist; in some embodiments, the first photoresist pattern 330 can be liquid photoresist or dry film. . The first photoresist pattern 330 partially overlaps the seed layer 220 in the direction Z and partially exposes the seed layer 220. The first photoresist material pattern 330 has a plurality of first trenches TR1~TR4, and the first trenches TR1~TR4 respectively expose openings PG1, PG2 or contact holes HL1~HL3 and are respectively connected to openings PG1, PG2 or contact holes HL1 ~HL3. In some embodiments, the first photoresist pattern 330 does not overlap with the openings PG1, PG2 or the contact holes HL1~HL3 in the direction Z; in some embodiments, the first photoresist pattern 330 does not overlap with the openings PG1, PG2 or the contact holes HL1~HL3 in the direction Z. The contact holes HL1~HL3 completely overlap; in some embodiments, the first trenches TR1~TR4 respectively overlap the openings PG1, PG2 or the contact holes HL1~HL3 in the direction Z; in some embodiments, the first trench TR1 ~TR4 overlaps with the connecting conductor layer 116 in the direction Z. The first photoresist material pattern 330 may include a plurality of columnar bodies, for example, a first columnar body 330P. In some embodiments, the sidewalls of the first columnar body 330P may be inclined surfaces, and the cross-sectional area of the first columnar body 330P in the parallel XY plane can be changed; in some embodiments, the first columnar body 330P is from the bottom end to The top end is tapered, meaning that it is tapered in the direction away from the seed layer 220 (that is, direction Z) or fan out in the direction close to the seed layer 220; in some embodiments, the first A columnar body 330P has a cone shape. In order to improve the accuracy of the production of the first photoresist pattern 330, in some embodiments, the first columnar body 330P is formed by a large substrate yellow light-defined pattern, and furthermore, it is formed in a high-precision yellow light manufacturing process; In some embodiments, the photoresist is patterned by an exposure and development process to form the first columnar body 330P of the first photoresist pattern 330.

Next, referring to FIG. 4, a plurality of alignment marks 410 are formed on the substrate 100. The alignment mark 410 is located in the non-display area NAA, which can be used as a reference point for positioning or alignment in the subsequent manufacturing process. In some embodiments, the alignment mark 410 may be a through hole that penetrates the substrate 100. In this way, whether it is the production of elements or films on the first surface 100T side of the substrate 100 or the second surface 100B side of the substrate 100 The production of components or film layers can be based on the alignment mark 410, and the production yield can be ensured. In some embodiments, the alignment mark 410 may be omitted. Next, referring to FIG. 5, the carrier substrate 100S is removed from the substrate 100, that is, the release process is performed. In some embodiments, the release process can be performed by laser or physical stripping.

Next, referring to FIG. 6, a plurality of first conductive structures 640S1 to 640S4 are formed on the first surface 100T of the substrate 100. In some embodiments, based on the consideration of conductivity, the material of the first conductive structure 640S1 to 640S4 is generally a metal material or alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, etc. Material; In some embodiments, the material of the first conductive structure 640S1 to 640S4 is copper. In some embodiments, the method for forming the first conductive structures 640S1 to 640S4 may include thick film formation techniques such as electroplating; in some embodiments, the method for forming the first conductive structures 640S1 to 640S4 may include physical vapor deposition or Chemical vapor deposition method. In some embodiments, the seed layer 220 facilitates the formation of the first conductive structures 640S1 to 640S4, or can improve the uniformity of the formation of the first conductive structures 640S1 to 640S4 (meaning that the entire surface is evenly plated with copper), or can strengthen the first conductive structure. The combination of the conductive structures 640S1 to 640S4 and the substrate 100. The first conductive structures 640S1 to 640S4 cover part of the seed layer 220, and the first trenches TR1 to TR4 of the first photoresist material pattern 330 and the opening PG1 of the film layer 114 are filled with the material forming the first conductive structures 640S1 to 640S4 PG2 to make the first conduction structure 640S1~640S4. Among them, the film layer 114, the seed layer 220, and the first conductive structures 640S1 to 640S4 fill the openings PG1 and PG2, and the first conductive structures 640S1 to 640S4 fill the openings PG1 and PG2. In addition, the first conductive structures 640S1 to 640S4 fill the first trenches TR1 to TR4 of the first photoresist material pattern 330 to be fitted with the first trenches TR1 to TR4, that is, the first photoresist material pattern 330 can be The seed layer 220 is blocked from contacting the electroplating solution, so that the first conductive structures 640S1 to 640S4 have a patterned structure. In some embodiments, since the first columnar body 330P of the first photoresist material pattern 330 and the sidewalls of the openings PG1 and PG2 are inclined surfaces, the sidewalls of the first conductive structures 640S1 to 640S4 are also inclined surfaces, that is, the first conductive structure 640S1 The cross-sectional area of ~640S4 in the parallel XY plane can be changed; in some embodiments, the first conductive structures 640S1~640S4 gradually become thicker from the bottom end to the top end, which means that it faces away from the first surface 100T of the substrate 100 (that is, the direction Z) The upper fan out or tapered toward the direction close to the first surface 100T of the substrate 100; in some embodiments, the first conductive structures 640S1 to 640S4 are tapered. In this way, the first conductive structures 640S1 to 640S4 can ensure the yield and production efficiency of subsequent micro bonding processes (such as micro bump bonding or micro light emitting diode bonding, etc.). In some embodiments, the aperture d1 of the first conductive structure 640S1 (that is, the aperture near the bottom end of the substrate 100) is approximately between 30 microns (micrometer, µm) and 80 microns; in some embodiments, the first conductive structure The aperture d1 of the 640S1 is approximately less than 150 microns, where the aperture can be diameter, diagonal length, edge width or other geometric features. In some embodiments, the thickness TH1 of the first conductive structure 640S1 to 640S4 is greater than 10 microns; in some embodiments, the thickness TH1 of the first conductive structure 640S1 to 640S4 is greater than 20 microns; in some embodiments, The thickness TH1 of the first conductive structure 640S1 to 640S4 is much larger than the thickness of the seed layer 220; in some embodiments, the thickness TH1' of the first conductive structure 640S1, 640S3 is greater than 10 microns. The thicker thickness TH1 of the first conductive structure 640S1 to 640S4 can reduce the resistance value of the wiring on the first surface 100T of the substrate 100, and can carry a large current, thereby achieving high current density driving. In addition, the thicker thickness TH1 of the first conductive structures 640S1 to 640S4 facilitates the subsequent micro-bonding process, because the first conductive structures 640S1 to 640S4 form relatively protruding points, which facilitates alignment.

Next, referring to FIG. 7, a support layer 770 is formed on the first surface 100T of the substrate 100. In some embodiments, the support layer 770 covers the seed layer 220 and the first conductive structures 640S1 to 640S4. In some embodiments, the support layer 770 is located at least in the display area AA. In this case, since the support layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110) located in the display area AA, they can To avoid damage to the elements and films located in the display area AA in the subsequent process. In some embodiments, the support layer 770 can be used as a protective film layer to facilitate the backside manufacturing process, such as copper plating. In some embodiments, the support layer 770 can increase the structural strength of the substrate 100, and improve the problem of insufficient stress or stiffness.

Next, referring to FIG. 8, a plurality of blind holes V1 and V2 are formed. A plurality of blind holes V1, V2 overlap the first conductive structure 640S1, 640S3. The blind holes V1 and V2 are drilled from the second surface 100B of the substrate 100 to the first surface 100T, that is, drilled along the direction Z. In some embodiments, the method for forming the blind holes V1 and V2 may include laser or etching (such as dry etching). The support layer 770 and the first conductive structure 640S1 to 640S4 can improve the structural strength and hardness of the substrate 100, and facilitate the drilling process of the blind holes V1 and V2. Therefore, the support layer 770 and the first conductive structure 640S1 to 640S4 are in the blind hole. The holes V1 and V2 are formed before the drilling process. Moreover, after the blind holes V1 and V2 are drilled, there are still other elements or films above the blind holes V1 and V2, that is, the blind holes V1 and V2 do not completely penetrate the first surface 100T of the substrate 100. All components or films, and furthermore, there will be components or films on the surface of the blind holes V1 and V2, which are different from the through holes. In this way, it not only helps to improve the resolution, but also avoids the problem of metal reflection. The blind holes V1 and V2 are respectively connected to the openings PG1 and PG2, that is, the blind holes V1 and V2 overlap the openings PG1 and PG2 in the direction Z. In this case, the positions of the blind holes V1 and V2 are related to the positions of the openings PG1 and PG2. Therefore, when the first conductive structures 640S1 and 640S3 are formed, the positions of the blind holes V1 and V2 have been determined. In other words, the positions of the blind holes V1 and V2 are determined when the copper is plated on the front side. In some embodiments, the first conductive structures 640S1 to 640S4, the blind holes V1, V2, and the openings PG1, PG2 are located in the display area AA (ie, the image display area), and the surrounding non-display area NAA does not need to be wired (such as connecting metal Line), but not limited to this. In some embodiments, the blind holes V1 and V2 penetrate through the substrate 100 and the film layer 111 to expose the seed layer 220 located above the first surface 100T of the substrate 100. In some embodiments, the laser stops at the seed layer 220. The top surfaces of the blind holes V1 and V2 are the bottom surfaces of the seed layer 220. Therefore, the top surfaces of the blind holes V1 and V2 are not coplanar with the first surface 100T of the substrate 100, but are higher than the first surface 100T of the substrate 100. That is, the distance in the direction Z between the top surface of the blind hole V1 (or blind hole V2) and the first surface 100T of the substrate 100 is smaller than that between the top surface of the blind hole V1 (or blind hole V2) and the first surface 100T of the substrate 100. The distance between the two surfaces 100B along the direction Z; in some embodiments, by appropriately designing the blind holes V1 and V2, the subsequent formed back electrode will extend beyond the substrate 100. In some embodiments, the sidewalls of the blind holes V1, V2 are inclined surfaces, that is, the cross-sectional areas of the blind holes V1, V2 in the parallel XY plane can be changed; in some embodiments, the blind holes V1, V2 are from (adjacent to the first part of the substrate 100). The bottom end of the two surfaces 100B (adjacent to the first conductive structure 640S1, 640S3) is gradually tapered, meaning that it tapers toward the direction (ie direction Z) close to the first conductive structure 640S1, 640S3 or away from the first conductive structure The structures 640S1 and 640S3 fan out in the direction; in some embodiments, the blind holes V1 and V2 are tapered or horn holes or large and small holes. In this way, the apertures (for example, diameters) of the top ends of the blind holes V1, V2 (adjacent to the first conductive structures 640S1, 640S3) can be ensured to be small, which helps to improve the resolution. In addition, in some embodiments, the size DD1 (eg, cross-sectional area width) of the first conductive structure 640S1 is approximately between 100 μm and 120 μm. Therefore, the first conductive structure 640S1 can completely shield the blind hole V1; in some implementations In an example, the size DD1 of the first conductive structure 640S1 is less than 200 microns.

Next, referring to FIG. 9, a surface treatment film 920 is formed. The surface treatment film 920 is located on the second surface 100B side of the substrate 100 and completely covers the substrate 100. For example, the surface treatment film 920 covers the second surface 100B and the blind holes V1 and V2 of the substrate 100. In some embodiments, the surface treatment film 920 may be a conductive material layer. In some embodiments, a surface metallization process may be used to form the surface treatment film 920; in some embodiments, the entire substrate 100 is electrically conductive. In some embodiments, the surface of the substrate 100 can be ring-opened by plasma treatment or chemical strong alkali treatment, that is, open the heterocyclic ring of the substrate 100 or open the weaker bond, and then, the substrate 100 The surface of the substrate is subjected to metal ion exchange, and then the metal is reduced to the surface of the substrate 100 to form a surface treatment coating 920. In some embodiments, the substrate 100 (and the film layer thereon) is immersed in a chemical solution, so the surface treatment film 920 completely covers the substrate 100. In some embodiments, the surface treatment coating 920 can be used as a seed layer, which is beneficial to the subsequent electroplating process and can avoid the phenomenon of film peeling. Since the support layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110) located in the display area AA on the first surface 100T of the substrate 100, damage to the surface treatment film 920 during the process of forming the surface treatment film 920 can be avoided. Display area AA elements and film layers. In other words, the substrate 100 and the support layer 770 cover the entire display area AA on both sides, so subsequent processes will not cause process damage to the display area AA. For example, the strong alkali used to make the substrate 100 conductive will not damage the front surface. In contrast, if the double-sided copper electroplating process is performed at one time, the front display area AA may be damaged.

Next, referring to FIG. 10, a second photoresist material pattern 1030 is formed on the surface treatment film 920. In other words, the second photoresist material pattern 1030 is located on the second surface 100B side of the substrate 100. The material of the second photoresist pattern 1030 may be the same as or different from the first photoresist pattern 330. The second photoresist material pattern 1030 partially overlaps the surface treatment film 920 in the direction Z and partially exposes the surface treatment film 920. In some embodiments, the second photoresist pattern 1030 does not overlap the blind holes V1, V2 in the direction Z; in some embodiments, the second photoresist pattern 1030 has a plurality of second trenches BR1~BR3, The second trenches BR1 and BR3 respectively expose the blind holes V1 and V2 and are connected to the blind holes V1 and V2 respectively; in some embodiments, the second trenches BR1 and BR3 overlap the blind holes V1 and V2 in the direction Z respectively. . The second photoresist material pattern 1030 may include a plurality of columnar bodies, for example, a second columnar body 1030P. In some embodiments, the sidewalls of the second columnar body 1030P can be inclined surfaces, and the cross-sectional area of the second columnar body 1030P in the parallel XY plane can be changed; in some embodiments, the second columnar body 1030P is self-propelled from (adjacent to the substrate). The bottom end of the second surface 100B of the second surface 100B of the substrate 100 is gradually tapered to the top end (away from the second surface 100B of the substrate 100), which means that it is tapered toward the direction away from the substrate 100 or toward the direction closer to the substrate 100 (ie direction Z) The upper fan out; in some embodiments, the second columnar body 1030P is tapered. In some embodiments, the second columnar body 1030P of the second photoresist material pattern 1030 can be formed by patterning, wherein the manufacturing precision of the first columnar body 330P of the first photoresist material pattern 330 is higher than that of the second photoresist material pattern 330. The manufacturing precision of the second columnar body 1030P of the photoresist material pattern 1030.

Next, referring to FIG. 11, a plurality of second conductive structures 1140S1 to 1140S3 are formed on the surface treatment film 920. In other words, the second conductive structures 1140S1 to 1140S3 are located on the second surface 100B side of the substrate 100. The second conductive structures 1140S1 to 1140S3 contact the seed layer 220 through the blind holes V1 and V2. In some embodiments, the bottom surface of the second conductive structure 1140S1 (or the second conductive structure 1140S3) is not coplanar with the first surface 100T of the substrate 100, but is higher than the first surface 100T of the substrate 100; in some embodiments The bottom surface of the second conductive structure 1140S1 (or the second conductive structure 1140S3) is located above the first surface 100T of the substrate 100. The material of the second conductive structures 1140S1 to 1140S3 may be the same as or different from that of the first conductive structures 640S1 to 640S4. In some embodiments, the method for forming the second conductive structure 1140S1 to 1140S3 may include a thick film formation technique such as electroplating; in some embodiments, the method for forming the second conductive structure 1140S1 to 1140S3 may include a physical vapor deposition method or Chemical vapor deposition method. In some embodiments, the surface treatment film 920 facilitates the formation of the second conductive structures 1140S1~1140S3, or can improve the uniformity of the formation of the second conductive structures 1140S1~1140S3, or can strengthen the second conductive structures 1140S1~1140S3 and the substrate 100 In some embodiments, the seed layer 220 or the first conductive structure 640S1~640S4 and the adjacent but not in direct contact between the surface treatment film 920 can be formed by skip plating to form the second conductive structure 1140S1 ~1140S3. The second conductive structure 1140S1~1140S3 covers part of the surface treatment film 920, and the second trench BR1~BR3 and the blind holes V1, V2 of the second photoresist material pattern 1030 are filled with the material forming the second conductive structure 1140S1~1140S3 To make the second conductive structure 1140S1~1140S3. Wherein, the surface treatment film 920 and the second conductive structures 1140S1 to 1140S3 are filled in the blind holes V1 and V2, and the second conductive structures 1140S1 to 1140S3 are filled in the blind holes V1 and V2. In addition, the second conductive structure 1140S1~1140S3 fills the second trenches BR1~BR3 of the second photoresist material pattern 1030 and engages the second trenches BR1~BR3, that is, the second photoresist material pattern 1030 can be The surface treatment coating film 920 is blocked from contacting the electroplating solution, so that the second conductive structures 1140S1 to 1140S3 have a patterned structure. In some embodiments, since the sidewalls of the second columnar body 1030P and the blind holes V1 and V2 of the second photoresist material pattern 1030 are inclined surfaces, the sidewalls of the second conductive structures 1140S1 to 1140S3 are also inclined surfaces, that is, the second conductive structure The cross-sectional area of 1140S1~1140S3 in the parallel XY plane can be changed; in some embodiments, the second conductive structure 1140S1~1140S3 gradually thickens from the bottom end (bottom surface 1140B) to the top end (top surface 1140T), which means moving away from the substrate The second surface 100B of the 100 fan out or tapers toward the second surface 100B of the substrate 100 (ie, the direction Z); in some embodiments, the second conductive structures 1140S1 to 1140S3 are tapered. In this way, the second conductive structures 1140S1 to 1140S3 can ensure the yield and manufacturing efficiency of the subsequent bonding process. In some embodiments, the aperture d2 of the second conductive structure 1140S1 (that is, the aperture near the bottom end of the first conductive structure 640S1, 640S3) is approximately between 1 micrometer (μm) and 20 micrometers; in some embodiments The aperture d2 of the second conductive structure 1140S1 is approximately between 10 and 20 microns; in some embodiments, the aperture d2 of the second conductive structure 1140S1 is different from the aperture d1 of the first conductive structure 640S1; in some embodiments The aperture d2 of the second conductive structure 1140S1 is smaller than the aperture d1 of the first conductive structure 640S1. In some embodiments, the thickness TH2 of the second conductive structure 1140S1~1140S3 is greater than 20 microns; in some embodiments, the thickness TH2 of the second conductive structure 1140S1~1140S3 is much greater than the thickness of the surface treatment film 920; In an embodiment, the thickness TH1 of the first conductive structure 640S1~640S4 is different from the thickness TH2 of the second conductive structure 1140S1~1140S3; in some embodiments, the thickness of the front and back copper is different; in some embodiments, the first conductive structure The thickness TH1 of the 640S1 to 640S4 is smaller than the thickness TH2 of the second conductive structure 1140S1 to 1140S3; in some embodiments, the thickness TH1 of the first conductive structure 640S1 to 640S4 is the same as the thickness TH2 of the second conductive structure 1140S1 to 1140S3. The thicker thickness TH2 of the second conductive structure 1140S1~1140S3 can reduce the resistance value of the traces on the second surface 100B of the substrate 100, and can carry a large current, thereby achieving high current density driving to ensure external quantum efficiency (EQE, External Quantum Efficiency) and the chromaticity of the light-emitting unit.

Next, referring to FIG. 12, the support layer 770 is removed. Next, referring to FIG. 13, a first conductive layer 1301 is formed on the first conductive structures 640S1 to 640S4, and a second conductive layer 1302 is formed on the second conductive structures 1140S1 to 1140S3. In other words, the first conductive layer 1301 is located The first surface 100T side of the substrate 100, and the second conductive layer 1302 is located on the second surface 100B side of the substrate 100. In some embodiments, the first conductive layer 1301 and the second conductive layer 1302 are formed together in the same process. Furthermore, the front and back sides are a one-time process, that is, double-sided tin is completed at one time; in some In an embodiment, the first conductive layer 1301 and the second conductive layer 1302 are formed in different processes. In some embodiments, based on the consideration of conductivity, the materials of the first conductive layer 1301 and the second conductive layer 1302 are generally metallic materials or alloys, nitrides of metallic materials, oxides of metallic materials, and oxynitrides of metallic materials. In some embodiments, the material of the first conductor layer 1301 and the second conductor layer 1302 is tin. Therefore, the first conductor layer 1301 and the second conductor layer 1302 are formed by a tin process, In this way, surface oxidation can be prevented; in some embodiments, the material of the first conductive layer 1301 and the second conductive layer 1302 is gold. In some embodiments, the thickness of the first conductor layer 1301 or the second conductor layer 1302 is approximately between 3 and 4 microns; in some embodiments, the thickness of the first conductor layer 1301 or the second conductor layer 1302 is approximately Between 1 and 2 microns.

Next, referring to FIG. 14, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed. In some embodiments, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed together in the same process. Furthermore, the front and back sides are a one-time process, that is, the double-sided photoresist is removed. The agent is a one-time process; in some embodiments, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed in different procedures. Wherein, in the present invention, after the first conductive layer 1301 and the second conductive layer 1302 are formed, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed. In this way, the first conductive layer 1301 and the second conductive layer 1302 are removed. The second conductive layer 1302 is formed at the position where the first photoresist material pattern 330 and the second photoresist material pattern 1030 are located, so that the sides of the first conductive structures 640S1 to 640S4 or the second conductive structures 1140S1 to 1140S3 are also covered with tin, thereby Affect process accuracy.

Next, referring to FIG. 15, a patterning step is performed to pattern the seed layer 220 and the surface treatment coating 920 to form a seed pattern layer 220N and a pattern coating 920N. In some embodiments, the seed layer 220 and the surface treatment film 920 are patterned together in the same process, that is, a one-time patterning process; in some embodiments, the seed layer 220 and the surface treatment film 920 It is patterned in different procedures. Among them, the patterning step involves an exposure process, a development process, or an etching process. The projections of the seed pattern layer 220N and the pattern coating 920N on the substrate 100 in the direction Z are substantially overlapped with the projections of the first conductive structures 640S1 to 640S4 and the second conductive structures 1140S1 to 1140S3 on the substrate 100 in the direction Z. In some embodiments, based on the height H1 of the first conductive structure 640S2 (or the first conductive structure 640S3) greater than 20 microns, the aperture a1 is approximately between 4 microns and 6 microns, and the ratio between the height and the aperture is greater than 3; In some embodiments, based on the aspect ratio of the first conductive structure 640S2, 640S3, the first conductive structure 640S2, 640S3 can be defined as a columnar body or a copper column; in some embodiments, the copper column is connected by the first conductive structure. The structures 640S1~640S4 and the seed pattern layer 220N are formed, but there is an interface between the first conductive structure 640S1~640S4 and the seed pattern layer 220N, or the copper pillar is formed by the second conductive structure 1140S1~1140S3 and the pattern coating 920N However, there is an interface between the second conductive structure 1140S1~1140S3 and the pattern coating 920N; in some embodiments, the first conductive structure 640S1~640S4 is compared with the composition of the seed pattern layer 220N (or the seed layer 220) The composition is different, or the degree of impurity doping or the film quality is different, so there is an interface between the first conductive structure 640S1~640S4 and the seed pattern layer 220N. Similarly, the second conductive structure 1140S1~1140S3 is compared with the pattern coating 920N ( Or the composition of the surface treatment film 920) is different, or the degree of impurity inclusion or film quality is different.

Next, referring to FIG. 16, a first shielding layer 1601 is formed on the first conductive layer 1301, and a second shielding layer 1602 is formed on the second conductive layer 1302. In other words, the first shielding layer 1601 is located on the first side of the substrate 100. One surface 100T side, and the second shielding layer 1602 is located on the second surface 100B side of the substrate 100. The first shielding layer 1601 partially overlaps the first conductive layer 1301 in the direction Z, and partially exposes the first conductive layer 1301 and the first conductive structures 640S2, 640S3 underneath, as bonding regions. The second shielding layer 1602 partially overlaps the second conductive layer 1302 in the direction Z, and partially exposes the second conductive layer 1302 and the second conductive structure 1140S3 thereunder as a bonding area. In some embodiments, the first conductive structure 640S2, 640S3 and the first conductive layer 1301 thereon can be used as contact pads or soldering pads; similarly, the second conductive structure 1140S3 and the second conductive layer 1302 thereon can be used as contact pads. Pad or solder pad. In some embodiments, the material of the first shielding layer 1601 or the second shielding layer 1602 includes black ink; in some embodiments, the first shielding layer 1601 or the second shielding layer 1602 can be used as an anti-reflection layer or Solder Mask layer; in some embodiments, only the area for bonding the light-emitting unit LN1 is exposed on the front side, and only the area for bonding the integrated circuit is exposed on the back side. Therefore, the first shielding layer 1601 and the second shielding layer 1601 The shielding layer 1602 can be used to shield light, or avoid the problem of metal reflection to achieve seamless splicing.

Next, referring to FIG. 17, the light-emitting unit LN1 is disposed on the first conductor layer 1301. In other words, the light-emitting unit LN1 is located on the first surface 100T side of the substrate 100. In some embodiments, the light-emitting unit LN1 may be a light-emitting diode (LED) or a micro LED (micro LED), but the invention is not limited thereto. In some embodiments, the light-emitting unit LN1 is formed on a growth substrate first, and then transferred to another light-emitting unit substrate using a mass transfer technology. In some embodiments, the light-emitting unit LN1 is bonded to the first conductive layer 1301 by, for example, an adhesive layer or solder, and is further coupled to the first conductive structure 640S2, 640S3; in some embodiments, a miniature light-emitting diode It is bonded on the copper pillar by a micro bonding process. In some embodiments, the first conductive structure 640S2 may be coupled to one end of the light-emitting unit LN1, for example, to the cathode or anode of the light-emitting unit LN1; in some embodiments, the first conductive structure 640S3 Can be coupled to system low voltage (VSS).

On the other hand, as shown in FIG. 17, the substrate 1700 is disposed on the second conductor layer 1302, in other words, the substrate 1700 is located on the second surface 100B side of the substrate 100. The substrate 1700 is used to provide a driving circuit, which can be used to provide driving signals to active elements (not shown in the figure) of the pixel unit, and the driving circuit can be coupled to the second conductive structure 1140S3 through the second conductor layer 1302. At this point, the manufacture of the display panel 10 can be completed. In some embodiments, an encapsulant or a cover glass or a black matrix may be further provided to complete the manufacture of the display panel 10.

It can be seen from the above that the components on the first surface 100T of the substrate 100 can be coupled to the first conductive structure (for example, the first conductive structure 640S1, 640S3), and the first conductive structure can be coupled to the first conductive structure through the blind holes V1, V2. The second conduction structure, the second conduction structure (second conduction structure 1140S1, 1140S3) can be coupled to the element located on the second surface 100B of the substrate 100. That is to say, the device located on the second surface 100B of the substrate 100 can be coupled to the device located on the first surface 100T of the substrate 100 through the first conductive structure and the second conductive structure. The blind holes V1 and V2 are connected up and down. In this way, the space of the first surface 100T and the second surface 100B of the substrate 100 can be fully utilized for wiring, and the size of the display panel 10 can be reduced, thereby achieving miniaturization of the size. In addition, arranging a part of the circuit on the second surface 100B of the substrate 100 can reduce the area of the wiring area (that is, the non-light emitting area) on the first surface 100T of the substrate 100. In this case, the display panel 10 can implement a narrow frame design or a seamless splicing design.

In addition, the first conductive structures 640S1 to 640S4 are formed before the blind holes V1 and V2. Therefore, the first conductive structures 640S1 to 640S4 can increase the structural strength of the substrate 100 and facilitate the drilling of the blind holes V1 and V2. In addition, the blind holes V1 and V2 extend to the first conductive structures 640S1 to 640S4, but do not penetrate the first conductive structures 640S1 to 640S4. After that, the second conductive structures 1140S1 to 1140S3 are filled into the blind holes V1 and V2, and the electrical Connected to the first conductive structure 640S1~640S4. In other words, copper plating can be divided into two front and back sides. In this way, the panel manufacturing process with higher precision requirements (such as the manufacturing steps in Figure 1A to Figure 4) and the wiring process with higher precision requirements (as shown in Figure 4) can be combined. The manufacturing steps from 6 to 17) are carried out separately, which is different from the process technology of one-time copper plating on the front and back. In addition, when copper plating on the front side, the substrate does not have blind holes, and when drilling by the back laser, there is front hardness support, and the drilling stops on the copper layer on the front side. In this case, the blind hole structure helps to improve the resolution. . Moreover, since the support layer 770 and the substrate 100 cover the elements and film layers (such as the pixel array structure layer 110) located in the display area AA on the first surface 100T of the substrate 100, subsequent manufacturing processes (such as the open loop in FIG. 9) can be avoided. Procedure) Damage the components and film layer located in the display area AA. Since the first conductive layer 1301 and the second conductive layer 1302 are formed in the same process, the first photoresist pattern 330 and the second photoresist pattern 1030 are removed in the same process, and the seed crystal The layer 220 and the surface treatment film 920 are patterned together in the same process, so the process can be simplified and the process time can be shortened.

The depth of blind holes V1 and V2 can be adjusted according to different design considerations. For example, please refer to FIG. 18, which is a schematic cross-sectional view of a partial area of a display panel 10' according to another embodiment of the present invention. As shown in FIG. 18, the difference between the display panel 10' and the display panel 10 is that the blind holes V1' and V2' of the display panel 10' penetrate through the substrate 100, the film layer 111 and the seed layer 220, and expose the The first conductive structures 640S1, 640S3 above the first surface 100T of 100, that is, the drilling process of the blind holes V1', V2' ends at the first conductive structures 640S1, 640S3. In some embodiments, the laser stops at the first conductive structure 640S1, 640S3 (or thick copper layer). The top surfaces of the blind holes V1', V2' are the bottom surfaces of the first conductive structures 640S1, 640S3. Therefore, the top surfaces of the blind holes V1', V2' are not coplanar with the first surface 100T of the substrate 100, but are higher than the substrate. 100的第一surface 100T. The second conductive structures 1140S1 and 1140S3 contact the first conductive structures 640S1 and 640S3 through the blind holes V1' and V2', so that the first conductive structures 640S1 and 640S3 serve as termination layers of the second conductive structures 1140S1 and 1140S3. In some embodiments, the front copper layer is a termination layer of the back copper layer.

In summary, the display panel of the present invention has a blind hole penetrating the substrate. The first conductive structure can be coupled to the second conductive structure through the blind hole. Therefore, the element located on the upper surface of the substrate can be coupled to the element located on the substrate. In this way, the components on the lower surface can be miniaturized in size. The first conductive structure and the support layer of the display panel are formed before the blind hole. Therefore, the first conductive structure and the support layer can improve the structural strength of the substrate, which is beneficial to the drilling of the blind hole and can improve the yield. In addition, since the support layer and the substrate cover the elements and film layers located in the display area on the first surface of the substrate, the subsequent process can prevent the elements and film layers located in the display area from being damaged, and the yield can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 10’: display panel 100, 1700: substrate 100B: second surface 100S: Carrier substrate 100T: first surface 110: Pixel array structure layer 111~115: Membrane 116: connecting conductor layer 220: seed layer 220N: Seed pattern layer 330: The first photoresist material pattern 330P: The first columnar body 410: counterpoint mark 640S1~640S4: the first conduction structure 770: support layer 920: Surface treatment film 920N: Pattern coating 1030: Second photoresist material pattern 1030P: second columnar body 1140S1~1140S3: second conduction structure 1140T: Top surface 1140B: bottom surface 1301: first conductor layer 1302: second conductor layer 1601: first shielding layer 1602: second shielding layer AA: Display area BR1~BR3: second groove CP1: Conductor pattern d1, d2, a1: aperture D1: Drain pattern DD1: size G1: Gate pattern HL1~HL3: contact hole LN1: Light-emitting unit NAA: Non-display area PG1, PG2: opening S1: Source pattern SE1: Semiconductor layer T1: Active component TH1, TH1’, TH2: thickness TR1~TR4: the first groove V1, V2, V1’, V2’: blind holes X, Y, Z: direction

1A to FIG. 17 are schematic diagrams of a manufacturing process of a partial area of a display panel according to an embodiment of the present invention. FIG. 18 is a schematic cross-sectional view of a partial area of a display panel according to another embodiment of the present invention.

10: Display panel

100, 1700: substrate

111~115: Membrane

220: seed layer

640S1~640S4: the first conduction structure

1140S1~1140S3: second conduction structure

1301: first conductor layer

1302: second conductor layer

1601: first shielding layer

1602: second shielding layer

CP1: Conductor pattern

D1: Drain pattern

G1: Gate pattern

LN1: Light-emitting unit

S1: Source pattern

SE1: Semiconductor layer

X, Y, Z: direction

Claims (15)

A display panel including: A substrate having a first surface and a second surface; A film layer disposed above the first surface of the substrate, the film layer having a plurality of openings, and a plurality of blind holes penetrating the substrate are respectively connected to the openings; A seed pattern layer is disposed above the film layer, and the seed pattern layer fills the openings; A first conductive structure disposed above the seed pattern layer, the first conductive structure fills the openings, and the blind holes overlap the first conductive structure; A pattern covering film overlapping the second surface of the substrate and the blind holes; and A second conductive structure is disposed above the patterned film, and the second conductive structure is filled in the blind holes to be electrically connected to the first conductive structure. In the display panel described in claim 1, wherein a bottom surface of one of the second conductive structures is located above the first surface of the substrate. In the display panel described in claim 1, wherein the ratio between the thickness of one of the first conductive structures and the aperture is greater than 3. In the display panel described in claim 1, wherein the thickness of one of the first conductive structures is smaller than the thickness of one of the second conductive structures. In the display panel described in claim 1, wherein one of the blind holes is tapered toward the first conductive structure, and one of the openings is tapered toward the substrate. In the display panel described in claim 1, wherein the hole diameter of the bottom surface of one of the first conductive structures is different from the hole diameter of the bottom surface of one of the second conductive structures. According to the display panel described in item 1 of the scope of patent application, there is an interface between the second conductive structure and the first conductive structure. A method for manufacturing a display panel includes: Forming a film layer on a first surface of a substrate, the film layer having a plurality of openings; Forming a seed layer above the film layer, the seed layer filling the openings; Forming a first conductive structure above the seed layer, the first conductive structure filling the openings; Forming a plurality of blind holes, the blind holes penetrating the substrate and communicating with the openings, the blind holes overlapping the first conductive structure; Forming a surface treatment film covering a second surface of the substrate and the blind holes; Forming a second conductive structure above the surface treatment film, the second conductive structure is filled in the blind holes to be electrically connected to the first conductive structure; and The seed layer and the surface treatment coating are patterned to form a seed pattern layer and a pattern coating. The manufacturing method of the display panel as described in claim 8 further includes forming a first photoresist material pattern on the seed layer before forming the first conductive structure, the first photoresist material pattern having multiple A first trench, the first conductive structure is filled in the first trenches, and a part of the first trenches are respectively connected to the openings. As described in item 8 of the scope of patent application, the method for manufacturing a display panel further includes forming a plurality of alignment marks, and the alignment marks are located in a non-display area of the substrate and penetrate the substrate. The manufacturing method of the display panel as described in claim 8 further includes forming a support layer above the first conductive structure and the first photoresist material pattern before forming the blind holes. The manufacturing method of the display panel as described in claim 8 further includes forming a second photoresist material pattern on the surface treatment film before forming the second conductive structure, the second photoresist material pattern having A plurality of second trenches, the second conductive structure is filled in the second trenches, and a part of the second trenches are respectively connected to the blind holes. The manufacturing method of the display panel as described in claim 8 further includes forming a first conductive layer above the first conductive structure and a second conductive layer above the second conductive structure at the same time. The manufacturing method of the display panel as described in claim 8 further includes removing a first photoresist material pattern and a second photoresist material before patterning the seed layer and the surface treatment film pattern. The manufacturing method of the display panel as described in item 8 of the scope of patent application also includes: Forming a first shielding layer above the first conductive layer and a second shielding layer above the second conductive layer, the first shielding layer exposing part of the first conductive layer as a first bonding area; and A light-emitting unit is bonded to the first conductor layer located in the first bonding area.

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