TW202101221A - Data storage device and non-volatile memory control method - Google Patents

Abstract

Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. According to an uncorrectable flag assertion command (i.e. WriteUNC of NVMe) issued by a host, the controller operates the CRC engine to encode a data pattern with an shifted seed to generate shifted CRC code. The controller programs the shifted CRC code to the non-volatile memory along with the data pattern. The data pattern, therefore, will not pass CRC. The uncorrectable flag assertion command works successfully.

Description

Data storage device and non-volatile memory control method

The present invention relates to the control of non-volatile memory.

Non-volatile memory has many forms-for example, flash memory (flash memory), magnetoresistive RAM (Magnetoresistive RAM), ferroelectric random access memory (Ferroelectric RAM), resistive random access Memory (Resistive RAM), Spin Transfer Torque-RAM (STT-RAM)... etc. are used for long-term data storage and can be used as storage media to realize a data storage device.

With the advancement of technology, the storage capacity of data storage devices has become stronger. The technical field needs mapping information management technology that can cope with large-scale storage.

The mapping information format used in this case does not require special planning and cannot correct the UNC bit. The mapping information format therefore has sufficient bits for physical address marking.

A data storage device implemented according to an embodiment of this case includes a non-volatile memory and a controller. The controller controls the non-volatile memory and includes a cyclic redundancy check (CRC) engine. According to an uncorrectable marking command issued by a host (such as NVMe's WriteUNC command), the controller operates the cyclic redundancy check engine to encode a data template with an offset coding seed to generate an offset cyclic redundancy check code. The controller programs the offset cyclic redundancy check code along with the data template into the non-volatile memory. The data template must not pass the cyclic redundancy check. The uncorrectable indication command has successfully operated.

In one embodiment, the uncorrectable flag command indicates a logical address. The controller offsets the logical address to generate an offset logical address. The controller operates the cyclic redundancy check engine to use the offset logical address as the offset encoding seed. The data template can be zero.

In one embodiment, according to a read command issued by the host to the logical address, the controller obtains the data template and the offset cyclic redundancy check code from the non-volatile memory. The controller operates the cyclic redundancy check engine to use the logical address as an encoding seed. The controller operates the cyclic redundancy check engine to generate a cyclic redundancy check code for the data template using the coding seed. The controller operates the cyclic redundancy check engine to compare and find that the cyclic redundancy check code is different from the offset cyclic redundancy check code, and does not respond to the host with the data template.

In one embodiment, the controller obtains the data template and the offset cyclic redundancy check code from the non-volatile memory according to a mapping information of the logical address. A mapping information format adopted by the mapping information does not include any uncorrectable flag bits. In one embodiment, the marking unit of the uncorrectable marking command is smaller than the data unit managed by the mapping information format.

In one embodiment, regarding an error data obtained from a first area of the non-volatile memory according to a logical address and error checking and correction failed, the controller sends the error data and a cyclic redundancy check code It is programmed to a second area of the non-volatile memory. The cyclic redundancy check code is read by the controller from the first area of the non-volatile memory along with the error data. In one embodiment, according to a read command requested by the host for the logical address, the controller obtains the error data and the cyclic redundancy check code from the second area of the non-volatile memory. The controller operates the cyclic redundancy check engine to use the logical address as an encoding seed. The controller operates the cyclic redundancy check engine to generate an error cyclic redundancy check code for the error data with the encoding seed. The controller operates the cyclic redundancy check engine to compare and find that the error cyclic redundancy check code is different from the cyclic redundancy check code, and does not respond to the host with the error data.

In one embodiment, the above-mentioned error checking and correction originate from a read command from the host to the non-volatile memory.

In one embodiment, the above-mentioned error checking and correction result from a garbage collection performed by the controller on the non-volatile memory.

The operation of the above memory controller on the non-volatile memory can also be implemented by other structures. In this case, the aforementioned concept can be used to implement a non-volatile memory control method, including the following steps: providing a cyclic redundancy check engine; operating the cyclic redundancy check engine according to an uncorrectable indication command issued by a host The shift encoding seed encodes a data template to generate an offset cyclic redundancy check code; and the offset cyclic redundancy check code is programmed into a non-volatile memory along with the data template.

Hereinafter, specific embodiments are given in conjunction with accompanying drawings to illustrate the content of the present invention in detail.

The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention, and is not intended to limit the content of the present invention. The actual scope of invention shall be defined in accordance with the scope of patent application.

Non-volatile memory can be flash memory (Flash Memory), magnetoresistive RAM (Magnetoresistive RAM), ferroelectric random access memory (Ferroelectric RAM), resistive RAM (RRAM) ), Spin Transfer Torque-RAM (STT-RAM), etc., provide storage media for long-term data storage. The following discussion takes the flash memory as an example.

Nowadays, data storage devices often use flash memory as storage media to realize products such as Memory Card, Universal Serial Bus Flash Device (USB Flash Device), Solid State Drive (SSD)...etc. One application is to use multi-chip packaging to package flash memory and its controller together-called embedded flash memory modules (such as eMMC).

The data storage device using flash memory as the storage medium can be applied to a variety of electronic devices. The electronic devices include smart phones, wearable devices, tablet computers, virtual reality equipment, etc. The computing module of the electronic device can be regarded as a host, which operates the data storage device used to access the flash memory therein.

Data storage devices using flash memory as storage media can also be used to construct data centers. For example, the server can operate a solid state drive (SSD) array to form a data center. The server can be regarded as the host, operating the connected solid-state drive to access the flash memory.

Flash memory has its special storage characteristics, which are described below.

The host (Host) uses logical addresses (for example, logical block address LBA or global host page number GHP... etc.) to distinguish data. As for where the data is actually stored in flash memory, it is managed by mapping information.

The physical space of the flash memory is divided into a plurality of blocks (Blocks) for allocation. Figure 1 illustrates the structure of a block Blk of the flash memory. The block Blk includes a plurality of pages (Pages), for example, page 0...page 255. One implementation method is to sequentially use a block of storage space according to the page number—from low to high. Each page includes a plurality of sectors (Sectors), such as 32 sectors, each sector can store 512B length of user data. One write may involve multiple sectors. For example, in the 4KB data management mode, 8 sections can be regarded as a data unit (Unit) for management. One write may cover 8 sectors (4KB) in length. A 16KB page can be composed of four data units (32 sections); the logical relationship of the four data units may not be continuous.

In particular, the data update of the same logical address is not overwritten to the storage space of the old data, and the data of the new version must be written into a blank section. The content of the old space is invalid. A block may only retain valid data sporadically. Since the storage space of the flash memory needs to be erased before it can be used again, the spare blocks are gradually consumed. When the number of spare blocks is insufficient (for example, below the threshold), a garbage collection (Garbage Collection) demand is generated. The scattered valid data stored in one block is collected in other spaces through garbage collection. Blocks with invalid data are erased and released, increasing the number of spare blocks to ensure the normal use of flash memory. Garbage collection may also make the logical relationship with the block content more fragmented.

It can be seen from the foregoing that the spatial configuration of the flash memory is quite complicated. One implementation is to create a logical-to-physical address mapping table (Logical-to-Physical Addresses Mapping Table, L2P mapping table) to record the mapping information between the logical address and the physical address, preferably using the logical address as an index. The physical address is content, where the physical address is, for example, a physical block address (Physical Block Address, PBA). One implementation is to indicate the physical location of block information Blk#, page information Page#, and data unit information Unit# (or offset). Alternatively, the multi-channel (multi-channel) technology further includes a physical space mark such as the channel number CH#.

FIG. 2A illustrates a mapping information format 200 used in the conventional technology, which includes 32 bits (four bytes) to record physical addresses. Your plan is as follows: l Bit [31]: Uncorrectable (UNC) flag bit, used to indicate that the content pointed to by the mapping information is unreliable, or technically speaking, UNC indicates that the data cannot be corrected through error checking and correction (ECC). To be corrected, when ECC fails, the UNC flag bit will switch from "0" to "1", for example. Possible reasons for ECC failure include physical errors caused by environmental factors or time factors, errors in the process of reading data, and errors in the process of data programming. l Bit [30:29]: The bit of the pattern mode (Pattern Mode). In one embodiment, the data that the host requests to write into the flash memory is first cached in a temporary memory. After a programmed condition is met (for example, the cache reaches a certain amount, or is sealed regularly), the data is moved from the temporary memory to the flash memory. Therefore, the logical address may also be mapped to the temporary memory. Pattern Mode displays whether the mapping information points to temporary memory or flash memory. 00/01 represents the subsequent bit [28:0] indicates the physical address of the flash memory, 10 represents the subsequent bit [28:0] indicates the physical address of the temporary memory, and 11 represents the subsequent bit [28: 0] is meaningless dummy data. l Bit [28:0]: The physical address of flash memory or temporary memory, or dummy data.

The mapping information format 200 is equipped with mapping information mode bits [30:29], and after deducting the UNC flag bit [31], only 29 bits can be used to indicate the physical address, which will limit the data storage device can provide Storage capacity.

In order to avoid the above problem, Figure 2B illustrates a mapping information format 210 used in an implementation of this case, which includes 32 bits (four bytes). The mapping information format 210 no longer includes UNC flag bits. In this way, the mapping The information format 210 has more bits that can be used to represent physical addresses, so that the storage capacity provided by the data storage device can be doubled compared to the previous storage capacity, achieving the purpose of the present invention. In addition, the mapping information format 210 no longer includes the mapping information mode bit. The following describes in detail how to achieve uncorrectable (UNC) without using UNC flag bits.

FIG. 3 is a block diagram illustrating a data storage device 300 according to an embodiment of the present invention, which includes a flash memory 302, a controller 304, and a temporary memory 306. The host 308 operates the flash memory 302 through the controller 304. The interior of the data storage device 300 can also be activated by the controller 304 to optimize the flash memory 302; for example, the space of the flash memory 302 can be arranged to maximize the storage performance. The controller 304 uses the temporary memory 306 to temporarily store data when performing operations. The temporary storage memory 306 can be a dynamic random access memory (DRAM) or SRAM.

The flash memory 302 includes a plurality of blocks. The block storing system information is called the system block pool 310. For example, the system block storing the mapping information is a non-volatile storage for the mapping information. The active block A0 from the spare block pool 312 is used to program the write data required by the host 308. After the active block A0 is programmed, it becomes a data block and is pushed into the data block pool 314. After running for a period of time, some data blocks may be updated frequently, leaving only scattered valid data. These data blocks will be released by garbage collection (Garbage Collection) and reclassified to the spare block pool 312. The target block A1 from the spare block pool 312 is used for effective data collection for garbage collection. After the target block A1 is filled with data, it is also pushed into the data block pool 314.

As shown in the figure, the controller 304 first caches data in the data cache space 316 of the temporary memory 306, and then programs the data cache space 316 to the active block A0. The controller 304 can use the space 318 of the temporary memory 306 to dynamically maintain the mapping information. The controller 304 includes a cyclic redundancy check (CRC) engine 320. The uncorrectable marking command (called UNC marking command, for example: Write UNC command) issued by the host 308 includes a target logical address LBA. When the controller 304 executes the UNC marking command issued by the host 308, it first generates the offset logical address LBA_UNC for the target logical address LBA, and then instructs the CRC engine 320 to use the offset logical address LBA_UNC as the encoding seed, and then The data template (Pattern) P is encoded, and finally the offset cyclic redundancy check code CRC_UNC is generated. Then, the controller 304 programs the data template P and the offset cyclic redundancy check code CRC_UNC to the idle data unit 330 of the active block A0, for example, fills the data template P into the data area 332 of the idle data unit 330 , The offset cyclic redundancy check code CRC_UNC is filled into the metadata area 334 of the idle data unit 330 to complete the UNC marking and the execution of the UNC marking command. After that, the mapping information of the target logical address LBA is updated. In one embodiment, the data pattern P is "0" or the original data stored in the physical address corresponding to the target logical address LBA.

Later, if the host 308 wants to read the data of the target logical address LBA, the CRC engine 320 uses the target logical address LBA as the encoding seed S, and uses the encoding seed S to calculate the data template P taken from the data area 332 CRC. At this time, the CRC is obviously different from the offset cyclic redundancy check code CRC_UNC stored in the metadata area 334. Therefore, the controller 304 responds to the host 308 with a preset message, for example, the target logical address LBA has not been recorded. Or the target logical address LBA has been cleared, etc. In this way, in the present invention, the UNC marking command is not only executed, but the result of execution conforms to the spirit of UNC, so that the data of the target logical address LBA is invalidated or not adopted.

In one embodiment, the host 308 requests to read the target logical address LBA with a read command. What the controller 304 obtains from the data unit 340 of the data block 338 is the error data D_ERR (data area 342) and the cyclic redundancy check code CRC (meta data area 344). The controller 304 performs ECC processing on the error data D_ERR, and the result is that the ECC fails. In response, the controller 304 reprograms the error data D_ERR and the cyclic redundancy check code CRC to the active block A0 (for example, the data area 332 and the metadata area 334 of the data unit 330) to complete the UNC marking. After that, when the host 308 wants to read the data of the target logical address LBA, the controller 304 operates the CRC engine 320 to calculate the error data D_ERR from the data area 332 according to the target logical address LBA and obtain the error cyclic redundancy check The code CRC_ERR is obviously different from the cyclic redundancy check code CRC stored in the metadata area 334, so the controller 304 responds with a preset message to the host 308. The UNC mark invalidates or is not adopted the data of the target logical address LBA, which conforms to the spirit of being marked as UNC.

ECC failure may also occur during the execution of garbage collection (Garbage Collection) programs. In one embodiment, the controller 304 uses the data block 338 as the source block (Source Block) of the garbage collection process, and obtains the error data D_ERR (data area 342) and the cyclic redundancy check code CRC (metadata) from the data unit 340 Area 344) to copy to the destination block A1. Before copying, the controller 304 performs ECC processing on the error data D_ERR, and the result is that the ECC fails. The controller 304 programs the error data D_ERR and the cyclic redundancy check code CRC on the target block A1 (for example, the data area 352 and the metadata area 354 of the data space 350) to complete the UNC marking. Later, when the host 308 wants to read the data of the target logical address LBA, the controller 304 operates the CRC engine 320 to calculate the error cyclic redundancy check code from the error data D_ERR from the data area 352 according to the target logical address LBA CRC_ERR, which is obviously different from the cyclic redundancy check code CRC stored in the metadata area 334, the controller 304 responds with a preset message to the host 308. The UNC mark invalidates or is not adopted the data of the target logical address LBA, which conforms to the spirit of being marked as UNC.

In one embodiment, the CRC engine 320 performs CRC encoding in units of section length (512B). Each section corresponds to a CRC value of 2B length. A data unit length (4KB) of data can generate 8 cyclic redundancy check codes CRC. Data of shorter length (less than 4KB) can also have a corresponding CRC value. For example, only 512B data can correspond to a cyclic redundancy check code CRC (2B). Therefore, the UNC labeling method using cyclic redundancy check code CRC or offset cyclic redundancy check code CRC_UNC can be applied to data of segment length (512B), data unit length (4KB) or other lengths. The technology of the present application makes the marking unit of the marking command unable to be calibrated smaller than the data unit managed by the mapping information format 210.

Figure 4 corresponds to the UNC marking command (Write UNC) to illustrate a data unit 400 of a page in the flash memory 302. The data unit 400 includes 8 areas of 4KB (8*512B), respectively corresponding to the logical address LBA#0 ~#7. The UNC marking command includes: the starting logical address LBA#4, the logical address length is equal to 4. Therefore, the controller 304 needs to perform the logical address LBA#4~#7 in the logical address LBA#0~#7 UNC mark. As shown in the figure, the controller 304 programs the data D of the target logical address LBA#0~#3 and the cyclic redundancy check code CRC to the first four sections of the data unit 400. As for the logical positions LBA#4~#7 to be marked with UNC, the controller 304 operates the CRC engine 320 to encode the data D of the logical positions LBA#4~#7 with the offset logical addresses LBA#5~#8 , Get the offset cyclic redundancy check code CRC_UNC#4~#7. The controller 304 programs the data D of the logical position LBA#4~#7 and the offset cyclic redundancy check code CRC_UNC#4~#7 into the last four sections of the data unit 400 to complete the execution of the UNC marking command .

Figure 5 is a flowchart illustrating the processing flow of the UNC marking command (Write UNC) according to an embodiment of this case.

In step S502, the controller 304 receives a UNC marking command (Write UNC) from the host 308, where the UNC marking command includes the target logical address.

In step S504, the controller 304 generates an offset logical address LBA_UNC, where the offset logical address LBA_UNC can be generated according to the target logical address or generated randomly.

In step S506, the controller 304 operates the CRC engine 320 to encode the data pattern P with the offset logic address LBA_UNC to obtain the offset cyclic redundancy check code CRC_UNC, where the data pattern P is "0" or the target logic The original data stored in the physical address corresponding to the address LBA.

In step S508, the controller 304 programs the data pattern P and the offset cyclic redundancy check code CRC_UNC to the idle data unit 330 of the active block A0.

Figure 6 is a flowchart illustrating how the controller 304 handles the reading request of the host 308 according to an embodiment of this case.

In step S602, the controller 304 receives a read instruction from the host 308, where the read instruction includes the target logical address LBA.

In step S604, the controller 304 obtains the physical address corresponding to the target logical address LBA according to the target logical address LBA and the L2P mapping table, where the physical address is PBA.

Step S606, the controller 304 obtains the data D_read and the cyclic redundancy check code CRC_read from the physical address.

In step S608, the controller 304 operates the CRC engine 320 to encode the data D_read with the cyclic redundancy check code CRC_read to obtain the cyclic redundancy check code CRC_ref.

In step S610, the controller 304 compares the cyclic redundancy check code CRC_read and the cyclic redundancy check code CRC_ref, and if the comparison result is not the same, step S612 is executed, and the controller 304 outputs a preset message to the host 308. In addition, the controller 304 does not return the data D_read to the host 308. If the comparison result is the same, step S614 is executed, and the controller 304 returns the data D_read to the host 308 to complete the execution of the read command.

The above operation design of the memory controller 304 on the flash memory 302 can also be implemented by other structures. Any technology that operates the flash memory based on the aforementioned concept and makes the mapping data omit the UNC-marked exclusive bit belongs to the scope of protection of this case. In this case, the aforementioned concept can be used to realize the control method of non-volatile memory.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone familiar with the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

200, 210: mapping information format 300: Data storage device 302: flash memory 304: Controller 306: Temporary memory 308: host 310: System block pool 312: Spare Block Pool 314: Data Block Pool 316: data cache space 318: Space, dynamic maintenance of mapping information 320: Cyclic Redundancy Check Engine 330, 332, 334: data unit and its data area and metadata area 338: Data Block 340, 342, 344: data unit and its data area and metadata area 350, 352, 354: data unit and its data area and metadata area 400: data unit A0: Active block A1: Destination block LBA: logical address S502...S508, S602...S614: steps

Figure 1 illustrates the structure of a block Blk of the flash memory; Figure 2A illustrates a mapping information format 200 used in conventional technology; Figure 2B illustrates a mapping information format 210 used in an implementation of this case; Figure 3 is a block diagram illustrating a data storage device 300 according to an embodiment of the present case; Figure 4 illustrates a data unit 400 on a block of the flash memory 302 corresponding to a UNC marking command (WriteUNC); Figure 5 is a flowchart illustrating the processing flow of the UNC marking command (WriteUNC) according to an embodiment of this case; and Figure 6 is a flowchart illustrating how the controller 304 handles the reading request of the host 308 according to an embodiment of this case.

300: Data storage device

302: flash memory

304: Controller

306: Temporary memory

308: host

310: System block pool

312: Spare Block Pool

314: Data Block Pool

316: data cache space

318: Space, dynamic maintenance of mapping information

320: Cyclic Redundancy Check Engine

330, 332, 334: data unit and its data area and metadata area

338: Data Block

340, 342, 344: data unit and its data area and metadata area

350, 352, 354: data unit and its data area and metadata area

A0: Active block

A1: Destination block

Claims (20)

A data storage device includes: A non-volatile memory; and A controller that controls the non-volatile memory and includes a cyclic redundancy check engine, among them: According to an uncorrectable indication instruction issued by a host, the controller operates the cyclic redundancy check engine to encode a data template with an offset encoding seed to generate an offset cyclic redundancy check code; and The controller programs the offset cyclic redundancy check code along with the data template into the non-volatile memory. The data storage device described in item 1 of the scope of patent application, in which: The uncorrectable flag command indicates a logical address; The controller offsets the logical address to generate an offset logical address; and The controller operates the cyclic redundancy check engine to use the offset logical address as the offset encoding seed. The data storage device described in item 2 of the scope of patent application, in which: The data template is zero. The data storage device described in item 2 of the scope of patent application, in which: According to a read command issued by the host to the logical address, the controller obtains the data template and the offset cyclic redundancy check code from the non-volatile memory; The controller operates the cyclic redundancy check engine to use the logical address as an encoding seed; The controller operates the cyclic redundancy check engine to generate a cyclic redundancy check code for the data template using the coding seed; and The controller operates the cyclic redundancy check engine to compare and find that the cyclic redundancy check code is different from the offset cyclic redundancy check code, and does not respond to the host with the data template. The data storage device described in item 4 of the scope of patent application, in which: The controller obtains the data template and the offset cyclic redundancy check code from the non-volatile memory according to a mapping information of the logical address; and A mapping information format adopted by the mapping information does not include any uncorrectable flag bits. The data storage device described in item 5 of the scope of patent application, in which: The label unit of the uncorrectable label command is smaller than the data unit managed by the mapping information format. The data storage device described in item 1 of the scope of patent application, in which: Regarding an error data obtained from a first area of the non-volatile memory according to a logical address and error checking and correction failed, the controller programs the error data and a cyclic redundancy check code to the non-volatile memory A second area of the integrated memory; and The cyclic redundancy check code is read by the controller from the first area of the non-volatile memory along with the error data. Such as the data storage device described in item 7 of the scope of patent application, in which: According to a read command requested by the host for the logical address, the controller obtains the error data and the cyclic redundancy check code from the second area of the non-volatile memory; The controller operates the cyclic redundancy check engine to use the logical address as an encoding seed; The controller operates the cyclic redundancy check engine to generate an error cyclic redundancy check code for the error data with the encoding seed; and The controller operates the cyclic redundancy check engine to compare and find that the error cyclic redundancy check code is different from the cyclic redundancy check code, and does not respond to the host with the error data. Such as the data storage device described in item 7 of the scope of patent application, in which: The above-mentioned error checking and correction are derived from a read command from the host to the non-volatile memory. Such as the data storage device described in item 7 of the scope of patent application, in which: The above-mentioned error checking and correction originate from a garbage collection performed by the controller on the non-volatile memory. A non-volatile memory control method, including: Provide a cyclic redundancy check engine; According to an uncorrectable marking instruction issued by a host, operating the cyclic redundancy check engine to encode a data template with an offset encoding seed to generate an offset cyclic redundancy check code; and The offset cyclic redundancy check code is programmed into a non-volatile memory along with the data template. The non-volatile memory control method described in item 11 of the scope of patent application further includes: Offset a logical address indicated by the uncorrectable marking command to generate an offset logical address; and Operate the cyclic redundancy check engine to use the offset logical address as the offset encoding seed. The non-volatile memory control method as described in item 12 of the scope of patent application, in which: The data template is zero. The non-volatile memory control method described in item 12 of the scope of patent application further includes: Obtaining the data template and the offset cyclic redundancy check code from the non-volatile memory according to a read command issued by the host to the logical address; Operate the cyclic redundancy check engine to use the logical address as an encoding seed; Operate the cyclic redundancy check engine to generate a cyclic redundancy check code for the data template with the encoding seed; and The cyclic redundancy check engine is operated to compare and the cyclic redundancy check code is different from the offset cyclic redundancy check code, and the data template is not used to respond to the host. For example, the non-volatile memory control method described in item 14 of the scope of patent application, wherein the data template and the offset cyclic redundancy check code are obtained from the non-volatile memory according to a mapping information of the logical address, And a mapping information format adopted by the mapping information does not include any uncorrectable flag bits. The non-volatile memory control method as described in item 15 of the scope of patent application, in which: The label unit of the uncorrectable label command is smaller than the data unit managed by the mapping information format. The non-volatile memory control method described in item 11 of the scope of patent application further includes: Regarding an error data obtained from a first area of the non-volatile memory according to a logical address and error checking and correction failed, the error data and a cyclic redundancy check code are programmed into the non-volatile memory A second area of Wherein, the cyclic redundancy check code is read from the first area of the non-volatile memory along with the error data. The non-volatile memory control method described in item 17 of the scope of patent application further includes: Obtaining the error data and the cyclic redundancy check code from the second area of the non-volatile memory according to a read command requested by the host for the logical address; Operate the cyclic redundancy check engine to generate the logical address as an encoding seed; Operate the cyclic redundancy check engine to generate an error cyclic redundancy check code for the error data with the encoding seed; and The cyclic redundancy check engine is operated to compare and the error cyclic redundancy check code is different from the cyclic redundancy check code, and the error data is not returned to the host. The non-volatile memory control method described in item 17 of the scope of patent application, in which: The above-mentioned error checking and correction are derived from a read command from the host to the non-volatile memory. The non-volatile memory control method described in item 17 of the scope of patent application, in which: The above-mentioned error checking and correction result from a garbage collection of the non-volatile memory.

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