TW202038412A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate and a conducting structure. The substrate has a first conductivity type and includes a first isolation area, a first doping area, and a second doping area. The first isolation area is disposed along the circumference of the substrate. The first doping area has the first conductivity type, and the second doping area has a second conductivity type opposite the first conductivity type. The conducting structure is disposed on the substrate, and at least a portion of the conducting structure is located on the first isolation area.

Description

Semiconductor device

The embodiment of the present invention relates to a semiconductor device, and particularly relates to a semiconductor on insulator (SOI) device.

Semiconductor devices can be widely used in various applications. For example, semiconductor devices can be used as rectifiers, oscillators, light emitters, amplifiers, photometers, etc.

With the advancement of science and technology, the semiconductor industry has developed a semiconductor on insulator (SOI) device, which can easily increase the clock pulse and reduce current leakage to become a power-saving integrated circuit (IC) , Part of the mask can be omitted in the manufacturing process to save cost and other advantages.

However, the existing semiconductor devices on an insulating layer are not satisfactory in all aspects. For example, the polysilicon connection located on the active area of the semiconductor device may generate additional parasitic capacitance, thus causing RC delay on the integrated circuit line.

The embodiment of the present invention includes a semiconductor device. The semiconductor device includes a substrate and a conductive structure. The substrate has the first conductivity type. The substrate includes a first isolation area, a first implantation area, and a second implantation area. The first isolation region is arranged around the substrate. The first implanted area has the first conductivity type. The second planting area has a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The conductive structure is disposed on the substrate, and at least part of the conductive structure is located on the first isolation region.

The embodiment of the present invention also includes a semiconductor device. The semiconductor device includes a substrate and a conductive structure. The substrate includes a first isolation region, a second isolation region, a first implantation region, and a second implantation region. The first isolation region is arranged around the substrate. The second isolation region is disposed inside the area surrounded by the first isolation region and separated from the first isolation region. The first implantation area is adjacent to the second isolation area. The second planting area is adjacent to the second isolation area and the first planting area. The conductive structure is disposed on the substrate, and at least part of the conductive structure is located on the first isolation region and the second isolation region.

The following disclosure provides many different embodiments or examples to implement different features of this case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if the embodiment of the present invention describes that a first characteristic part is formed on or above a second characteristic part, it means that it may include an embodiment in which the first characteristic part and the second characteristic part are in direct contact. It may include an embodiment in which an additional characteristic part is formed between the first characteristic part and the second characteristic part, and the first characteristic part and the second characteristic part may not be in direct contact.

It should be understood that additional operation steps may be implemented before, during or after the method, and in other embodiments of the method, part of the operation steps may be replaced or omitted.

In addition, terms related to space may be used, such as "below", "below", "lower", "above", "above", "higher" and similar terms. These space-related terms are used to facilitate the description of the relationship between one element(s) or characteristic part and another (some) elements or characteristic parts in the illustration. These space-related terms include the difference between devices in use or operation. Position, and the position described in the diagram. When the device is turned in different directions (rotated by 90 degrees or other directions), the space-related adjectives used therein will also be interpreted according to the turned position.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings commonly understood by the general artisans to whom the disclosure belongs. It is understandable that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal way. Interpretation, unless specifically defined in the embodiments of the present invention.

The different embodiments disclosed below may use the same reference symbols and/or marks repeatedly. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures discussed.

In the semiconductor device of the embodiment of the present invention, a plurality of electrodes (for example, source/drain, base) can be separated from each other through a conductive structure (including a conductive layer and a dielectric layer), and a part of the conductive structure is disposed in the isolation region (for example, , Above the deep trench isolation (DTI) structure, thereby effectively reducing the parasitic capacitance (parasitic capacitance) and improving the RC delay of the circuit. The following will describe with reference to the embodiment shown in the drawings.

FIG. 1 is a partial top view of a semiconductor device 100 according to an embodiment of the invention. FIG. 2 is a partial cross-sectional view of the semiconductor device 100 taken along the line A-A in FIG. 1. FIG. FIG. 3 is a partial cross-sectional view of the semiconductor device 100 taken along the line B-B in FIG. 1. FIG. It should be noted that, in order to show the features of the embodiments of the present invention more clearly, some elements may be omitted in Figures 1 to 3.

Referring to FIGS. 1 to 3, the semiconductor device 100 of the embodiment of the present invention includes a substrate 10. In some embodiments, the substrate 100 is a silicon substrate, but the embodiment of the present invention is not limited to this. For example, in some other embodiments, the substrate 10 may include some other elemental semiconductor (eg, germanium) substrate. The substrate 10 may also include a compound semiconductor (for example, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide) substrate. The substrate 10 may also include an alloy semiconductor (eg, germanium silicide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide) substrate.

In some embodiments, the substrate 10 may include a semiconductor on insulator (SOI) substrate (for example, a silicon-on-insulator substrate or a germanium-on-insulation substrate). The buried oxide layer on the aforementioned bottom plate and the semiconductor layer arranged on the aforementioned buried oxide layer. In some embodiments, the substrate 10 may include a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination of the foregoing.

In this embodiment, the substrate 10 may have a first conductivity type. For example, the first conductivity type is P-type, which may include P-type dopants such as boron, aluminum, gallium, indium, and thallium. In some embodiments, the doping concentration (for example, the average doping concentration) of the substrate 10 may be 10 ¹⁰ to 10 ¹⁶ cm ⁻³ , but the embodiment of the present invention is not limited thereto. In other embodiments, the first conductivity type may also be N type.

As shown in FIG. 1, the substrate includes a first isolation region 31, and the first isolation region 31 is disposed around the substrate 10. For example, the first isolation region 31 can be used to define an active region and provide electrical isolation required by various device elements in and/or on the substrate 10 formed in the aforementioned active region. In the embodiment of the present invention, the first isolation region 31 is a deep trench isolation (DTI) structure. For example, the depth of the first isolation region 31 may be 0.1 to 100 µm.

In some embodiments, the step of forming the first isolation region 31 (deep trench isolation) may include etching trenches in the substrate 10 and filling the trenches with insulating materials (for example, silicon oxide, silicon nitride, Or silicon oxynitride). The filled trench may have a multilayer structure (for example, a thermal oxide liner layer and silicon nitride filled in the trench). A chemical mechanical polishing (CMP) process may be performed to polish excess insulating material and planarize the upper surface of the first isolation region 31.

In this embodiment, the substrate 10 includes a first implantation area 11 and a second implantation area 21. The first implantation area 11 and the substrate 10 also have the first conductivity type (for example, P type), and the second implantation area The region 21 has a second conductivity type (for example, N-type) opposite to the first conductivity type. Specifically, an appropriate process (for example, an ion implantation process) can be performed to implant P-type dopants such as boron, aluminum, gallium, indium, and thallium into the first implantation region 11 of the substrate 10 of the semiconductor device 100 To form the P-type first implantation region 11, an appropriate process (for example, an ion implantation process) may be performed to implant N-type dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth on the substrate 10 of the semiconductor device 100 In the second planting area 21 to form an N-type second planting area 21. For example, a suitable implantation mask (not shown) can be formed on the substrate 10 first, and an ion implantation process can be performed through the aforementioned implantation shield to form the P-type first implantation area 11; The implantation mask (not shown) is placed on the substrate 10, and the ion implantation process is performed through the aforementioned implantation shield to form the N-type second implantation area 21. In this embodiment, the doping concentration of the first implanted region 11 is greater than the doping concentration of the substrate 10.

As shown in FIG. 1, the semiconductor device 100 further includes a conductive structure 40. The conductive structure 40 is disposed on the substrate 10, and at least part of the conductive structure 40 is located on the first isolation region 31. In this embodiment, the second planting area 21 can be divided into a first electrode 211 and a second electrode 213 through the conductive structure 40. Specifically, the conductive structure 40 can be divided into a first sub-region 40-1 and a second sub-region 40-2, and the first sub-region 40-1 and the second sub-region 40-2 are separated from each other. The first sub-region 40-1 of the conductive structure 40 can be disposed on the junction of the first implantation region 11 and the second implant region 21, and the second subregion 40-2 of the conductive structure 40 can be the second The implant area 21 is divided into a first electrode 211 and a second electrode 213.

Referring to FIGS. 2 and 3 at the same time, the conductive structure 40 (the first sub-region 40-1 and the second sub-region 40-2) includes a dielectric layer 41 and a conductive layer 43, and the conductive layer 43 is disposed on the dielectric layer 41. In some embodiments, a layer of dielectric material (not shown) and a layer of conductive material (not shown) located thereon can be sequentially blanket deposited on the substrate 10, and then the dielectric material The layer and the conductive material layer are patterned by lithography and etching processes to form the dielectric layer 41 and the conductive layer 43, respectively.

In some embodiments, the aforementioned dielectric material layer (used to form the dielectric layer 41) may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material. Formed by electrical materials or a combination of the foregoing. For example, the aforementioned high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO ₃ (BST), Al ₂ O ₃ , other suitable high-k dielectric materials or a combination of the foregoing . In some embodiments, the aforementioned dielectric material layer may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or spin coating. For example, the aforementioned chemical vapor deposition method may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), and rapid temperature chemical vapor deposition. Method (rapid thermal chemical vapor deposition, RTCVD) or plasma enhanced chemical vapor deposition (PECVD).

In some embodiments, the aforementioned conductive material layer (used to form the conductive layer 43) may be formed of polysilicon, but the embodiment of the present invention is not limited to this. In some embodiments, the aforementioned conductive material layer can be made of metal (for example, W, Ti, Al, Cu, Mo, Ni, Pt, similar metal materials or a combination of the foregoing), metal alloys, metal nitrides (for example, nitride Tungsten, molybdenum nitride, titanium nitride, tantalum nitride, similar metal nitrides or combinations of the foregoing), metal silicides (for example, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, similar Or a combination of the foregoing), a metal oxide (for example, ruthenium oxide, indium tin oxide, similar metal oxides or a combination of the foregoing), other suitable conductive materials, or a combination of the foregoing. For example, a chemical vapor deposition process, a physical vapor deposition process (for example, a vacuum evaporation process or a sputtering process), other appropriate processes or a combination of the foregoing can be used to form the aforementioned conductive material. Material layer.

In the embodiment shown in FIGS. 1 to 3, the substrate 10 may further include a second isolation region 33. The second isolation region 33 is disposed inside the area surrounded by the first isolation region 31 and separated from the first isolation region 31. As shown in FIG. 1, the first planting area 11 is adjacent to the second isolation area 33, and the second planting area 21 is adjacent to the second isolation area 33 and the first planting area 11. Specifically, the first planting area 11 and the second planting area 21 may be disposed between the first isolation area 31 and the second isolation area 33, and the first planting area 11 and the second planting area 21 surround the Two isolation area 33.

Similarly, the second isolation region 33 has a deep trench isolation (DTI) structure. For example, the depth of the second isolation region 33 may be 0.1 to 100 µm. In some embodiments, the step of forming the second isolation region 33 (deep trench isolation) may include etching trenches in the substrate 10 and filling the trenches with insulating materials (for example, silicon oxide, silicon nitride, Or silicon oxynitride). The filled trench may have a multilayer structure (for example, a thermal oxide liner layer and silicon nitride filled in the trench). A chemical mechanical polishing (CMP) process may be performed to polish excess insulating material and planarize the upper surface of the second isolation region 33.

In this embodiment, part of the first sub-region 40-1 of the conductive structure 40 is disposed on the first isolation region 31, and a part of the first sub-region 40-1 is disposed on the second isolation region 33. A part of the second sub-region 40-2 is disposed on the first isolation region 31, and a part of the second sub-region 40-2 is disposed on the second isolation region 33. Specifically, as shown in FIG. 1, both ends of the first sub-region 40-1 of the conductive structure 40 are disposed on the first isolation region 31, and the center of the first sub-region 40-1 is disposed on the second isolation region. 33; the two ends of the second sub-region 40-2 of the conductive structure 40 are respectively disposed on the first isolation region 31 and the second isolation region 33. However, the embodiments of the present invention are not limited thereto.

In some embodiments, the conductive layer 43 of the second sub-region 40-2 of the conductive structure 40 can be used as the gate electrode of the semiconductor device 100, and the dielectric layer 41 of the second sub-region 40-2 of the conductive structure 40 can be used as the semiconductor device 100 of the gate dielectric layer, the first electrode 211 of the second implanted region 21 can be used as the source of the semiconductor device 100, the second electrode 213 can be used as the drain of the semiconductor device 100, and the first implanted region 11 can be used as The base (Bulk) of the semiconductor device 100. However, the embodiments of the present invention are not limited thereto. In some embodiments, the first electrode 211 of the second implant region 21 can be used as the drain of the semiconductor device 100, and the second electrode 213 can be used as the source of the semiconductor device 100.

In the embodiment shown in FIGS. 1 to 3, the second sub-region 40-2 of the conductive structure 40 is disposed on the first electrode 211 and the second electrode 213 (source/drain) of the second implantation region 21 ) And the two ends of the second subregion 40-2 of the conductive structure 40 are respectively disposed on the first isolation region 31 and the second isolation region 33; the first subregion 40-1 of the conductive structure 40 is disposed on the first Between the implantation region 11 (base) and the second implantation region 21 (source/drain) and the two ends of the first subregion 40-1 of the conductive structure 40 are disposed on the first isolation region 31, The center of a sub-region 40-1 is set above the second isolation region 33. Since the first isolation region 31 and the second isolation region 33 are deep trench isolation structures, the parasitic capacitance of the semiconductor device 100 can be effectively reduced, and the resistance capacitance delay of the circuit can be improved.

FIG. 4 is a partial top view of a semiconductor device 101 according to another embodiment of the invention. Similarly, in order to show the features of the embodiments of the present invention more clearly, some elements may be omitted in Figure 4.

As shown in FIG. 4, the semiconductor device 101 of the embodiment of the present invention includes a substrate (not labeled) and a conductive structure 45. The substrate has a first conductivity type (for example, P type), and the substrate includes a first isolation region 31, a first implantation region 11 and a second implantation region 21. In this embodiment, the first isolation region 31 is disposed around the substrate; the first implantation region 11 has the same first conductivity type (for example, P-type) as the substrate, and the doping concentration of the first implantation region 11 Greater than the doping concentration of the substrate; the second implanted region 21 has a second conductivity type (eg, N-type) opposite to the first conductivity type; the conductive structure 45 is disposed on the substrate, and at least part of the conductive structure 45 is located in the first isolation Above area 31. In some embodiments, the first isolation region 31 is a deep trench isolation structure, and the conductive structure 45 includes a dielectric layer and a conductive layer. The conductive layer is disposed on the dielectric layer, and the conductive layer may be, for example, a polysilicon layer.

Specifically, the conductive structure 45 can be divided into a first sub-region 45-1 and a second sub-region 45-2. In this embodiment, the first sub-region 45-1 and the second sub-region 45-2 are connected to each other, and the first sub-region 45-1 and the second sub-region 45-2 are cross-shaped (or cross-shaped). ). However, the embodiments of the present invention are not limited thereto. In other embodiments, the first sub-region 45-1 and the second sub-region 45-2 may also be T-shaped, which will not be repeated here.

Similarly, the first sub-region 45-1 of the conductive structure 45 can be disposed on the junction of the first implantation region 11 and the second implant region 21, and the second subregion 45-2 of the conductive structure 45 can be The second planting area 21 is divided into a first electrode 211 and a second electrode 213. In the embodiment shown in Figure 4, both ends of the first sub-region 45-1 of the conductive structure 45 are disposed on the first isolation region 31; both ends of the second sub-region 45-2 of the conductive structure 45 are disposed Above the first isolation region 31. In addition, as shown in FIG. 4, the second sub-region 45-2 of the conductive structure 45 can also divide the first implant region 11 into two regions (electrodes). However, the embodiments of the present invention are not limited thereto.

FIG. 5 is a partial top view of a semiconductor device 102 according to an embodiment of the invention. FIG. 6 is a partial cross-sectional view of the semiconductor device 102 taken along the line C-C in FIG. 5. FIG. 7 is a partial cross-sectional view of the semiconductor device 102 taken along the line D-D in FIG. 5. FIG. It should be noted that, in order to show the features of the embodiments of the present invention more clearly, some elements may be omitted in FIGS. 5-7.

Referring to FIGS. 5-7, the semiconductor device 102 of the embodiment of the present invention includes a substrate 10 and a conductive structure 47. The substrate 10 has a first conductivity type (for example, P type), and the substrate includes a first isolation region 31, a first implantation region 11 and a second implantation region 21. In this embodiment, the first isolation region 31 is disposed around the substrate; the first implantation region 11 has the same first conductivity type (for example, P-type) as the substrate 10, and the doping of the first implantation region 11 The concentration is greater than the doping concentration of the substrate 10; the second implant area 21 has a second conductivity type (for example, N-type) opposite to the first conductivity type; the conductive structure 47 is disposed on the substrate, and at least part of the conductive structure 47 is located in the first Above an isolation area 31. In some embodiments, the first isolation region 31 is a deep trench isolation structure, and the conductive structure 47 includes a dielectric layer 41 and a conductive layer 43. The conductive layer 43 is disposed on the dielectric layer 41, and the conductive layer 43 may be, for example, polysilicon. Floor.

Specifically, the conductive structure 47 can be divided into a first sub-region 47-1 and a second sub-region 47-2. In this embodiment, the first sub-region 47-1 and the second sub-region 47-2 are connected to each other, and the first sub-region 47-1 and the second sub-region 47-2 are T-shaped, but the embodiment of the present invention is not Limit this.

In this embodiment, the second sub-region 47-2 of the conductive structure 47 can divide the second implant region 21 into a first electrode 211 and a second electrode 213. As shown in FIG. 5, both ends of the second sub-region 47-2 of the conductive structure 47 are disposed on the first isolation region 31. In addition, in this embodiment, the first planting area 11 may be adjacent to the second planting area 21. Specifically, referring to FIGS. 5 and 6, the first implantation area 11 may be adjacent to the first electrode 211 of the second implantation area 21, and the first electrode 211 of the second implantation area 21 may be adjacent to the first electrode 211. Two second electrodes 213 in the implantation area 21. That is, the first electrode 211 of the second implantation area 21 may be located between the first implantation area 11 and the second electrode 213 of the second implantation area 21.

In the embodiment shown in FIG. 5 to FIG. 7, the second sub-region 47-2 (the conductive layer 43) of the conductive structure 47 can be used as the gate of the semiconductor device 102, and the first implant region 21 The electrode 211 can be used as the source of the semiconductor device 102, the second electrode 213 can be used as the drain of the semiconductor device 102, and the first implant region 11 can be used as the base (Bulk) of the semiconductor device 102.

In the embodiment shown in FIG. 5 to FIG. 7, a plurality of contacts 51 of the semiconductor device 102 are further shown. These contacts may be respectively disposed in the first implantation area 11 (base) of the semiconductor device 102. Electrode), the first electrode 211 (source) of the second planting area 21 and the second electrode 213 (drain) of the second planting area 21. It should be noted that the number and positions of the contacts 51 are not limited to the embodiments shown in FIGS. 5-7. For example, in some embodiments, the first sub-region 47-1 of the conductive structure 47 may also be provided with a plurality of contacts 51, which may be determined according to actual requirements, and will not be repeated here.

FIG. 8 is a partial top view of a semiconductor device 103 according to another embodiment of the invention. Similarly, in order to show the features of the embodiments of the present invention more clearly, some elements may be omitted in Figure 8.

As shown in FIG. 8, the semiconductor device 103 of the embodiment of the present invention includes a substrate (not labeled) and a conductive structure 49. The substrate has a first conductivity type (for example, P type), and the substrate includes a first isolation region 31, a first implantation region 11 and a second implantation region 21. In this embodiment, the first isolation region 31 is disposed around the substrate; the first implantation region 11 has the same first conductivity type (for example, P-type) as the substrate, and the doping concentration of the first implantation region 11 Greater than the doping concentration of the substrate; the second implanted region 21 has a second conductivity type (for example, N-type) opposite to the first conductivity type; the conductive structure 49 is disposed on the substrate, and at least part of the conductive structure 49 is located in the first isolation Above area 31. In some embodiments, the first isolation region 31 is a deep trench isolation structure, and the conductive structure 49 includes a dielectric layer and a conductive layer. The conductive layer is disposed on the dielectric layer, and the conductive layer may be, for example, a polysilicon layer.

Specifically, the conduction structure 49 can be divided into a first sub-region 49-1 and a second sub-region 49-2. In this embodiment, the first sub-region 49-1 and the second sub-region 49-2 are connected to each other, and the first sub-region 49-1 and the second sub-region 49-2 are substantially T-shaped. However, the embodiments of the present invention are not limited thereto. In other embodiments, the first sub-region 49-1 and the second sub-region 49-2 may also have other shapes, which may be determined according to actual requirements, and will not be repeated here.

Similarly, the first sub-region 49-1 of the conductive structure 49 can be disposed on the junction of the first implantation region 11 and the second implant region 21, and the second subregion 49-2 of the conductive structure 49 can be The second planting area 21 is divided into a first electrode 211 and a second electrode 213. In the embodiment shown in FIG. 8, both ends of the first sub-region 49-1 of the conductive structure 49 are disposed on the first isolation region 31; both ends of the second sub-region 49-2 of the conductive structure 49 are disposed Above the first isolation region 31.

In addition, as shown in FIG. 8, in this embodiment, the first implantation area 11 and the second implantation area 21 may be formed in an L-shaped structure. Specifically, the first implantation area 11 may be adjacent to the first electrode 211 of the second implantation area 21, and the extension direction of the first implantation area 11 is perpendicular to the first electrode 211 and the second implantation area 21. The extension direction of the two electrodes 213. However, the embodiments of the present invention are not limited thereto.

It should be noted that although the foregoing embodiments are all described with the first conductivity type being P-type and the second conductivity type being N-type, the embodiments of the present invention are not limited thereto. In some embodiments, the first conductivity type may be N-type and the second conductivity type is P-type.

In summary, in the semiconductor device of the embodiment of the present invention, a plurality of electrodes (e.g., source/drain, base) can be separated from each other through a conductive structure (including a conductive layer and a dielectric layer), and part of the conductive structure (e.g., The end of the conductive structure is disposed on the isolation region (for example, a deep trench isolation (DTI) structure). Therefore, the parasitic capacitance in the semiconductor device can be effectively reduced, and the RC delay of the circuit can be improved.

The foregoing text outlines the characteristic components of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Without departing from the spirit and scope of the embodiments of the present invention, various changes, substitutions or modifications can be made to the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the appended patent scope. In addition, although the present invention has been disclosed as above in several preferred embodiments, they are not intended to limit the present invention, and not all advantages have been described in detail here.

Each claim of the present disclosure may be a separate embodiment, and the scope of the present disclosure includes each claim of the present disclosure and the combination of each embodiment with each other.

100, 101, 102, 103: semiconductor device 10: substrate 11: first implantation area 21: second implantation area 211: first electrode 213: second electrode 31: first isolation area 33: second isolation area 40 , 45, 47, 49: conductive structure 40-1, 45-1, 47-1, 49-1: first sub-region 40-2, 45-2, 47-2, 49-2: second sub-region 41 : Dielectric layer 43: Conductive layer 51: Contact AA, BB, CC, DD: Section line

The embodiments of the present invention will be described in detail below in conjunction with the drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the element may be enlarged or reduced to clearly show the technical features of the embodiment of the present invention. FIG. 1 is a partial top view of a semiconductor device according to an embodiment of the invention. FIG. 2 is a partial cross-sectional view of the semiconductor device taken along line A-A in FIG. 1. FIG. FIG. 3 is a partial cross-sectional view of the semiconductor device taken along line B-B in FIG. 1. FIG. FIG. 4 is a partial top view of a semiconductor device according to another embodiment of the invention. FIG. 5 is a partial top view of a semiconductor device according to an embodiment of the invention. Fig. 6 is a partial cross-sectional view of the semiconductor device taken along line C-C in Fig. 5; Fig. 7 is a partial cross-sectional view of the semiconductor device taken along the line D-D in Fig. 5. FIG. 8 is a partial top view of a semiconductor device according to another embodiment of the invention.

100: Semiconductor device

11: The first planting area

21: The second planting area

211: first electrode

213: second electrode

31: The first quarantine area

33: The second quarantine area

40: Conduction structure

40-1: The first sub-area

40-2: The second sub-area

A-A, B-B: Section line

Claims (20)

A semiconductor device, comprising: a substrate having a first conductivity type, the substrate comprising: 　a first isolation region disposed around the substrate; 　a first implantation region having the first conductivity type; and a first Two implanted regions having a second conductivity type, the second conductivity type being opposite to the first conductivity type; and a conductive structure disposed on the substrate, and at least part of the conductive structure is located on the first isolation region . In the semiconductor device described in claim 1, wherein the first isolation region is a deep trench isolation structure. According to the semiconductor device described in claim 2, wherein the conduction structure includes: a dielectric layer; and a conductive layer disposed on the dielectric layer. The semiconductor device described in item 3 of the scope of patent application, wherein the conductive layer is a polysilicon layer. According to the semiconductor device described in item 3 of the scope of patent application, the second implanted region is divided into a first electrode and a second electrode through the conductive structure. According to the semiconductor device described in claim 5, the conduction structure is divided into a first sub-region and a second sub-region, and the second implant region is divided into the first sub-region by the second sub-region The electrode and the second electrode. According to the semiconductor device described in item 6 of the scope of patent application, the first sub-region is disposed on the junction of the first implantation region and the second implantation region. According to the semiconductor device described in claim 7, wherein the first implantation region and the second implantation region form an L-shaped structure. According to the semiconductor device described in claim 6, wherein the first sub-region and the second sub-region are connected to each other. According to the semiconductor device described in claim 9, wherein the first sub-region and the second sub-region are cross-shaped or T-shaped. According to the semiconductor device described in claim 6, wherein the first sub-region and the second sub-region are separated from each other. The semiconductor device described in claim 11, wherein the substrate further includes a second isolation region, and the second isolation region is disposed inside the region surrounded by the first isolation region and separated from the first isolation region . For the semiconductor device described in claim 12, part of the first sub-region is disposed on the first isolation region, part of the first sub-region is disposed on the second isolation region, and part of the second The sub-region is disposed on the first isolation region, and a part of the second sub-region is disposed on the second isolation region. In the semiconductor device described in claim 13, wherein the second isolation region is a deep trench isolation structure. According to the semiconductor device described in claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The semiconductor device described in claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. A semiconductor device, comprising: a substrate, the substrate comprising: 　a first isolation region arranged around the substrate; 　a second isolation region arranged in the region surrounded by the first isolation region and the first isolation region The isolation area is separated; 　a first implantation area adjacent to the second isolation area; and a second implantation area adjacent to the second isolation area and the first implantation area; and a conduction structure arranged On the substrate, and at least part of the conductive structure is located on the first isolation region and the second isolation region. The semiconductor device described in claim 17, wherein the substrate and the first implanted region have a first conductivity type, the second implanted region has a second conductivity type, and the second conductivity type is The first conductivity type is opposite. According to the semiconductor device described in claim 17, wherein the first isolation region and the second isolation region are deep trench isolation structures. The semiconductor device according to claim 17, wherein the conduction structure includes a first sub-region and a second sub-region that are separated from each other, and the first sub-region is disposed in the first implantation region and the second subregion. Above the junction of the implantation area, the second sub-region divides the second implantation area into a first electrode and a second electrode.

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