TW202036734A - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a chip package structure is provided. A circuit substrate and a chip are provided. The circuit substrate is formed with a two-stage thermosetting adhesive layer. An active surface of the chip is formed with a conductive pillar and a support pillar. The circuit substrate is passed through the two-stage thermosetting adhesive layer to abut the active surface of the chip. The two-stage thermosetting adhesive layer is dropped between the conductive pillar and the support pillar. A bonding process is performed, and the chip is electrically connected to the circuit substrate through the conductive pillar and supported by the support pillar to be positioned on the circuit substrate. The two-stage thermosetting adhesive layer is fully cured. An encapsulant is formed on the circuit substrate to encapsulate the chip, the conductive pillar, the support pillar, and the two-stage thermosetting adhesive layer. A chip package structure is also provided.

Description

Chip packaging structure and manufacturing method thereof

The present invention relates to a package structure and a manufacturing method thereof, and particularly relates to a chip package structure and a manufacturing method thereof.

Generally speaking, when traditional chips are bonded to a substrate, such as flip chip mounting, since the bonding part of the chip is often located in the center of the chip, there is no support on both sides of the chip, and it is easy to cause the chip due to uneven force during bonding. Tilt, causing poor electrical connection. In addition, since the stress is concentrated on the joint, it is easy to break at the joint, causing the possibility of electrical joint failure. The above-mentioned problems will make the reliability of the chip package structure worse. Therefore, how to improve the reliability of the chip package structure will become an important issue.

The present invention provides a chip package structure and a manufacturing method thereof, which can reduce the phenomenon of chip tilt and reduce the possibility of joint fracture, thereby improving the reliability of the chip package structure.

The method for manufacturing a chip package structure provided by the present invention includes the following steps. A circuit substrate and a chip are provided, wherein the circuit substrate is formed with a two-stage thermosetting adhesive layer. In addition, conductive pillars and supporting pillars are formed on the active surface of the wafer. The circuit substrate is abutted against the active surface of the chip through the two-stage thermosetting adhesive layer, and the two-stage thermosetting adhesive layer is dropped between the conductive pillar and the supporting pillar. Then, the bonding process is performed, and the chip is electrically connected to the circuit substrate through the conductive pillars, and is supported by the supporting pillars and positioned on the circuit substrate. A packaging glue is formed on the circuit substrate to cover the chip, the conductive pillar, the supporting pillar and the two-stage thermosetting glue layer. The two-stage thermosetting adhesive layer is completely cured.

In an embodiment of the present invention, the above-mentioned manufacturing method further includes pre-curing the two-stage thermosetting adhesive layer before the circuit substrate abuts the active surface of the chip through the two-stage thermosetting adhesive layer.

In an embodiment of the present invention, the above-mentioned manufacturing method further includes forming a primer layer between the circuit substrate and the active surface of the chip before forming the encapsulant on the circuit substrate to cover the conductive pillars, the supporting pillars and the two Stage thermosetting adhesive layer.

In an embodiment of the present invention, the above-mentioned two-stage thermosetting adhesive layer is in a paste form. In the process of making the circuit substrate abut the active surface of the chip through the two-stage thermosetting adhesive layer, the two-stage thermosetting adhesive layer is compressed and deformed to Cover the conductive column and the support column.

The chip packaging structure of the present invention includes a circuit substrate, a chip, a two-stage thermosetting adhesive layer and a packaging glue. The chip has an active surface, and the active surface is provided with conductive pillars and supporting pillars. The chip is electrically connected to the circuit substrate through the conductive column, and is supported by the supporting column and positioned on the circuit substrate. The two-stage thermosetting adhesive layer is arranged between the active surface of the chip and the circuit substrate. The packaging glue is arranged on the circuit substrate to cover the chip, the conductive pillar, the support pillar and the two-stage thermosetting glue layer.

In an embodiment of the present invention, the above-mentioned two-stage thermosetting adhesive layer connects the circuit substrate and the chip, and falls between the conductive pillar and the supporting pillar.

In an embodiment of the present invention, the above-mentioned two-stage thermosetting adhesive layer connects the circuit substrate and the chip, and covers the conductive pillars and the supporting pillars.

In an embodiment of the present invention, it further includes a primer layer. The primer layer is arranged between the circuit substrate and the active surface of the chip to cover the conductive pillars, the supporting pillars and the two-stage thermosetting adhesive layer.

In an embodiment of the present invention, the aforementioned wafer has a central area and an edge area, the central area is farther from the sidewall of the wafer than the edge area, the conductive pillar is located in the central area, and the support pillar is located in the edge area.

In an embodiment of the present invention, the aforementioned chip package structure includes a plurality of conductive pillars and a plurality of supporting pillars, and the plurality of conductive pillars are located between the plurality of supporting pillars.

Based on the above, the wafer of the present invention has not only conductive pillars for electrical connection, but also support pillars for supporting and positioning. Therefore, the phenomenon of uneven force caused by wafer tilt during wafer bonding can be reduced. In addition, since the stress can be more uniformly dispersed, the possibility of electrical bonding failure caused by the fracture of the joint can be reduced, thereby improving the reliability of the chip package structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1D are schematic cross-sectional views of a manufacturing process of a chip package structure 100 according to an embodiment of the invention. Please refer to FIG. 1A. First, a circuit substrate 110 and a chip 120 are provided. In detail, the circuit substrate has a plurality of pads 112 and a solder mask 114. The solder mask 114 covers the conductive lines (not shown) in the circuit substrate 110 and exposes a plurality of pads 112 to facilitate subsequent electrical connections of the pads 112. The wafer 120 has an active surface 120a. The chip 120 is, for example, a memory chip, a microprocessor chip, or a special application integrated circuit chip (ASIC). However, the invention does not limit the type of the chip 120, and it may be determined according to actual design requirements.

Please continue to refer to FIG. 1A, the circuit substrate 110 is formed with a two-stage thermosetting adhesive layer 130. The two-stage thermosetting adhesive layer 130 is, for example, a b-stage epoxy resin. The method of forming the two-stage thermosetting adhesive layer 130 may include a spin coating process or a printing process. The two-stage thermosetting adhesive layer is, for example, a liquid (Liquid) at the A stage, a partially cured semi-solid (Jelly) at the B stage, and a fully cured solid (Solid) epoxy resin at the C stage ( epoxy resin). In this embodiment, as shown in FIG. 1A, the two-stage thermosetting adhesive layer 130 may be first coated on the substrate in a liquid manner, and then pre-curing the two-stage thermosetting adhesive layer 130 through a heating procedure. Here, to partially cure the A-stage two-stage thermosetting adhesive layer to a B-stage two-stage thermosetting is called the pre-curing process. In some embodiments, the two-stage thermosetting adhesive layer 130 may be surrounded by the pad 112.

On the other hand, the active surface 120 a of the wafer 120 is formed with conductive pillars 122 and supporting pillars 124. In detail, the conductive pillar 122 is located in the central area 1201 of the wafer 120; and the support pillar 124 is located in the edge area 1202 of the wafer 120, wherein the central area 1201 is farther from the sidewall 120s of the wafer 120 than the edge area 1202. In other words, with respect to the supporting pillars 124, the conductive pillars 122 are farther away from the sidewall 120s of the wafer 120. In some embodiments, there may be multiple conductive pillars 122 and supporting pillars 124, and the multiple conductive pillars 122 are located between the multiple supporting pillars 124. It should be noted that although FIG. 1A only has two conductive pillars 122 and two supporting pillars 124, the present invention does not limit the number of conductive pillars 122 and supporting pillars 124, which can be determined according to actual design requirements.

1B, the circuit substrate 110 is bonded to the chip 120 facing downwards. The circuit substrate 110 abuts against the active surface 120a of the chip 120 through the two-stage thermosetting adhesive layer 130, and the two-stage thermosetting adhesive layer 130 falls on the conductive pillars 122 and Between the support columns 124. In other words, the two-stage thermosetting adhesive layer 130 is disposed between the active surface 120 a of the chip 120 and the circuit substrate 110 and connects the circuit substrate 110 and the chip 120. In detail, the circuit substrate 110, the conductive pillars 122, the support pillars 124 and the chip 120 surround the two-stage thermosetting adhesive layer 130, and the conductive pillars 122 and the support pillars 124 abut on the pads 112 of the circuit substrate 110 correspondingly. In this embodiment, since the pre-cured two-stage thermosetting adhesive layer 130 is also partially adhesive, it can assist the circuit substrate 110 to temporarily fix it on the active surface 120a of the chip 120 before the bonding process.

Then, the bonding process is performed, and the chip 120 is electrically connected to the circuit substrate 110 through the conductive pillars 122 and is supported by the supporting pillars 124 to be positioned on the circuit substrate 110. The bonding procedure is, for example, a flip chip bonding procedure. In some embodiments, the support column 124 may also have a conductive function in addition to the supporting function, so that the flexibility of the circuit layout can be increased. The material selected for the support pillars 124 and the conductive pillars 122 can be copper, silver, gold or other conductive alloys. In this embodiment, the support pillars 124 and the conductive pillars 122 are copper pillars, and a material containing The solder cap (not numbered) is used for bonding with the pad 112 on the circuit substrate 110; in this embodiment, the shape of the solder cap on the top of the support pillar 124 and the conductive pillar 122 is hemispherical. In other embodiments, it is also An electroplating method can be used to form a flat-top solder layer; however, the present invention is not limited to this, and the support pillar 124 may also have no conductive function, depending on the chip design. In this embodiment, in addition to the conductive pillars 122 for electrical connection, the wafer 120 also has support pillars 124 for supporting and positioning. Therefore, the wafer 120 can reduce uneven forces that may cause the wafer to tilt during bonding. phenomenon. In addition, since the stress can be more uniformly dispersed, the possibility of electrical bonding failure due to the fracture of the joint is reduced, and the reliability of the chip package structure 100 is improved.

Please refer to FIG. 1C to fully cure the two-stage thermosetting adhesive layer 130. For example, a heating process is used for curing, and the heating process is, for example, temperature-rising baking. In other words, the semi-cured two-stage thermosetting adhesive layer 130 may be heated, so that the semi-cured two-stage thermosetting adhesive layer 130 becomes a fully cured two-stage thermosetting adhesive layer 130a. Next, an encapsulant 140 is formed on the circuit substrate 110 to cover the chip 120, the conductive pillar 122, the support pillar 124, and the two-stage thermosetting adhesive layer 130a. The material of the encapsulant 140 is, for example, Epoxy Molding Compound (EMC). In some embodiments, the step of turning up and down may be selectively performed between the curing step and the step of forming the encapsulant 140, but the present invention is not limited to this. At this point, the chip package structure 100 is substantially completed. It is worth mentioning that the two-stage thermosetting adhesive layer 130 fully curing process can also be heated and heated after the packaging adhesive 140 is molded.

1D, in some other embodiments, before forming the encapsulant 140 on the circuit substrate 110, it may further include forming a primer layer 150 between the circuit substrate 110 and the active surface 120a of the chip 120 to cover The conductive pillar 122, the supporting pillar 124 and the two-stage thermosetting adhesive layer 130a. In detail, the primer layer 150 is filled in the gap between the circuit substrate 110 and the active surface 120a of the chip 120. The material of the primer layer 150 may be different or the same as that of the encapsulant 140.

It must be noted here that the following embodiments use the component numbers and part of the content of the above embodiments, wherein the same or similar reference numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A to 2D are schematic cross-sectional views of a manufacturing process of a chip package structure 200 according to an embodiment of the invention. Please refer to FIGS. 2A to 2D at the same time. The difference between the embodiment of FIGS. 2A to 2D and the embodiment of FIGS. 1A to 1D is that the circuit substrate 110 is made to contact the active surface 120a of the chip 120 through the two-stage thermosetting adhesive layer 230 Previously, the two-stage thermosetting adhesive layer 230 did not undergo a heating pre-curing process.

In detail, the two-stage thermosetting adhesive layer 230 is jelly at the beginning. When the circuit substrate 110 is brought into contact with the active surface 120a of the chip 120 through the two-stage thermosetting adhesive layer 230, the two-stage thermosetting adhesive layer 230 is slightly deformed outwards under pressure due to the flip chip bonding to cover the conductive pillar 122 and the support pillar 124, as shown in FIG. 2B. Then, the two-stage thermosetting adhesive layer 230 is heated to be fully cured to form a two-stage thermosetting adhesive layer 230a, as shown in FIG. 2C. In the chip packaging structure 200 of this embodiment, the two-stage thermosetting adhesive layer 230 first covers the conductive pillars 122 and the supporting pillars 124, and then covers the chip 120, the conductive pillars 122, the supporting pillars 124, and the two-stage thermosetting adhesive through the packaging glue 140 The layer 230 can further provide buffering, moisture-proof and dust-proof effects, thereby improving the reliability of the chip package structure 200. In addition, the two-stage heating and complete curing process of the thermosetting adhesive layer 230 can also be performed after the molding of the encapsulant 140, and the heating timing can be before or after the molding.

In summary, in addition to the conductive pillars for electrical connection, the wafer of the present invention also has support pillars for supporting positioning. Therefore, the uneven force during the bonding of the wafer can reduce the phenomenon that the wafer tilts due to uneven force. In addition, since the stress can be more uniformly dispersed, the possibility of electrical bonding failure caused by the fracture of the joint can be reduced. In turn, the reliability of the chip package structure is improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 200: chip package structure 110: circuit board 112: Pad 114: Solder mask 120: chip 1201: central area 1202: fringe zone 120a: active surface of the chip 120s: sidewall of the chip 122: Conductive column 124: Support column 130, 130a, 230, 230a: two-stage thermosetting adhesive layer 140: Encapsulation colloid 150: primer layer

1A to 1D are schematic cross-sectional views of a manufacturing process of a chip package structure according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views of a manufacturing process of a chip package structure according to an embodiment of the invention.

100: Chip package structure

110: circuit board

112: Pad

114: Solder mask

120: chip

120a: active surface of the chip

122: Conductive column

124: Support column

130a: Two-stage thermosetting adhesive layer

140: Encapsulation colloid

Claims (10)

A method for manufacturing a chip packaging structure includes: A circuit substrate and a chip are provided, wherein the circuit substrate is formed with a two-stage thermosetting adhesive layer, and the active surface of the chip is formed with conductive pillars and support pillars; Make the circuit substrate abut the active surface of the chip through the two-stage thermosetting adhesive layer, and make the two-stage thermosetting adhesive layer fall between the conductive pillar and the supporting pillar, and then perform a bonding process, the chip passes through the The conductive column is electrically connected to the circuit substrate, and is supported by the support column and positioned on the circuit substrate; Forming a packaging glue on the circuit substrate to cover the chip, the conductive pillar, the support pillar and the two-stage thermosetting adhesive layer; and Heating completely cures the two-stage thermosetting adhesive layer. The manufacturing method of the chip package structure as described in item 1 of the scope of patent application further includes: Before allowing the circuit substrate to abut the active surface of the chip through the two-stage thermosetting adhesive layer, the two-stage thermosetting adhesive layer is pre-cured. The manufacturing method of the chip package structure as described in item 1 of the scope of patent application further includes: Before forming the encapsulant on the circuit substrate, a primer layer is formed between the circuit substrate and the active surface of the chip to cover the conductive pillar, the support pillar and the two-stage thermosetting adhesive layer. According to the method for manufacturing the chip package structure described in the first item of the patent application, the two-stage thermosetting adhesive layer is in a paste form, and the circuit substrate is brought into contact with the active surface of the chip through the two-stage thermosetting adhesive layer In this case, the two-stage thermosetting adhesive layer is compressed and deformed to cover the conductive pillar and the support pillar. A chip packaging structure, including: Circuit board The chip has an active surface, wherein the active surface is provided with conductive pillars and support pillars, the chip is electrically connected to the circuit substrate through the conductive pillars, and is supported by the support pillars to be positioned on the circuit substrate; A two-stage thermosetting adhesive layer is disposed between the active surface of the chip and the circuit substrate; and The packaging glue is arranged on the circuit substrate to cover the chip, the conductive pillar, the support pillar and the two-stage thermosetting glue layer. According to the chip package structure described in item 5 of the scope of patent application, the two-stage thermosetting adhesive layer connects the circuit substrate and the chip and falls between the conductive pillar and the support pillar. According to the chip package structure described in item 5 of the patent application, the two-stage thermosetting adhesive layer connects the circuit substrate and the chip, and covers the conductive pillar and the support pillar. The chip package structure described in item 5 of the scope of patent application further includes a primer layer disposed between the circuit substrate and the active surface of the chip to cover the conductive pillar, the support pillar and the two-stage thermosetting Glue layer. For the chip package structure described in claim 5, the chip has a central area and an edge area, the central area is farther from the sidewall of the chip than the edge area, the conductive pillar is located in the central area, and the support pillar is located The marginal zone. According to the chip package structure described in claim 5, the chip package structure includes a plurality of the conductive pillars and a plurality of the supporting pillars, and the conductive pillars are located between the supporting pillars.

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