TW202034046A - Display panel and manufacturing method thereof - Google Patents

Abstract

A display panel includes a substrate, a planarization layer, and a sealant. The planarization layer is disposed on the substrate. The planarization layer has a plurality of through holes and a plurality of concavities. The display panel has a display region and a frame region surrounding the display region. The through holes are located inside the display region and penetrate through the planarization layer. The concavities are positioned on a surface of the planarization layer away from the substrate and are located inside the frame region. Maximum widths of the concavities are shorter than that of the through holes. The sealant covers the concavities and has a plurality of protrusions corresponding to the concavities.

Description

Display panel and manufacturing method thereof

This disclosure relates to a display panel and a manufacturing method thereof.

In recent years, as electronic devices with a high screen-to-body ratio have become popular, narrowing the display frame has become one of the hot research directions. However, the use of a narrow frame design makes the area where the sealant can be applied to the display panel is limited, and the ability of the display edge to withstand impact also decreases.

In view of this, one purpose of the present disclosure is to provide a display panel with improved edge impact resistance and a manufacturing method thereof.

To achieve the above objective, according to some embodiments of the present disclosure, a display panel includes a first substrate, a first flat layer, and a sealant. The first flat layer is disposed on the first substrate and has a plurality of through holes and a plurality of concave holes. The display panel has a display area and a border area surrounding the display area. The through hole is located in the display area and penetrates the first flat layer. The concave hole is located on the surface of the first flat layer away from the first substrate and located in the frame area. The maximum width of the recessed hole is smaller than the maximum width of the through hole. The sealant covers the concave holes, and the corresponding concave holes have plural A protrusion.

In one or more embodiments of the present disclosure, the frame area has an exit area, and the recessed hole is located in the exit area.

In one or more embodiments of the present disclosure, the border area has a non-outline area. The first flat layer further includes a plurality of first recesses located in the non-outgoing area. The maximum width of the first recess is greater than the maximum width of the concave hole. The sealant has a plurality of first raised portions corresponding to the first concave portion.

In one or more embodiments of the present disclosure, the maximum width of the first recess is substantially equal to the maximum width of the through hole.

In one or more embodiments of the present disclosure, the distance between two adjacent concave holes is substantially twice the maximum width of the concave holes.

In one or more embodiments of the present disclosure, the depth of the recessed hole is less than or equal to half of the thickness of the first flat layer.

In one or more embodiments of the present disclosure, the depth of the recessed hole is in the range of 1 μm to 1.5 μm.

In one or more embodiments of the present disclosure, the concave hole is located in the area where the sealant is vertically projected on the first flat layer.

In one or more embodiments of the present disclosure, part of the concave holes are arranged in a plurality of straight rows. The straight rows are arranged along the first direction, and two adjacent straight rows of recessed holes are displaced from each other in a second direction substantially perpendicular to the first direction.

In one or more embodiments of the present disclosure, the display panel further includes a second substrate and a second flat layer. The second flat layer is disposed on the side of the second substrate facing the first flat layer, and has a plurality of second recesses located in the frame area. The sealant has a plurality of second raised portions corresponding to the second recessed portion.

In one or more embodiments of the present disclosure, the maximum width of the second recessed portion is substantially equal to the maximum width of the concave hole.

According to some embodiments of the present disclosure, a method for manufacturing a display panel for manufacturing a display panel, wherein the display panel includes a first substrate and a first planar layer on the first substrate, and has a display area and a frame area surrounding the display area . The display panel manufacturing method includes: exposing a first flat layer through a photomask, wherein the photomask has a plurality of first openings and a plurality of second openings smaller than the first openings, facing the display area, and the second openings facing the frame area Develop the first flat layer to form a plurality of through holes corresponding to the first opening and a plurality of first concave holes corresponding to the second opening on the first flat layer, the maximum width of the first concave hole is smaller than that of the through hole Maximum width; and covering the sealant on the first concave hole, so that the sealant forms a plurality of first protrusions corresponding to the first concave hole.

In one or more embodiments of the present disclosure, the display panel further includes a second substrate and a second flat layer on the second substrate. The display panel manufacturing method further includes: exposing the second flat layer through a photomask; developing the second flat layer to form a plurality of second concave holes corresponding to the second opening on the second flat layer; The concave hole is covered with sealant, so that the sealant forms a plurality of second protrusions corresponding to the second concave hole.

In summary, the display panel of the present disclosure is provided with recessed holes in the flat layer (which can be the flat layer of the thin film transistor array substrate or the flat layer of the color filter substrate) in the frame area, and the sealant coated on the flat layer corresponds to the hole With protrusions, as a result, the contact surface area of the sealant and the thin film transistor array substrate/color filter substrate increases, and the protrusions can disperse external forces in multiple directions, making the present disclosure The impact resistance of the edge of the display panel shown is significantly improved compared to the existing display panel.

100‧‧‧Display Panel

101‧‧‧Display area

102‧‧‧Frame area

103‧‧‧Outline Area

104‧‧‧Non-outline area

200‧‧‧Thin Film Transistor Array Substrate

210‧‧‧First substrate

220‧‧‧First flat layer

221‧‧‧Through hole

222‧‧‧Concave hole

223‧‧‧The first depression

224‧‧‧Straight

230‧‧‧First electrode layer

240‧‧‧First alignment layer

300‧‧‧Color filter substrate

310‧‧‧Second substrate

320‧‧‧Second flat layer

321‧‧‧Second depression

330‧‧‧Second electrode layer

340‧‧‧Second alignment layer

410‧‧‧Display medium layer

420‧‧‧Frame glue

421‧‧‧Protrusion

422‧‧‧Second Uplift

500‧‧‧Display panel manufacturing method

900‧‧‧Mask

901‧‧‧First opening

902‧‧‧Second opening

D1, D2, D3‧‧‧Depth

G‧‧‧Pitch

X1‧‧‧First direction

X2‧‧‧Second direction

W1, W2, W3‧‧‧Maximum width

WS‧‧‧Width

In order to make the above and other objectives, features, advantages and implementations of the present disclosure more comprehensible, the description of the accompanying drawings is as follows: FIG. 1 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

FIG. 2 is a top view of the first flat layer of the display panel shown in FIG. 1. FIG.

FIG. 3 is a partial enlarged top view of the first flat layer of the display panel shown in FIG. 1. FIG.

FIG. 4 is a partial enlarged top view of the first flat layer of the display panel according to another embodiment of the present disclosure.

FIG. 5 is a flowchart illustrating a method of manufacturing a display panel according to an embodiment of the present disclosure.

6 to 10 are schematic diagrams of the display panel manufacturing method shown in FIG. 5 at different stages.

In order to make the description of this disclosure more detailed and complete, please refer to the attached drawings and the various embodiments described below. The elements in the drawings are not drawn to scale, and are provided only to illustrate the present disclosure. Many practical details are described below to provide a comprehensive understanding of this disclosure. However, those with ordinary skills in the relevant fields should When it is understood that this disclosure can be implemented without one or more practical details, these details should not be used to limit this disclosure.

Please refer to Figure 1 and Figure 2. FIG. 1 is a cross-sectional view of the display panel 100 according to an embodiment of the present disclosure, and FIG. 2 is a top view of the first flat layer 220 of the display panel 100 shown in FIG. 1. The display panel 100 has a display area 101 and a frame area 102 surrounding the display area 101. The display panel 100 includes a thin film transistor array substrate 200, a color filter substrate 300, a display medium layer 410 and a sealant 420. In this embodiment, the display panel 100 is a liquid crystal display panel, the display medium layer 410 is liquid crystal, and the thin film transistor array substrate 200 and the color filter substrate 300 are located on opposite sides of the display medium layer 410. The sealant 420 is connected between the thin film transistor array substrate 200 and the color filter substrate 300, and is distributed along the frame area 102 to surround the display area 101, so that the display medium layer 410 is located on the thin film transistor array substrate 200 and the color filter substrate 300 and the sealant 420 together form a space. In some embodiments, the display panel 100 further includes a spacer (not shown), which is supported between the thin film transistor array substrate 200 and the color filter substrate 300, so that the thin film transistor array substrate 200 and the color filter substrate 300 Maintain a fixed spacing.

It should be noted that, in order to clearly convey the technical focus of the present disclosure, FIG. 1 only schematically depicts part of the layers and structures of the thin film transistor array substrate 200 and the color filter substrate 300. Depending on practical requirements, the thin film transistor array substrate 200 and the color filter substrate 300 may further include other layers or structures.

As shown in Figure 1, the thin film transistor array substrate 200 includes a first substrate 210, a first flat layer 220, a first electrode layer 230, and a first alignment layer 240. The first flat layer 220 is disposed on the first substrate 210 and has a plurality of through holes 221 (only one is representatively shown in FIG. 1) and a plurality of concave holes 222. The through hole 221 is located in the display area 101 and penetrates the first flat layer 220. The through hole 221 is used for connecting the first electrode layer 230 to the thin film transistor (not shown) below. The concave hole 222 is located on the upper surface of the first flat layer 220 away from the first substrate 210 and is located in the frame area 102. The depth D2 of the concave hole 222 is smaller than the depth D1 of the through hole 221, and the maximum width W2 of the concave hole 222 is smaller than the maximum width W1 of the through hole 221. In some embodiments, the maximum width W1 of the through hole 221 is substantially 5 μm, and the maximum width W2 of the concave hole 222 is substantially 3 μm.

In some embodiments, as shown in FIG. 1, in the direction perpendicular to the first substrate 210, the depth D2 of the recessed hole 222 is less than or equal to half of the thickness of the first flat layer 220 (that is, the thickness of the through hole 221 Half the depth D1). In some embodiments, the thickness of the first flat layer 220 is substantially in the range of 2 μm to 3 μm, and the depth D2 of the recessed hole 222 is substantially in the range of 1 μm to 1.5 μm.

It should be noted that although the through holes 221 and the concave holes 222 are shown as circles in the second figure, in practical applications, the through holes 221 and the concave holes 222 are formed by exposing and developing the first flat layer 220. Therefore, The shape is not necessarily a perfect circle. The through hole 221 and the concave hole 222 of the present disclosure are not limited to the above-mentioned shapes, and the through hole 221 and the concave hole 222 may have any suitable shape.

As shown in FIG. 1, the first electrode layer 230 partially covers the upper surface of the first flat layer 220 and partially fills the through hole 221. In some embodiments, the first electrode layer 230 includes a plurality of pixel electrodes (not shown), each image The pixel electrode corresponds to one of the pixels of the display panel 100. The first alignment layer 240 covers a side of the first electrode layer 230 away from the first flat layer 220 and partially fills the through holes 221 and the recess holes 222.

It should be noted that, in order to clearly draw the layers, in Figure 1, the thickness of the first electrode layer 230 and the first alignment layer 240 are slightly enlarged. In practical applications, the ratio of the thickness of the first electrode layer 230/first alignment layer 240 to the first flat layer 220 is smaller than the thickness ratio shown in the figure. Therefore, when the first alignment layer 240 is formed, the first alignment layer 240 The side facing the first flat layer 220 corresponds to the concave hole 222 protruding, and the side of the first alignment layer 240 away from the first flat layer 220 corresponds to the concave hole 222 concave. If there are other layers located between the first alignment layer 240 and the first flat layer 220 in the frame area 102, they will also protrude corresponding to the concave holes 222 on the side facing the first flat layer 220, and move away from the first flat layer 220. One side of a flat layer 220 corresponds to the recessed hole 222. In some embodiments, the thickness of the first electrode layer 230 is substantially in the range of 750 Å to 1300 Å, and the thickness of the first alignment layer 240 is substantially 600 Å.

As shown in FIG. 1, the sealant 420 covers the concave hole 222 and has a plurality of protrusions 421 corresponding to the concave hole 222 on the side facing the first flat layer 220. The arrangement of the protrusion 421 can not only increase the surface area of the sealant 420 and the thin film transistor array substrate 200, but also disperse the external force in multiple directions. Therefore, when the side of the display panel 100 is impacted (for example, the display panel 100 is dropped) Time) is not easily separated from the thin film transistor array substrate 200, effectively improving the edge impact resistance of the display panel 100.

In some embodiments, as shown in FIG. 1, the concave hole 222 is located in the sealant 420 and projected on the first flat layer along a direction perpendicular to the first substrate 210 In the area of 220, in other words, all the concave holes 222 are covered by the sealant 420.

It should be noted that a specific type of display panel (such as a blue phase liquid crystal display panel) does not need to be provided with an alignment layer. Therefore, in some embodiments, the first alignment layer 240 may be omitted.

In some embodiments, as shown in FIG. 2, the border area 102 includes a lead-out area 103 and a non-lead-out area 104, where the non-lead-out area 104 refers to the part of the border area 102 outside the lead-out area 103. The portion of the first flat layer 220 in the outlet area 103 has a circuit (not shown) arranged therein for the display panel 100 to connect to the outside. The recessed hole 222 is located in the outlet area 103. The non-penetrating depth of the recessed hole 222 is designed so that it will not affect the lines arranged in the first flat layer 220. In the non-outgoing area 104, the first flat layer 220 may further include a plurality of first recesses 223. The sealant 420 covers the first concave portion 223 and has a plurality of protruding portions (not shown) corresponding to the first concave portion 223, thereby further improving the impact resistance of the edge of the display panel 100.

As mentioned above, the first recess 223 provided in the non-outgoing area 104 does not need to avoid the line, so its size can be larger than the concave hole 222 in the outgoing area 103. In some embodiments, the depth and maximum width of the first recess 223 are substantially equal to the depth D2 and the maximum width W2 of the concave hole 222, respectively. In some embodiments, the depth and the maximum width of the first recess 223 are larger than the depth D2 and the maximum width W2 of the concave hole 222, but do not penetrate the first flat layer 220. In some embodiments, the first recess 223 is a through hole, and its depth and maximum width are respectively equal to the depth D1 and the maximum width W1 of the through hole 221. The first recessed portion 223 of the present disclosure is not limited to the above-mentioned size, and there are Those with ordinary knowledge can appropriately adjust the size of the first recess 223 according to practical requirements.

Please refer to FIG. 3, which is a partial enlarged top view of the first flat layer 220 of the display panel 100 shown in FIG. 1. In some embodiments, the cavities 222 are arranged in a matrix. Specifically, the concave holes 222 are arranged in a plurality of straight rows 224, and the straight rows 224 are arranged along the first direction X1. The concave holes 222 of two adjacent straight rows 224 are aligned with each other in the second direction X2 perpendicular to the first direction X1. In other words, the concave holes 222 of two adjacent straight rows 224 have the same coordinates in the second direction X2.

In some embodiments, as shown in FIG. 3, the gap G between two adjacent concave holes 222 is substantially twice the maximum width W2 of the concave holes 222, in other words, two adjacent straight rows 224 are separated by a gap G . For example, when the maximum width W2 is 3 microns, the pitch G is 6 microns. If the designed pitch is too large and the density of the recessed holes 222 is too low, the arrangement of the recessed holes 222 is of limited help in improving the adhesion between the sealant 420 and the thin film transistor array substrate 200. On the contrary, if the designed spacing is too small, the adjacent recessed holes 222 may be connected during manufacturing, and the connected recessed holes 222 are less effective than the separated recessed holes 222.

In the figure, only a few recessed holes 222 are schematically drawn. In practical applications, the number of recessed holes 222 may be greater than the number depicted in the figure. In some embodiments, the width WS of the sealant 420 is substantially 500 microns (see Figure 1). When the maximum width W2 of the cavity 222 is 3 microns and the pitch G is 6 microns, in the second direction X2 , A horizontal row can contain dozens of recessed holes 222.

Please refer to FIG. 4, which is a partial enlarged top view of the first flat layer of the display panel according to another embodiment of the present disclosure. The difference between this embodiment and the embodiment shown in FIG. 3 lies in the arrangement of the recessed holes 222. Specifically, in this embodiment, the concave holes 222 of two adjacent straight rows 224 are misaligned with each other in the second direction X2. In other words, the concave holes 222 of two adjacent straight rows 224 have different positions in the second direction X2. coordinate. The adjacent concave holes 222 have a fixed interval G, so that three adjacent concave holes 222 are arranged in a regular triangle. Given the spacing G, the recessed holes 222 of this embodiment are arranged relatively tightly, and more recessed holes 222 can be arranged in a unit area of the frame area 102, thereby further improving the impact resistance of the edge of the display panel 100. The concave holes 222 of the present disclosure are not limited to the arrangement shown in FIG. 3 and FIG. 4, and the concave holes 222 can be arranged in any suitable manner.

Please refer back to Figure 1. The color filter substrate 300 includes a second substrate 310, a second flat layer 320, a second electrode layer 330, and a second alignment layer 340. The second flat layer 320 is disposed on the second substrate 310 and covers the color filter layer and the light shielding layer (not shown). The second flat layer 320 has a plurality of second recesses 321 located in the frame area 102. In some embodiments, the second planarization layer 320 is an overcoat layer. The second electrode layer 330 partially covers the lower surface of the second flat layer 320 facing the display medium layer 410, and the second alignment layer 340 covers the side of the second electrode layer 330 away from the second flat layer 320, and partially fills the second recessed portion Within 321.

As shown in Figure 1, the thickness of the second alignment layer 340 (and the second electrode layer 330) is significantly smaller than that of the second flat layer 320. Therefore, the side of the second alignment layer 340 facing the second flat layer 320 corresponds to the second recessed portion 321 protrusion, and the second The side of the direction layer 340 away from the second flat layer 320 corresponds to the second recessed portion 321 being concave. The sealant 420 covers the second recessed portion 321 and has a plurality of second raised portions 422 corresponding to the second recessed portion 321 on the side facing the second flat layer 320. With the above structural configuration, the impact resistance of the edge of the display panel 100 is further improved.

In some embodiments, the second electrode layer 330 includes a common electrode, and the common electrode forms an electric field with the pixel electrode of the first electrode layer 230 to control the arrangement of the liquid crystal in the display medium layer 410. In other embodiments, the common electrode is disposed on the thin film transistor array substrate 200. In this configuration, the color filter substrate 300 does not include the second electrode layer 330.

Since there is no circuit inside the second flat layer 320, the second recess 321 does not need to avoid the circuit, so it can have any size. The second concave portion 321 may be a through hole that penetrates the second flat layer 320 or a concave hole that does not penetrate the second flat layer 320. In some embodiments, the second recessed portion 321 and the recessed hole 222 of the first flat layer 220 are formed by using the same photomask, so that the depth D3 and the maximum width W3 of the second recessed portion 321 are substantially equal to the recessed hole 222, respectively. The depth D2 and the maximum width W2.

It should be noted that a person with ordinary knowledge in the related art can selectively dispose the second concave portion 321 on the second flat layer 320 according to the requirement of the display panel 100 for the edge impact resistance. For example, for the display panel 100 with a lower requirement on the edge impact resistance, the second recess 321 of the second flat layer 320 can be omitted to simplify the manufacturing process of the display panel 100.

Please refer to FIG. 5, which is a flowchart of a display panel manufacturing method 500 according to an embodiment of the present disclosure. Display panel manufacturing method 500 series For manufacturing the display panel 100, it includes steps S501 to S509. Hereinafter, the display panel manufacturing method 500 will be described in detail with reference to FIG. 6 to FIG. 10.

As shown in FIG. 6, in step S501, the first flat layer 220 is exposed through a photomask 900, wherein the photomask 900 has a plurality of first openings 901 (only one is representatively shown in FIG. 6) and is smaller than the first opening 901. A plurality of second openings 902 of an opening 901, the first opening 901 faces the display area 101, and the second opening 902 faces the frame area 102.

As mentioned above, during exposure, light will be irradiated onto the first flat layer 220 through the first opening 901 and the second opening 902, so that a part of the first flat layer 220 will undergo a chemical reaction. Specifically, in the direction perpendicular to the first substrate 210, the first flat layer 220 has a first exposure area (not shown) below the first opening 901 that is smaller than the first opening 901, and the second flat layer 320 is There is a second exposure area (not shown) below the second opening 902 that is smaller than the second opening 902, and the second exposure area is smaller than the first exposure area.

As shown in FIG. 7, in step S503, the first flat layer 220 is developed to form a through hole 221 corresponding to the first opening 901 and a concave hole 222 corresponding to the second opening 902 on the first flat layer 220. The maximum width W2 of the recessed hole 222 is smaller than the maximum width W1 of the through hole 221.

Specifically, in this step, a developer is added on the first flat layer 220, and the first exposed area and the second exposed area that undergo a chemical reaction through the exposure step S501 are dissolved in the developer to form the through holes 221 and Cavities 222. Since the size of the second opening 902 of the photomask 900 is smaller than that of the first opening 901, the area under the second opening 902 is not completely exposed, so a recessed hole 222 with a depth and a maximum width smaller than the through hole 221 is formed.

As shown in FIG. 8, in step S505, a first electrode layer 230 is formed on the first flat layer 220. The first electrode layer 230 partially covers the side of the first flat layer 220 away from the first substrate 210 and partially fills the through hole 221.

As shown in FIG. 9, in step S507, a first alignment layer 240 is formed on the first electrode layer 230. The first alignment layer 240 covers the side of the first electrode layer 230 away from the first substrate 210 and partially fills the through holes 221 and the recess holes 222. The side of the first alignment layer 240 facing the first flat layer 220 protrudes corresponding to the concave hole 222, and the side of the first alignment layer 240 away from the first flat layer 220 corresponds to the concave hole 222 inwardly. When the display panel 100 does not require an alignment layer, this step can be omitted.

As shown in FIG. 10, in step S509, a sealant 420 is covered on the concave hole 222, so that the sealant 420 forms a protrusion 421 corresponding to the concave hole 222. Specifically, the sealant 420 is coated on the first alignment layer 240 along the frame area 102 and fills the space of the first alignment layer 240 opposite to the recess 222 to form the protrusion 421.

Please refer back to Figure 1. In some embodiments, the same photomask 900 may be used to form the second recessed portion 321 on the second flat layer 320 of the color filter substrate 300. In these embodiments, the display panel manufacturing method 500 further includes: (1) exposing the second flat layer 320 through the photomask 900; (2) after the exposure, developing the second flat layer 320 for the second A second recessed portion 321 corresponding to the second opening 902 is formed on the flat layer 320; and (3) after the second electrode layer 330 and the second alignment layer 340 are formed, the color filter substrate 300 faces the thin-film electronic device with the second alignment layer 340 The crystal array substrate 200 is pressed on the sealant 420 in a manner such that the sealant 420 covers the second recessed portion 321 and forms a second raised portion 422 corresponding to the second recessed portion 321. In these embodiments, the depth D3 and the maximum width W3 of the second recessed portion 321 are substantially different It is equal to the depth D2 and the maximum width W2 of the concave hole 222, and the size of the second protrusion 422 is substantially equal to the protrusion 421.

It should be noted that in the embodiment described in the preceding paragraph, the first opening 901 is not illuminated during exposure, so as to avoid the formation of through holes located in the display area 101 on the second flat layer 320. In some embodiments, when the second flat layer 320 is exposed, the first opening 901 is blocked to prevent light from passing through the first opening 901 to illuminate the second flat layer 320.

In summary, the display panel of the present disclosure is provided with recessed holes in the flat layer (which can be the flat layer of the thin film transistor array substrate or the flat layer of the color filter substrate) in the frame area, and the sealant coated on the flat layer corresponds to the hole With protrusions, as a result, the surface area of the sealant and the thin film transistor array substrate/color filter substrate in contact is increased, and the protrusions can disperse external forces in multiple directions, making the edge of the display panel of the present disclosure more resistant to impact than The existing display panel has been significantly improved.

Although this disclosure has been disclosed in the above manner, it is not intended to limit the disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection of this disclosure The scope shall be subject to those defined in the attached patent scope.

100‧‧‧Display Panel

101‧‧‧Display area

102‧‧‧Frame area

200‧‧‧Thin Film Transistor Array Substrate

210‧‧‧First substrate

220‧‧‧First flat layer

221‧‧‧Through hole

222‧‧‧Concave hole

230‧‧‧First electrode layer

240‧‧‧First alignment layer

300‧‧‧Color filter substrate

310‧‧‧Second substrate

320‧‧‧Second flat layer

321‧‧‧Second depression

330‧‧‧Second electrode layer

340‧‧‧Second alignment layer

410‧‧‧Display medium layer

420‧‧‧Frame glue

421‧‧‧Protrusion

422‧‧‧Second Uplift

D1, D2, D3‧‧‧Depth

W1, W2, W3‧‧‧Maximum width

WS‧‧‧Width

Claims (13)

A display panel has a display area and a frame area, the frame area surrounds the display area, the display panel includes: a first substrate; a first flat layer disposed on the first substrate, and has a plurality of through Holes and a plurality of concave holes, wherein the through holes are located in the display area and penetrate the first flat layer, and the concave holes are located on a surface of the first flat layer away from the first substrate and located in the frame area Inside, a maximum width of the concave holes is smaller than a maximum width of the through holes; and a sealant covers the concave holes and has a plurality of protrusions corresponding to the concave holes. The display panel according to claim 1, wherein the frame area has an exit area, and the recessed holes are located in the exit area. The display panel according to claim 1, wherein the frame area has a non-outgoing area, the first flat layer further includes a plurality of first recesses, the first recesses are located in the non-outgoing area, and A maximum width of the first recessed portions is greater than the maximum width of the recessed holes, and the sealant has a plurality of first raised portions corresponding to the first recessed portions. The display panel according to claim 3, wherein the maximum width of the first recesses is substantially equal to the maximum width of the through holes. The display panel according to claim 1, wherein a distance between two adjacent ones of the concave holes is substantially twice the maximum width of the concave holes. The display panel according to claim 1, wherein a depth of the concave holes is less than or equal to half of a thickness of the first flat layer. The display panel according to claim 1, wherein a depth of the concave holes is in the range of 1 micrometer to 1.5 micrometers. The display panel according to claim 1, wherein the recessed holes are located in an area where the sealant is vertically projected on the first flat layer. The display panel according to claim 1, wherein some of the recessed holes are arranged in a plurality of straight rows, the straight rows are arranged along a first direction, and the recessed holes of two adjacent ones of the straight rows are arranged in a The second direction is misaligned with each other, and the second direction is substantially perpendicular to the first direction. The display panel according to claim 1, further comprising: a second substrate; and a second flat layer disposed on a side of the second substrate facing the first flat layer and having a plurality of second recesses, The second recessed portions are located in the frame area, and the sealant has a plurality of second raised portions corresponding to the second recessed portions. The display panel according to claim 10, wherein a maximum width of the second concave portions is substantially equal to the maximum width of the concave holes. A method for manufacturing a display panel is used to manufacture a display panel. The display panel includes a first substrate and a first flat layer on the first substrate, and has a display area and a frame area surrounding the display area, The display panel manufacturing method includes: exposing the first flat layer through a photomask, wherein the photomask has a plurality of first openings and a plurality of second openings, the first openings face the display area, the The second opening faces the frame area, and the second openings are smaller than the first openings; the first flat layer is developed to form a plurality of through holes and a plurality of first concave holes on the first flat layer , Wherein the through holes correspond to the first openings, the first recessed holes correspond to the second openings, a maximum width of the first recessed holes is smaller than a maximum width of the through holes; and A frame glue is covered on the first concave holes, so that the frame glue forms a plurality of first protrusions corresponding to the first concave holes. The display panel manufacturing method according to claim 12, wherein the display panel further includes a second substrate and a second flat layer on the second substrate, and the display panel manufacturing method further includes: Expose the second flat layer; The second flat layer is developed to form a plurality of second concave holes on the second flat layer, and the second concave holes correspond to the second openings; and the frame is covered on the second concave holes Glue so that the frame glue forms a plurality of second protrusions corresponding to the second concave holes.

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