TW202010084A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Description

Semiconductor package and its manufacturing method

The embodiment of the invention relates to a semiconductor package and a manufacturing method thereof.

Semiconductor devices and integrated circuits are usually fabricated on a single semiconductor wafer. The wafer die can be processed and packaged using other wafer-level semiconductor devices or die, and various technologies for wafer-level packaging have been developed.

An embodiment of the present invention provides a semiconductor package including a first chip package, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The first chip package includes a plurality of first semiconductor die and a first Insulation package. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulation encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are in electrical communication with each other by being connected to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die . The second insulating package encapsulates the first chip package, the second semiconductor die and the third semiconductor die.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, constructions, etc. are set forth below to simplify embodiments of the invention. Of course, these are only examples and are not intended to be limiting. Can imagine other components, values, operations, materials, constructions, etc. For example, forming the first feature on or on the second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include in which the first feature and the second feature are Embodiments in which additional features may be formed between the two features, so that the first feature and the second feature may not directly contact. In addition, embodiments of the present invention may reuse reference numbers and/or letters in various examples. This re-use is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, for example, "beneath", "below", "lower", "above", "upper" may be used in this article "Upper" and other spatial relativity terms to explain the relationship between one element or feature and another element(s) or feature illustrated in the figure. The term spatial relativity is intended to include different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may have other orientations (rotation 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly accordingly.

In addition, for ease of explanation, terms such as "first", "second", "third", and "fourth" may be used herein to describe similar or different elements or features shown in the figures, and may Used interchangeably depending on the order of existence or the context of the description.

The embodiments of the present invention may also include other features and processes. For example, a test structure may be included to illustrate the verification test of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may, for example, include test pads formed in the redistribution layer or on the substrate to enable testing of 3D packages or 3DICs, use of probes and/or probe cards, and the like. Verification tests can be performed on the intermediate structure and the final structure. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

1 to 6 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present invention. 11 to 14 are schematic cross-sectional views of various stages in a method of manufacturing a wafer package included in a semiconductor package according to some exemplary embodiments of the present invention. In an embodiment, the manufacturing method is part of a wafer-level packaging process. In FIGS. 1 to 6, for example, two semiconductor dies are shown to represent a plurality of semiconductor dies of a wafer, and a semiconductor package SP1 is shown to represent a semiconductor package obtained following, for example, the manufacturing method. In other embodiments, more than two semiconductor wafers or dies may be shown to represent multiple semiconductor wafers or dies of the wafer, and more than one semiconductor package may be shown to represent obtained following the manufacturing method Multiple semiconductor packages, the embodiments of the present invention are not limited to this. In FIGS. 11 to 14, for example, two semiconductor dies are shown to represent a plurality of dies included in one chip package CP1. However, the embodiments of the present invention are not limited to this, and more than two semiconductor dies may be shown to represent multiple dies included in one chip package CP1.

Referring to FIG. 1, in some embodiments, a carrier 110 is provided. In one embodiment, the carrier 110 may be a glass carrier or any carrier suitable for carrying semiconductor wafers or reconstituted wafers for manufacturing methods of semiconductor packages. In an alternative embodiment, the carrier 110 may be a reclaim wafer or a reconstructed wafer used in a manufacturing method of a semiconductor package. For example, since the material of the carrier 110 is a Si substrate, the carrier 110 can serve as a heat dissipating element of the semiconductor package SP1. In such an embodiment, the carrier 110 can also be used for warpage control.

In some alternative embodiments where the carrier 110 is removed after manufacturing the semiconductor package, the carrier 110 may also be coated with a release layer (not shown). For example, a peeling layer is provided on the carrier 110, and the material of the peeling layer may be any suitable for bonding and peeling the carrier 110 to the upper layer (eg, buffer layer) or any wafer provided on the carrier 110 material. In some embodiments, the release layer may include a release layer (eg, a light-to-heat conversion (LTHC)) layer or an adhesive layer (eg, an ultraviolet curable adhesive or a heat curable adhesive layer).

Continuing on the basis of FIG. 1, in some embodiments, a redistribution circuit structure 120 is formed on the carrier 110. For example, forming the redistribution circuit structure 120 includes alternately sequentially forming one or more polymer dielectric layers 122 and one or more metallization layers 124. In some embodiments, as shown in FIG. 1, the redistribution circuit structure 120 includes two polymer dielectric layers 122 and a metallization layer 124 sandwiched between the two polymer dielectric layers 122; However, the embodiments of the present invention are not limited to this. The number of metallization layers and polymer dielectric layers included in the redistribution circuit structure 120 is not limited to this. For example, the number of metallization layers and polymer dielectric layers can be one or more than one. Due to the configuration of the polymer dielectric layer 122 and the metallization layer 124, a routing function is provided for the semiconductor package SP1. In other words, the redistribution circuit structure 120 may be referred to as the backside redistribution layer of the semiconductor die 200 and the semiconductor die 300, for example.

In some embodiments, as shown in FIG. 1, the metallization layer 124 is disposed above the carrier 110 and sandwiched between the polymer dielectric layers 122, wherein some portions of the top surface of the metallization layer 124 are polymerized The topmost layer of the dielectric layer 122 is exposed and the bottom surface of the metallization layer 124 is covered by the bottommost layer of the polymer dielectric layer 122. In some embodiments, the material of the polymer dielectric layer 122 may include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole, PBO) or any other suitable polymer-based dielectric material, and the polymer dielectric layer 122 may be formed by deposition. In some embodiments, the material of the metallization layer 124 may include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, and the metallization layer 124 may be formed by electroplating or deposition. The embodiments of the present invention are not limited to this.

In some embodiments, as shown in FIG. 1, a plurality of through holes 130 are formed on the redistribution circuit structure 120. For example, the through holes 130 are physically connected to the portions of the top surface of the metallization layer 124 exposed by the topmost layer of the polymer dielectric layer 122. In other words, the through hole 130 is electrically connected to the redistribution circuit structure 120. In some embodiments, the perforation 130 may be an integrated fan-out (InFO) perforation. For simplicity, for illustrative purposes, only two perforations 130 are presented in FIG. 1, however, it should be noted that more than two perforations may be formed; embodiments of the present invention are not limited to this. The number of perforations 130 can be selected based on needs.

In some embodiments, the through holes 130 are formed by photolithography, plating, photoresist stripping process or any other suitable method. In one embodiment, the perforation 130 may be formed by forming a mask pattern (not shown) covering the redistribution wiring structure 120, the mask pattern having an opening to expose the most of the polymer dielectric layer 122 The top surface of the exposed metallization layer 124 of the top layer; the metal material filling the opening is formed by electroplating or deposition to form the through hole 130; and then the mask pattern is removed. In one embodiment, the material of the perforation 130 may include metal materials such as copper or copper alloy. However, the embodiments of the present invention are not limited to this.

In some embodiments, at least one semiconductor die is provided. As shown in FIG. 1, in a specific embodiment, the semiconductor die 200 and the semiconductor die 300 are provided and arranged on the redistribution circuit structure 120. For example, the semiconductor die 200 and the semiconductor die 300 are picked up and placed on the redistribution circuit structure 120, and the semiconductor die 200 and the semiconductor die 300 are bonded or glued to each other through the connection film DA1 and the connection film DA2 The wiring structure 120 is redistributed.

In some embodiments, the connection films DA1 and DA2 may be die attach films, adhesive pastes, and the like. In some embodiments, as shown in FIG. 1, in the direction Z, the semiconductor die 200 and/or the semiconductor die 300 may have a thickness smaller than the height of the through hole 130. However, the embodiments of the present invention are not limited to this. In alternative embodiments, in the direction Z, the thickness of the semiconductor die 200 and/or the semiconductor die 300 may be greater than or substantially equal to the height of the through hole 130. As shown in FIG. 1, the semiconductor die 200 and the semiconductor die 300 may be picked and placed on the redistribution wiring structure 120 after the formation of the through hole 130. However, the embodiments of the present invention are not limited to this. In an alternative embodiment, the semiconductor die 200 and the semiconductor die 300 may be picked and placed on the redistribution structure 120 before forming the through-hole 130. The cross-sectional shape of the perforation 130 may be selected based on requirements, and the cross-sectional shape of the perforation 130 is not limited to the embodiments of the embodiments of the present invention.

For example, as shown in FIG. 1, the semiconductor die 200 includes a semiconductor substrate 210 having an active surface 210a, an interconnect structure 220 formed on the active surface 210a, and a connection via electrically connected to the interconnect structure 220 230.

In some embodiments, the semiconductor substrate 210 may be a silicon substrate including active elements (eg, transistors, etc.) and/or passive elements (eg, resistors, capacitors, inductors) formed in the silicon substrate Etc.). The embodiments of the present invention are not limited to this.

In some embodiments, the interconnect structure 220 includes one or more interlayer dielectric layers 222 and one or more patterned conductive layers 224 that are alternately stacked. In some embodiments, the patterned conductive layer 224 is sandwiched between the interlayer dielectric layers 222, wherein some portions of the top surface of the topmost layer of the patterned conductive layer 224 are exposed and solid by the topmost layer of the interlayer dielectric layer 222 It is connected to the connection via 230, and some of the bottommost part of the patterned conductive layer 224 is exposed by the bottommost layer of the interlayer dielectric layer 222 and is electrically connected to the active devices and/or passive devices formed in the semiconductor substrate 210 (not show). As shown in FIG. 1, the bottommost layer of the interlayer dielectric layer 222 is located on the active surface 210 a of the semiconductor substrate 210, and the topmost layer of the interlayer dielectric layer 222 at least partially contacts the connection via 230. The number of the interlayer dielectric layer 222 and the patterned conductive layer 224 can be selected based on requirements, and is not limited in the embodiment of the present invention.

In one embodiment, the interlayer dielectric layer 222 can be polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), boron Borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof, etc., the interlayer dielectric layer 222 may utilize a lithography process and/or an etching process (Etching process) and patterning. In some embodiments, suitable methods such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. To form the interlayer dielectric layer 222. In one embodiment, the patterned conductive layer 224 may be made of a conductive material (for example, copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition, and the patterned conductive layer 224 may utilize lithography Process and etching process to pattern. In some embodiments, the patterned conductive layer 224 may be a patterned copper layer or other suitable patterned metal layer. Throughout this description, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities or containing small amounts such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, Copper alloys of elements such as platinum, magnesium, aluminum or zirconium.

In some embodiments, the connection via 230 includes one or more connection vias 232 and one or more connection vias 234, wherein the height of the connection via 232 is greater than the height of the connection via 234 as measured in the direction Z . As shown in FIG. 1, although only three connection vias 232 and one connection via 234 are presented in FIG. 1 for illustrative purposes, it should be noted that the connection vias 232 and The number of connecting through holes 234; the embodiment of the present invention is not limited to this. In some embodiments, the connection via 230 includes a plurality of connection vias 232, excluding the connection via 234 (see the semiconductor die 200a depicted in FIGS. 7-9). In one embodiment, the connection via 232 and the connection via 234 may be formed in different steps, wherein the connection via 232 may be formed before the connection via 234 is formed, and vice versa. As shown in FIG. 1, the connection via 232 and the connection via 234 are electrically connected to the interconnect structure 220.

For example, as shown in FIG. 1, the semiconductor die 300 includes a semiconductor substrate 310 having an active surface 310a, an interconnect structure 320 formed on the active surface 310a, and a connection via electrically connected to the interconnect structure 320 330.

In some embodiments, the semiconductor substrate 310 may be a silicon substrate including active elements (eg, transistors, etc.) and/or passive elements (eg, resistors, capacitors, inductors) formed in the silicon substrate Etc.). The embodiments of the present invention are not limited to this.

In some embodiments, the interconnect structure 320 includes one or more interlayer dielectric layers 322 and one or more patterned conductive layers 324 that are alternately stacked. In some embodiments, the patterned conductive layer 324 is sandwiched between the interlayer dielectric layers 322, wherein some portions of the top surface of the topmost layer of the patterned conductive layer 324 are exposed and solid by the topmost layer of the interlayer dielectric layer 322 Is connected to the connection via 330, and some of the bottommost part of the patterned conductive layer 324 is exposed by the bottommost layer of the interlayer dielectric layer 322 and is electrically connected to the active device and/or the passive device formed in the semiconductor substrate 310 (not show). As shown in FIG. 1, the bottommost layer of the interlayer dielectric layer 322 is located on the active surface 310 a of the semiconductor substrate 310, and the topmost layer of the interlayer dielectric layer 322 at least partially contacts the connection via 330. The number of the interlayer dielectric layer 322 and the patterned conductive layer 324 can be selected based on requirements, and is not limited in the embodiment of the present invention.

In one embodiment, the interlayer dielectric layer 322 may be polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, or a combination thereof, etc. The electrical layer 322 can be patterned using a lithography process and/or an etching process. In some embodiments, the interlayer dielectric layer 322 may be formed by suitable fabrication techniques such as spin coating, CVD, PECVD, and the like. In one embodiment, the patterned conductive layer 324 may be made of a conductive material (eg, copper, copper alloy, aluminum, aluminum alloy, or a combination thereof) formed by electroplating or deposition, and the patterned conductive layer 324 may utilize lithography Process and etching process to pattern. In some embodiments, the patterned conductive layer 324 may be a patterned copper layer or other suitable patterned metal layer.

In some embodiments, the connection via 330 includes one or more connection vias 332 and one or more connection vias 334, wherein the height of the connection via 332 is greater than the height of the connection via 334 as measured in the direction Z . As shown in FIG. 1, although only three connection vias 332 and one connection via 334 are presented in FIG. 1 for illustrative purposes, it should be noted that the connection vias 332 and may be selected or specified based on requirements and design layout The number of connecting through holes 334; the embodiment of the present invention is not limited to this. In some embodiments, the connection via 330 includes a plurality of connection vias 332, excluding the connection via 334 (see the semiconductor die 300a depicted in FIGS. 7-9). In one embodiment, the connection via 332 and the connection via 334 may be formed in different steps, wherein the connection via 332 may be formed before the connection via 334 is formed, and vice versa. As shown in FIG. 1, the connection via 332 and the connection via 334 are electrically connected to the interconnect structure 320.

In one embodiment, the semiconductor die 200 is the same as the semiconductor die 300. In an alternative embodiment, the semiconductor die 200 is different from the semiconductor die 300. The embodiments of the present invention are not limited to this.

Referring to FIG. 2, in some embodiments, a chip package CP1 is provided and arranged on a carrier 110. For example, the formation of the chip package CP1 shown in FIG. 2 can be illustrated in FIGS. 11 to 14, but the embodiments of the present invention are not limited thereto. Referring to FIG. 11, in some embodiments, a semiconductor substrate 650 on which an interconnect structure 660 is provided is provided. In one embodiment, the material of the semiconductor substrate 650 may include a silicon substrate including active elements (eg, transistors and/or eg n-type metal oxide semiconductor (n-type) formed in the silicon substrate metal oxide semiconductor (NMOS) and/or memory of a P-type metal oxide semiconductor (PMOS) device) and/or passive components (eg, resistors, capacitors, inductors, etc.). In an alternative embodiment, the semiconductor substrate 650 may be a bulk silicon substrate, such as a bulk single crystal silicon substrate, a doped silicon substrate, an undoped silicon substrate, or silicon on insulator , SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant or a combination thereof. The embodiments of the present invention are not limited to this.

In one embodiment, an interconnect structure 660 is formed on the active surface 650a of the semiconductor substrate 650. In some embodiments, the interconnect structure 660 may include one or more interlayer dielectric layers 662 and one or more patterned conductive layers 664 that are alternately stacked. For example, the interlayer dielectric layer 662 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and the interlayer dielectric layer 662 may be formed by deposition or the like . For example, the patterned conductive layer 664 may be a patterned copper layer or other suitable patterned metal layer, and the patterned conductive layer 664 may be formed by electroplating or deposition. However, the embodiments of the present invention are not limited to this. In some embodiments, the patterned conductive pattern 664 may be formed by a dual-damascene method. As shown in FIG. 11, for example, the top surface of the topmost layer of the patterned conductive layer 664 is exposed in a accessible manner through the topmost layer of the interlayer dielectric layer 662. In addition, there is a high degree of coplanarity between the top surface of the topmost layer of the patterned conductive layer 664 and the top surface of the topmost layer of the interlayer dielectric layer 662. The number of layers of the interlayer dielectric layer 662 and the patterned conductive layer 664 may be less than the number of layers shown in FIG. 11 or more than the number of layers shown in FIG. 11, and may be specified based on requirements and/or design layout; The embodiments of the present invention are not particularly limited thereto.

Continuing based on FIG. 11, in some embodiments, the semiconductor die 400 a and the semiconductor die 400 b are picked and placed on the interconnect structure 660. In some embodiments, the semiconductor die 400a includes: a semiconductor substrate 410a having an active surface 410at and a back surface 410ab opposite to the active surface 410at; a plurality of conductive pads 420a formed on the active surface 410at; a passivation layer 430a, Disposed on the conductive pad 420a and partially exposed the conductive pad 420a; rear passivation layer 440a, disposed on the passivation layer 430a and partially exposed the conductive pad 420a; connection via 450a, disposed on the conductive pad 420a And a protective layer 460a, covering the rear passivation layer 440a and surrounding the sidewalls of the connection via 450a. In other words, the conductive pads 420a distributed on the active surface 410at of the semiconductor substrate 410a are partially exposed by the contact opening of the passivation layer 430a and the contact opening of the rear passivation layer 440a to connect to the connection via 450a.

In some embodiments, the material of the semiconductor substrate 410a may include a silicon substrate including active elements (eg, transistors and/or memory such as NMOS and/or PMOS devices, etc.) formed in the silicon substrate ) And/or passive components (eg, resistors, capacitors, inductors, etc.). In alternative embodiments, the semiconductor substrate 410a may be a bulk silicon substrate, such as a bulk single crystal silicon substrate, a doped silicon substrate, an undoped silicon substrate, or an SOI substrate, wherein the doping of the doped silicon substrate The agent may be an N-type dopant, a P-type dopant, or a combination thereof. The embodiments of the present invention are not limited to this.

In some embodiments, the conductive pad 420a may be an aluminum pad or other suitable metal pad. For example, the connection via 450a may be a copper pillar, a copper alloy pillar, or other suitable metal pillar. In some embodiments, the passivation layer 430a, the rear passivation layer 440a, and/or the protective layer 460a may be a PBO layer, a polyimide (PI) layer, or other suitable polymers. In some embodiments, the passivation layer 430a, the rear passivation layer 440a, and/or the protective layer 460a may be made of inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. In one embodiment, the material of the passivation layer 430a, the material of the rear passivation layer 440a, and/or the material of the protective layer 460a may be the same. In alternative embodiments, the material of the passivation layer 430a, the material of the rear passivation layer 440a, and/or the material of the protective layer 460a may be different from each other, and the embodiments of the present invention are not limited thereto.

In some embodiments, the semiconductor die 400b includes: a semiconductor substrate 410b having an active surface 410bt and a back surface 410bb opposite to the active surface 410bt; a plurality of conductive pads 420b formed on the active surface 410bt; a passivation layer 430b, The conductive pad 420b is disposed and partially exposes the conductive pad 420b; the rear passivation layer 440b is disposed on the passivation layer 430b and partially exposes the conductive pad 420b; the connection via 450b is disposed on the conductive pad 420b ; And a protective layer 460b, covering the rear passivation layer [440b and surrounding the sidewalls of the connection via 450b. In other words, the conductive pads 420b distributed on the active surface 410bt of the semiconductor substrate 410b are partially exposed by the contact opening of the passivation layer 430b and the contact opening of the rear passivation layer 440b to be connected to the connection via 450b. For example, the materials of the semiconductor substrate 410b, the conductive pad 420b, the passivation layer 430b, the rear passivation layer 440b, the connection via 450b, and the protective layer 460b can be the same as the semiconductor substrate 410a, the conductive pad 420a, the passivation layer 430a, the rear passivation layer The materials of 440a, the connecting via 450a and the protective layer 460a are the same or similar, so they will not be repeated in this article.

Referring to FIGS. 11 and 12 together, in some embodiments, the semiconductor die 400a and the semiconductor die 400b are bonded to the interconnection provided on the semiconductor substrate 650 by hybrid bonding (via a hybrid bonding interface IF) Structure 660. As shown in FIG. 12, for example, a part of the interconnect structure 660 is not covered by the semiconductor die 400a and the semiconductor die 400b. For example, the hybrid bonding process may include a hydrophilic fusion bonding process (hydrophilic fusion bonding process) or a hydrophobic fusion bonding process (hydrophobic fusion bonding process). In one embodiment, a hydrophilic fusion bonding process is performed in which the workable bonding temperature is approximately in the range of 100°C to 300°C and the workable bonding pressure is approximately greater than 1 to 5 MPa (MPa) ; However, the embodiments of the present invention are not particularly limited thereto. Referring to FIG. 12, in some embodiments, an insulating encapsulant 630 is formed over a semiconductor substrate 650, wherein the semiconductor die 400a and the semiconductor die 400b are encapsulated in the insulating encapsulant 630, and the semiconductor die 400a The interconnect structure 660 exposed at 400b is covered by the insulating encapsulant 630. In some embodiments, as shown in FIG. 12, the sidewalls of the semiconductor die 400 a and the semiconductor die 400 b are surrounded and covered by the insulating encapsulation 630. In some embodiments, the insulating encapsulant 630 may be an oxide (eg, silicon oxide, etc.). In some embodiments, the insulating encapsulation 630 may be formed by deposition.

Continuing based on FIG. 12, in some embodiments, a plurality of through holes 640 are formed in the insulating encapsulation 630. In one embodiment, the material of the through hole 640 may include a metal material such as copper or copper alloy. However, the embodiments of the present invention are not limited to this. In some embodiments, the forming the through hole 640 may include patterning the insulating encapsulation 630 to form a through opening exposing the patterned conductive layer 664 and filling the through opening with a conductive material to form a through insulating encapsulation The body 630 is electrically connected to the through hole 640 of the interconnect structure 660. For example, the patterning process may include a laser drilling process or a lithography process and an etching process. The number and size of the perforations 640 are not limited to FIG. 12, and can be selected based on requirements.

For example, the interconnect structure 660 is located between the semiconductor substrate 650 and the semiconductor dies 400a and 400b, between the semiconductor substrate 650 and the insulating encapsulant 630, and between the semiconductor substrate 650 and the through hole 640, in which the conductive layer 664 is patterned The exposed top layer supports the connection through hole 450a, the connection through hole 450b, and the through hole 640, respectively. The semiconductor substrate 650 is coupled to the semiconductor die 400a and the semiconductor die 400b through the topmost layer of the patterned conductive layer 664, the connection via 450a and the connection via 450b, and the interconnection structure 660 is electrically connected to the semiconductor die 400a and the semiconductor die Grain 400b and perforation 640.

In one embodiment, the insulating encapsulant 630 may overmold the semiconductor die 400a, 400b and may need to be planarized before forming the via 640 to expose the backside surface 410ab of the semiconductor die 400a and the semiconductor crystal The back side surface 410bb of the connection through hole 450b of the pellet 400b. In yet another embodiment, a planarization step may be performed on the insulating encapsulant 630, the semiconductor die 400a, 400b, and the through hole 640, so that the surfaces of the insulating encapsulant 630, the semiconductor die 400a, 400b, and the through hole 640 are mutually shared Thus, high coplanarity is obtained between the insulating encapsulant 630, the semiconductor die 400a, 400b and the through hole 640. In some embodiments, the planarization step may be a polishing process or a chemical mechanical polishing (CMP) process. After the planarization step, a cleaning step may be optionally performed to, for example, clean and remove residues generated from the planarization step. However, the embodiments of the present invention are not limited to this, and the planarization step may be performed by any other suitable method. The embodiments of the present invention are not limited to this.

Referring to FIG. 13, in some embodiments, a redistribution circuit structure 620 is formed on an insulating encapsulant 630, and the redistribution circuit structure 620 includes a polymer dielectric layer 622 and a metallization layer 624; however, embodiments of the present invention Not limited to this. The number of metallization layers 624 and polymer dielectric layers 622 included in the redistribution circuit structure 620 is not limited to this. For example, the number of metallization layers 624 and polymer dielectric layers 622 may be one or more than one. For example, the material and formation of the polymer dielectric layer 622 may be the same as or similar to the material and formation of the polymer dielectric layer 122 described in FIG. 1, and the material and formation of the metallization layer 624 may be the same as that shown in FIG. The materials and formation of the metallization layer 124 are the same or similar, so they will not be described in detail herein.

Continuing based on FIG. 13, in some embodiments, contact pads 670 are formed on the exposed portions of the metallization layer 624 of the redistribution circuit structure 620. The contact pad 670 is connected to the exposed portion of the metallization layer 624 of the redistribution circuit structure 620; and therefore, the contact pad 670 is electrically connected to the semiconductor die through the redistribution circuit structure 620, the through hole 640, and the interconnect structure 660 400a and semiconductor die 400b. For example, the material of the contact pad 670 may include aluminum or aluminum alloy. In some embodiments, a protective layer 680 is formed on the redistribution circuit structure 620 and on the contact pad 670, wherein the protective layer 680 includes a plurality of openings to expose the contact pad 670.

Referring to FIG. 14, in some embodiments, a connection via 690 is formed on the protective layer 680 and the connection via 690 is physically connected to the contact pad 670. In other words, the connection via 690 is electrically connected to the semiconductor die 400a and the semiconductor die 400b through the contact pad 670, the redistribution circuit structure 620, the through hole 640, and the interconnect structure 660. In some embodiments, a dicing (or singulation) process is sequentially performed to divide the wafer into individual and separated chip packages CP1, the wafer having a plurality of chips connected between the wafers Package CP1. In one embodiment, the cutting process is a wafer cutting process including mechanical blade sawing or laser cutting. The embodiments of the present invention are not limited to this. At this point, the manufacturing of the chip package CP1 is completed. In some embodiments, during the dicing process, the holding device (not shown) is adapted to fix the wafer package CP1 before dicing to prevent damage caused by the dicing (or singulation) process. For example, the holding device may be an adhesive tape, carrier film or suction pad.

Referring to FIG. 2, in some embodiments, the chip package CP1 is bonded to the semiconductor die 200 and the semiconductor die 300 by flip chip bonding. For example, the chip package CP1 is physically connected to the semiconductor die 200 and the semiconductor die 300, wherein the connection via 690 of the chip package CP1 is physically connected to the connection via 234 of the semiconductor die 200 and the connection via of the semiconductor die 300, respectively孔334. In some embodiments, as shown in FIG. 2, the chip package CP1 is in the stacking direction (eg, direction Z) of the redistribution circuit structure 120 and the semiconductor die 200 (or, the redistribution circuit structure 120 and the semiconductor die 300 Stack direction) overlaps the semiconductor die 200 and the semiconductor die 300, and the vertical projection on the redistribution wiring structure 120 extends from the semiconductor die 200 to the semiconductor die 300. It should be noted that the semiconductor die 200 and the semiconductor die 300 do not overlap each other in the stacking direction (for example, the direction Z) but are arranged next to each other in the lateral direction. The semiconductor die 200 and the semiconductor die 300 are electrically communicated with each other through the chip package CP1. Due to the configuration, a short electrical path is realized between the semiconductor die 200a, the semiconductor die 300a, and the chip package CP1 (involving other semiconductor die 400a, 400b), thereby causing signal loss ( signal loss).

Referring to FIG. 3, in some embodiments, an insulating encapsulant 140 is formed on the carrier 110 (eg, on the redistribution wiring structure 120) to encapsulate the semiconductor die 200, the semiconductor die 300, the chip package CP1, and the through-hole 130. In other words, the semiconductor die 200, the semiconductor die 300, the chip package CP1, and the through hole 130 are covered by the insulating encapsulant 140 and embedded in the insulating encapsulant 140. In some embodiments, the insulating encapsulant 140 is a molding compound formed by a molding process, and the material of the insulating encapsulant 140 may include epoxy resin or other suitable resins. For example, the insulating encapsulant 140 may be an epoxy resin containing chemical filler.

Referring to FIGS. 3 and 4, in some embodiments, the insulating package 140 and the chip package CP1 are planarized until the surface of the chip package CP1 (for example, the bottom surface 650 b of the semiconductor substrate 650) and the connection via 232 are exposed The top surface 232t, the top surface 234t of the connection through hole 234, the top surface 332t of the connection through hole 332, the top surface 334t of the connection through hole 334 and the top surface 130t of the through hole 130. After planarizing the insulating envelope 140, an insulating envelope 140' is formed on the carrier 110 (e.g., on the redistribution wiring structure 120). During the planarization process of the insulating encapsulant 140 (shown in FIG. 4 ), the connection vias 232 and 234 of the semiconductor die 200 and/or the connection vias 332 and 332 of the semiconductor die 300 may also be used The connection via 334 is planarized. In some embodiments, as shown in FIG. 4, during the planarization process of the insulating encapsulant 140 and the chip package CP1, some portions of the through-hole 130 may also be planarized. For example, the insulating encapsulant 140' can be formed by mechanical grinding or CMP. After the planarization process, a cleaning step may be optionally performed to, for example, clean and remove residues generated from the planarization step. However, the embodiments of the present invention are not limited to this, and the planarization step may be performed by any other suitable method.

Referring to FIG. 5, in some embodiments, after forming the insulating encapsulant 140', a redistribution circuit structure 150 is formed on the planarized insulating encapsulant 140'. In some embodiments, on the top surface 140t of the insulating encapsulant 140', the bottom surface 650b of the semiconductor substrate 650, the top surface 232t of the connection via 232, the top surface 332t of the connection via 332, and the top surface 130t of the through hole 130 The upper wiring structure 150 is formed. That is, a weight is formed on the insulating encapsulant 140 ′ along the stacking direction of the redistribution circuit structure 120 and the semiconductor die 200 (for example, direction Z) (or, the stacking direction of the redistribution circuit structure 120 and the semiconductor die 300 ).布线结构150。 150 line structure. In some embodiments, the redistribution circuit structure 150 is made to be electrically connected to one or more connecting members underneath. Here, the aforementioned connecting member may be the connecting through hole 232 of the semiconductor die 200, the connecting through hole 332 of the semiconductor die 300, and the through hole 130 embedded in the insulating package 140'. In other words, the redistribution circuit structure 150 is electrically connected to the connection via 232 of the semiconductor die 200, the connection via 332 of the semiconductor die 300, and the through hole 130.

With continued reference to FIG. 5, in some embodiments, the redistribution wiring structure 150 includes a plurality of polymer dielectric layers 152 and a plurality of metallization layers 154 that are alternately stacked, and the metallization layer 154 is electrically connected to the connection of the semiconductor die 200 The through hole 232, the connection through hole 332 of the semiconductor die 300 and the through hole 130 embedded in the insulating encapsulant 140 ′. As shown in FIG. 5, in some embodiments, the top surface 232t of the connection through hole 232, the top surface 332t of the connection through hole 332, and the top surface 130t of the through hole 130 contact the redistribution circuit structure 150. In such an embodiment, the top surface 232t of the connection via 232, the top surface 332t of the connection via 332, and the top surface 130t of the through hole 130 contact the lowest layer of the metallization layer 154. In some embodiments, the top surface 232t of the connection via 232, the top surface 332t of the connection via 332, and the top surface 130t of the through hole 130 are partially covered by the bottommost layer of the polymer dielectric layer 152.

In some embodiments, the topmost layer of the metallization layer 154 may include multiple pads. In such an embodiment, the pad may include a plurality of under-ball metallurgy (UBM) patterns 154a for ball mounting.

However, the embodiments of the present invention are not limited to this. In an alternative embodiment, the topmost metallization layer 154 of the metallization layers 154 may include a plurality of UBM patterns 154a for ball mounting and/or a plurality of connection pads 154b for mounting other semiconductor elements (see FIG. 7) And according to the embodiment of the present invention, the number of metal patterns 154a under the ball and the number of connection pads 154b are not limited.

Referring to FIG. 6, in some embodiments, after forming the redistribution wiring structure 150, a plurality of conductive elements 160 are placed on the under-ball metal pattern 154 a. In some embodiments, the conductive element 160 may be placed on the under-ball metal pattern 154a through a ball bumping process and/or a reflow process or other suitable forming methods. In some embodiments, the conductive element 160 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps , Bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. For example, the material of the conductive element 160 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or a combination thereof. In one embodiment, for example, the material of the conductive element 160 may be solder-free.

In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 200 through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 300 through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the chip package CP1 through the redistribution circuit structure 150, the semiconductor die 200 and/or the semiconductor die 300. In some embodiments, some of the conductive elements 160 are electrically connected to the through holes 130 through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the redistribution circuit structure 120 through the redistribution circuit structure 150 and the through hole 130. In some embodiments, some of the conductive elements 160 may be electrically floated or electrically grounded, and the embodiments of the present invention are not limited thereto.

With continued reference to FIG. 6, a dicing process is sequentially performed to divide the plurality of semiconductor packages SP1 connected in the wafer into individual and separated semiconductor packages SP1. In one embodiment, the cutting process is a wafer cutting process including mechanical blade sawing or laser dicing. At this point, the manufacturing of the semiconductor package SP1 is completed. During the dicing process, a holding device (not shown) is used to fix the wafers with a plurality of semiconductor packages SP1 before dicing the wafers to prevent damage caused by sequential processes or transportation. For example, the holding device may be an adhesive tape, a carrier film, or a suction pad. In yet another embodiment, after the dicing process, the carrier 110 may be peeled from the semiconductor package SP1, wherein the redistribution circuit structure 120 is exposed; the embodiments of the present invention are not limited thereto.

7 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 6 and 7 together, the semiconductor package SP1 depicted in FIG. 6 is similar to the semiconductor package SP2 depicted in FIG. 7; thus, components that are similar or substantially the same as the above components will use the same reference number, In addition, some details or descriptions of the same elements and their relationships (for example, relative positioning configuration and electrical connection) will not be repeated here.

6 and 7 together, the difference is that for the semiconductor package SP2 shown in FIG. 1, the chip package CP1 is disposed on the redistribution circuit structure 150 and is located beside the conductive element 160, in which the semiconductor die 200 and the semiconductor die 300 Replaced by semiconductor die 200a and semiconductor die 300a. For example, as shown in FIG. 7, the difference between the semiconductor die 200 and the semiconductor die 200a is that the semiconductor die 200a includes a connection via 232 connecting to the via 230, and the connection via 230 does not include a connection via The hole 234; and the difference between the semiconductor die 300 and the semiconductor die 300a is that the semiconductor die 300a includes a connection via 332 connecting the via 330, the connection via 330 does not include the connection via 334. As shown in FIG. 7, the chip package CP1 is electrically connected to the semiconductor die 200 a and the semiconductor die 300 a through the redistribution wiring structure 150, wherein the chip package CP1 is electrically communicated with the semiconductor die 200 a and the semiconductor die 300 a.

In some embodiments, as shown in FIG. 7, the topmost metallization layer 154 of the metallization layer 154 includes a plurality of UBM patterns 154a for ball mounting and a plurality of connection pads 154b for mounting other semiconductor elements And, according to embodiments of the present invention, the number of metal patterns 154a under the ball and the number of connection pads 154b are not limited. In some embodiments, the chip package CP1 is bonded to the connection pad 154b, and some of the conductive elements 160 are electrically connected to the chip package CP1 through the redistribution circuit structure 150 and the connection pad 154b.

As shown in FIG. 7, the chip package CP1 is aligned with the stacking direction of the redistribution circuit structure 120 and the semiconductor die 200 a (for example, direction Z) (or, the stacking direction of the redistribution circuit structure 120 and the semiconductor die 300 a ). The semiconductor die 200a and the semiconductor die 300a overlap, and the vertical projection on the redistribution wiring structure 120 extends from the semiconductor die 200a to the semiconductor die 300a. In some embodiments, the height of the chip package CP1 is less than the height of the conductive element 160 as measured in the direction Z. Due to the configuration, a short electrical path is realized between the semiconductor die 200a, the semiconductor die 300a, and the chip package CP1 (involving other semiconductor die 400a, 400b), thereby reducing its signal loss.

8 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 6 and FIG. 8 together, the semiconductor package SP1 shown in FIG. 6 is similar to the semiconductor package SP3 shown in FIG. 8; thus, components similar to or substantially the same as the above components will use the same reference number, In addition, some details or descriptions of the same elements and their relationships (for example, relative positioning configuration and electrical connection) will not be repeated here.

Referring to FIGS. 6 and 8 together, the difference is that the semiconductor package SP3 shown in FIG. 8 further includes additional elements (for example, a dielectric layer PM1, a plurality of vias 132, a plurality of vias 134, and an insulating encapsulant 142), wherein the chip package CP1 is disposed between the redistribution circuit structure 150 and the insulating package 140', and the semiconductor die 200 and the semiconductor die 300 are replaced by the semiconductor die 200a and the semiconductor die 300a, respectively. For example, the difference between the semiconductor die 200 and the semiconductor die 200a is that the semiconductor die 200a includes a connection via 232 connecting to the via 230, and the connection via 230 does not include the connection via 234; and the semiconductor die The difference between 300 and the semiconductor die 300a is that the semiconductor die 300a includes a connection via 332 connecting the via 330, and the connection via 330 does not include the connection via 334.

In some embodiments, as shown in FIG. 8, the dielectric layer PM1 is formed on the insulating encapsulation body 140 ′ and physically contacts the insulating encapsulation body 140 ′, and its secondary dielectric layer PM1 has The top surface, a plurality of openings connecting the top surface of the through hole 332 and the top surface of the through hole 130. The material of the dielectric layer PM1 may include polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, or a combination thereof, etc. The dielectric layer PM1 may use micro Patterned by the shadow process and/or the etching process. In some embodiments, the via hole 132 and the via hole 134 are formed on the dielectric layer PM1 and connected to the connection via holes 232, 332 and the through hole 130 through the opening of the dielectric layer PM1. The materials and formation of the through holes 132 and the through holes 134 are the same as or similar to those of the through holes 130 shown in FIG. 1, so they will not be repeated here.

In some embodiments, the chip package CP1 is disposed on the via hole 134 and surrounded by the via hole 132. In some embodiments, as measured in the direction Z, the height of the chip package CP1 is smaller than the height of the via 132. As shown in FIG. 8, the chip package CP1 is aligned with the stacking direction of the redistribution circuit structure 120 and the semiconductor die 200 a (for example, direction Z) (or, the stacking direction of the redistribution circuit structure 120 and the semiconductor die 300 a ). The semiconductor die 200a and the semiconductor die 300a overlap, and the vertical projection on the redistribution wiring structure 120 extends from the semiconductor die 200a to the semiconductor die 300a. Due to the configuration, a short electrical path is realized between the semiconductor die 200a, the semiconductor die 300a, and the chip package CP1 (involving other semiconductor die 400a, 400b), thereby reducing its signal loss.

In some embodiments, the via hole 132, the via hole 134 and the chip package CP1 are encapsulated in the insulating encapsulant 142, and the dielectric layer PM1 exposed by the via hole 132 and the via hole 134 is covered by the insulating encapsulant 142 . As shown in FIG. 8, the bottom surface of the chip package CP1 (for example, the bottom surface 650 b of the semiconductor substrate 650 ), the top surface 132 t of the via hole 132, and the top surface 142 t of the insulating package 142 are substantially flush. In other words, the surface of the chip package CP1 (for example, the bottom surface 650 b of the semiconductor substrate 650) and the top surface 132 t of the via hole 132 and the top surface 142 t of the insulating package 142 are substantially coplanar. In some embodiments, the redistribution circuit structure 150 is located on the chip package CP1, and the via hole 132 and the insulating package 142 are physically connected and electrically connected to the via hole 132. The materials and formation of the insulating encapsulation 142 are the same as or similar to those of the insulating encapsulation 140 and the insulating encapsulation 140' described in Figs. 3 and 4, so they will not be repeated here.

As shown in FIG. 8, respectively, the chip package CP1 is electrically connected to the semiconductor die 200 a through the connection via 690, the via 134 and the connection via 232 and through the connection via 690, the via 134 and the connection via 332 Electrically connected to the semiconductor die 300a. In other words, the chip package CP1 is electrically communicated with the semiconductor die 200a and the semiconductor die 300a, wherein the semiconductor die 200a and the semiconductor die 300a are electrically communicated with each other through the chip package CP1. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 200 a through the redistribution circuit structure 150 and some of the vias 132 of the vias 132. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 300 a through the redistribution circuit structure 150 and some of the via holes 132 of the via holes 132. In some embodiments, some of the conductive elements 160 are electrically connected to the chip package CP1 through the redistribution circuit structure 150, some of the vias 132 of the vias 132, the semiconductor die 200a and/or 300a, and the vias 134 . In some embodiments, some of the conductive elements 160 are electrically connected to the through holes 130 through the redistribution circuit structure 150 and some of the via holes 132 of the via holes 132. In some embodiments, some of the conductive elements 160 are electrically connected to the redistribution circuit structure 120 through the redistribution circuit structure 150, some via holes 132 in the via holes 132 and the through holes 130.

9 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 8 and FIG. 9 together, the semiconductor package SP3 shown in FIG. 8 is similar to the semiconductor package SP4 shown in FIG. 9; thus, components similar to or substantially the same as the above components will use the same reference number, In addition, some details or descriptions of the same elements and their relationships (for example, relative positioning configuration and electrical connection) will not be repeated here.

Referring to FIGS. 8 and 9 together, the difference is that for the semiconductor package SP4 shown in FIG. 9, the dielectric layer PM1 is replaced with a redistribution circuit structure 180. For example, the formation of the redistribution circuit structure 180 includes alternately sequentially forming one or more polymer dielectric layers 182 and one or more metallization layers 184. In some embodiments, as shown in FIG. 9, the redistribution circuit structure 180 includes two polymer dielectric layers 182 and a metallization layer 184 sandwiched between the two polymer dielectric layers 182; However, the embodiments of the present invention are not limited to this. Due to the described configuration of the polymer dielectric layer 182 and the metallization layer 184, a wiring function is provided for the semiconductor package SP4.

The number of metallization layers and polymer dielectric layers included in the redistribution circuit structure 180 is not limited to this. For example, the number of metallization layers and polymer dielectric layers can be one or more than one. The material and formation of the redistribution circuit structure 180 are the same as or similar to the material and formation of the redistribution circuit structure 120 shown in FIG. 1 or the material and formation of the redistribution circuit structure 150 shown in FIG. 5, so they will not be repeated here.

As shown in FIG. 9, the chip package CP1 is electrically connected to the semiconductor die 200 a through the via 134, the redistribution circuit structure 180 (for example, the metallization layer 184 ), and the connection via 232, and the chip package CP1 passes through the via 134, The redistribution circuit structure 180 (for example, the metallization layer 184) and the connection via 332 are electrically connected to the semiconductor die 300a. In other words, the chip package CP1 is electrically communicated with the semiconductor die 200a and the semiconductor die 300a, wherein the semiconductor die 200a and the semiconductor die 300a are electrically communicated with each other through the chip package CP1. In some embodiments, the conductive element 160 is electrically connected to the redistribution circuit structure 180 through the redistribution circuit structure 150 and the via hole 132. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 200a through the redistribution structure 150, some of the vias 132 in the vias 132, and the redistribution structure 180. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 300 a through the redistribution circuit structure 150, some of the via holes 132 in the via holes 132, and the redistribution circuit structure 180. In some embodiments, some of the conductive elements 160 pass through the redistribution circuit structure 150, some of the via holes 132 in the via hole 132, the redistribution circuit structure 180, the via hole 134, and/or the semiconductor die 200a, 300a It is electrically connected to the chip package CP1. In some embodiments, some of the conductive elements 160 are electrically connected to the through holes 130 through the redistribution circuit structure 150, some of the via holes 132 in the via holes 132, and the redistribution circuit structure 180. In some embodiments, some of the conductive elements 160 are electrically connected to the redistribution circuit structure 120 through the redistribution circuit structure 150, some via holes 132 in the via holes 132, the redistribution circuit structure 180 and the through hole 130. Due to the configuration, a short electrical path is realized between the semiconductor die 200a, the semiconductor die 300a, and the chip package CP1 (involving other semiconductor die 400a, 400b), thereby reducing its signal loss.

10 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 6 and FIG. 10 together, the semiconductor package SP1 depicted in FIG. 6 is similar to the semiconductor package SP5 depicted in FIG. 10; thus, components that are similar or substantially the same as the above components will use the same reference number, In addition, some details or descriptions of the same elements and their relationships (for example, relative positioning configuration and electrical connection) will not be repeated here.

6 and FIG. 10 together, the difference is that for the semiconductor package SP5 shown in FIG. 10, the chip package CP2 is included and provided in the positioning position of the semiconductor die 200 shown in FIG. 6. In one embodiment, the semiconductor die 200 is integrated into the chip package CP2. For example, as shown in FIG. 15, the chip package CP2 has a structure similar to the structure of the chip package CP1 shown in FIG. 14, wherein in the chip package CP2, the semiconductor crystal of the chip package CP1 shown in FIG. 14 The grains 400a and 400b are replaced by the semiconductor die 200 and the semiconductor die 400c shown in FIGS. 1 to 6, respectively. In some embodiments, the chip package CP2 may have a structure similar to the structure of the chip package CP1 shown in FIG. 14, wherein in the chip package CP2, the semiconductor dies 400 a and 400 b of the chip package CP1 shown in FIG. 14 It can be replaced by the semiconductor die 200a and the semiconductor die 400c shown in FIGS. 7 to 9, respectively. However, the embodiments of the present invention are not limited to this; in an alternative embodiment, the chip package CP2 may include the same structure as the chip package CP1 depicted in FIG. 14, wherein the semiconductor die 400a, 400b may be of other types The semiconductor die replaces or remains in the chip package CP2.

In one embodiment, the semiconductor die 400c may be the same as the semiconductor die 400a and/or 400b. In alternative embodiments, the semiconductor die 400c may be different from the semiconductor die 400a and 400b. The embodiments of the present invention are not limited to this.

In some embodiments, the enlarged view of the structure of the chip package CP2 shown in FIG. 10 shown in FIG. 15 is for illustration, but not to limit the embodiments of the present invention. As shown in FIG. 15, in the chip package CP2, the interconnect structure 660 is disposed on the semiconductor substrate 650, and the semiconductor die 200 and the semiconductor die 400c are disposed on the interconnect structure 660 and electrically connected to the interconnect structure 660 and encapsulated in the insulating encapsulation body 630, the redistribution circuit structure 620 is disposed on the insulating encapsulation body 630, and the contact pad 670 is disposed on the redistribution circuit structure 620 and distributed over the redistribution circuit structure 620, The protective layer 680 covers the contact pad 670 and has an opening to expose some parts of the contact pad 670, and the connection through hole 690a is provided on the contact pad 670 and is connected to the contact pad 670 through the opening of the protective layer 680, wherein the through hole 640 penetrates the insulating package 630 to be physically connected and electrically connected to the interconnect structure 660 and the redistribution circuit structure 620. In some embodiments, in FIG. 10, the connection through-hole 690a includes at least one connection through-hole 692a and a connection through-hole 694a, wherein the height of the connection through-hole 692a is smaller than the height of the connection through-hole 694a as measured in the direction Z. The material and formation of the connection via 690a are similar to the material and formation of the connection via 690 described in FIG.

In some embodiments, the chip package CP1 is electrically connected to the chip package CP2 through the connection via 690 of the chip package CP1 and the connection via 692a of the chip package CP2, and the chip package CP1 passes through the connection via 690 of the chip package CP1 and the semiconductor crystal The connection via 334 of the die 300 is electrically connected to the semiconductor die 300. In other words, the chip package CP1 is electrically communicated with the chip package CP2 (for example, the semiconductor die 200 and the semiconductor die 400c) and the semiconductor die 300, where the chip package CP2 (for example, the semiconductor die 200 and the semiconductor die The pellet 400c) and the semiconductor die 300 are in electrical communication with each other through the wafer package CP1. In some embodiments, some of the conductive elements 160 are electrically connected to the chip package CP2 (for example, the semiconductor die 200 and the semiconductor die 400c) through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the semiconductor die 300 through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the chip package CP1 through the redistribution circuit structure 150 and the chip package CP2 (eg, the semiconductor die 200 and the semiconductor die 400c) or through the redistribution circuit structure 150 and the semiconductor die 300 are connected to the chip package CP1. In some embodiments, some of the conductive elements 160 are electrically connected to the through holes 130 through the redistribution wiring structure 150. In some embodiments, some of the conductive elements 160 are electrically connected to the redistribution circuit structure 120 through the redistribution circuit structure 150 and the through hole 130.

As shown in FIG. 10, the chip package CP1 is stacked in the stacking direction (for example, direction Z) of the redistribution circuit structure 120 and the chip package CP2 having the semiconductor die 200 (or, the redistribution circuit structure 120 and the semiconductor die 300 Stacking direction) overlaps with the chip package CP2 (for example, the semiconductor die 200) and the semiconductor die 300, and the vertical projection on the redistribution wiring structure 120 extends from the chip package CP2 (for example, the semiconductor die 200) to the semiconductor晶300。 Crystal 300. Due to the configuration, a short electrical path is realized between the chip package CP2 (for example, the semiconductor die 200 and the semiconductor die 400c), the semiconductor die 300 and the chip package CP1 (involving other semiconductor die 400a, 400b), This reduces its signal loss.

According to some embodiments, a semiconductor package includes a first chip package, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant, the first chip package includes a plurality of first semiconductor die and a first Insulation package. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated with each other by being connected to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third On semiconductor die. A second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

According to some embodiments, in the semiconductor package, the second semiconductor die and the third semiconductor die are arranged side by side, and the first chip package extends from the second semiconductor die to the The third semiconductor die. According to some embodiments, the semiconductor package further includes: a first redistribution circuit structure and a second redistribution circuit structure, located between two opposite sides of the second insulating encapsulation body and electrically connected to the A second semiconductor die and the third semiconductor die; and a plurality of conductive elements on the second redistribution wiring structure and electrically connected to the second redistribution wiring structure, wherein the second redistribution wiring The road structure is located between the second insulating envelope and the plurality of conductive elements. According to some embodiments, the semiconductor package further includes: a plurality of through holes penetrating the second insulating encapsulant and connected to the first redistribution circuit structure and the second redistribution circuit structure. According to some embodiments, in the semiconductor package, the first chip package may pass the second semiconductor die, the second redistribution structure, and the plurality of through holes or pass the third semiconductor die The pellet, the second redistribution circuit structure and the plurality of perforations are electrically connected to the first redistribution circuit structure. According to some embodiments, the semiconductor package further includes: a second wafer including the second semiconductor die and the fourth semiconductor die electrically connected to each other; and encapsulating the second semiconductor die and the first The third insulating encapsulation of the semiconductor die. According to some embodiments, in the semiconductor package, the second insulating encapsulant encapsulates the first chip package, the second chip package, and the third semiconductor die. According to some embodiments, in the semiconductor package, the first chip package is stacked on the second chip package and the third semiconductor die and extends from the second chip package to the third Semiconductor die.

According to some embodiments, a semiconductor package includes a first semiconductor die, a second semiconductor die, a first insulating package, a first redistribution circuit structure, and a chip package. The first semiconductor die and the second semiconductor die are encapsulated in the first insulating encapsulant. The first redistribution circuit structure is located on the first insulating package and is electrically connected to the first semiconductor die and the second semiconductor die. The chip package is electrically connected to the first semiconductor die and the second semiconductor die, wherein the chip package includes: a plurality of third semiconductor die, electrically connected to each other; and a second insulating encapsulant, Encapsulating the plurality of third semiconductor die. In the stacking direction of the first redistribution circuit structure and the first insulating encapsulant, the chip package overlaps the first semiconductor die and the second semiconductor die.

According to some embodiments, in the semiconductor package, the first semiconductor die and the second semiconductor die are arranged side by side, and the chip package extends from the first semiconductor die to the second Semiconductor die. According to some embodiments, in the semiconductor package, the chip package is located between the first redistribution circuit structure and the first insulating package. According to some embodiments, the semiconductor package further includes: a plurality of via holes located beside the positioning position of the chip package; and a third insulating encapsulation body that encapsulates the chip package and the plurality of via holes, The third insulating encapsulation body is located between the first insulating encapsulation body and the first redistribution circuit structure. According to some embodiments, in the semiconductor package, the second insulating encapsulation is surrounded by the third insulating encapsulation. According to some embodiments, the semiconductor package further includes: a second redistribution circuit structure located between the first insulating encapsulant and the third insulating encapsulant and electrically connected to the first semiconductor crystal Grains and the second semiconductor die, wherein the chip package is sandwiched between the first redistribution circuit structure and the second redistribution circuit structure. According to some embodiments, in the semiconductor package, the chip package is located on the first redistribution circuit structure and is electrically connected to the first redistribution circuit structure, and the first redistribution circuit structure is located at Between the chip package and the first insulating package. According to some embodiments, the semiconductor package further includes: a plurality of conductive elements on the first redistribution circuit structure and electrically connected to the first redistribution circuit structure, wherein the first redistribution circuit structure Located between the plurality of conductive elements and the first insulating envelope.

According to some embodiments, there is provided a method of manufacturing a semiconductor package, the manufacturing method having the following steps: providing a carrier; disposing a first semiconductor die and a second semiconductor die on the carrier; And a chip package is disposed on the second semiconductor die, the chip package includes a plurality of third semiconductor die electrically connected to each other and an insulating material encapsulating the plurality of third semiconductor die, wherein the The chip package extends from the first semiconductor die to the second semiconductor die and is electrically connected to the first semiconductor die and the second semiconductor die; the first semiconductor die and the The second semiconductor die is encapsulated in an insulating encapsulation body; a first redistribution circuit structure is formed on the insulating encapsulation body; and a plurality of conductive elements are formed on the first redistribution circuit structure.

According to some embodiments, in the manufacturing method, the chip package is disposed on the first semiconductor die and the second semiconductor die after the first semiconductor die and the first The second semiconductor die is encapsulated in the insulating encapsulation body, wherein encapsulating the first semiconductor die and the second semiconductor die in the insulating encapsulation body further includes encapsulating the wafer The package is encapsulated in the first insulating package. According to some embodiments, in the manufacturing method, the chip package is disposed on the first semiconductor die and the second semiconductor die before the forming of the first redistribution structure And after encapsulating the first semiconductor die and the second semiconductor die in the insulating encapsulation body, the chip package is disposed in the first redistribution circuit structure and the Between insulated enclosures. According to some embodiments, in the manufacturing method, the forming of the first redistribution circuit structure is before the wafer package is disposed on the first semiconductor die and the second semiconductor die It is performed to arrange the chip package on the first redistribution circuit structure, wherein the chip package is electrically connected to the first redistribution circuit structure.

Although the embodiments of the present invention are disclosed as above, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the embodiments of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

110‧‧‧ Carrier 120, 150, 180, 620‧‧‧ Redistribution circuit structure 122, 152, 182, 622‧‧‧ Polymer dielectric layer 124, 154, 184, 624‧‧‧‧Metalization layer 130, 640 ‧‧‧Perforation 130t, 132t, 140t, 142t, 232t, 332t ‧‧‧ top surface 132, 134‧‧‧ through hole 140, 140', 142, 630 ‧‧‧ insulation encapsulant 154a Pattern 154b ‧‧‧ connection pad 160 ‧‧‧ conductive element 200, 200a, 300, 300a, 400a, 400b, 400c ‧‧‧ semiconductor die 210, 310, 410a, 410b, 650 ‧ ‧‧ semiconductor substrate 210a, 310a , 410at, 410bt, 650a ‧‧‧ active surface 220, 320, 660 ‧‧‧ interconnect structure 222, 322, 662 ‧ ‧‧ interlayer dielectric layer 224, 324, 664 ‧ ‧ ‧ ‧ patterned conductive layer 230, 232 , 234, 330, 332, 334, 450a, 450b, 690, 690a, 692a, 694a ‧‧‧ through hole 410ab, 410bb ‧‧‧ back surface 420a, 420b ‧‧‧ conductive pads 430a, 430b ‧‧‧ Passivation layer 440a, 440b ‧‧‧ Rear passivation layer 460a, 460b, 680 ‧‧‧ Protective layer 650b ‧ ‧ ‧ bottom surface 670 ‧ ‧ ‧ contact pads CP1, CP2 ‧ ‧ ‧ chip package DA1, DA2 ‧ ‧ ‧ connection film IF‧‧‧ Hybrid bonding interface PM1‧‧‧ Dielectric layers SP1, SP2, SP3, SP4, SP5 ‧‧‧ Semiconductor package Z‧‧‧ Direction

According to the following detailed description and the accompanying drawings to understand the embodiments of the present invention. It should be noted that according to the general operations of the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be arbitrarily increased or decreased. 1 to 6 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present invention. 7 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 8 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 9 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 10 is a schematic cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention. 11 to 14 are schematic cross-sectional views of various stages in a method of manufacturing a wafer package included in a semiconductor package according to some exemplary embodiments of the present invention. 15 is a schematic cross-sectional view of a wafer package included in a semiconductor package according to some exemplary embodiments of the present invention.

110‧‧‧Carrier

120, 150‧‧‧ heavy wiring structure

122, 152‧‧‧ Polymer dielectric layer

124, 154‧‧‧Metalized layer

130‧‧‧Perforation

130t, 140t‧‧‧top surface

140’‧‧‧Insulation Envelope

154a‧‧‧Metal pattern under the ball

160‧‧‧Conducting element

200, 300 ‧‧‧ semiconductor die

210, 310‧‧‧ semiconductor substrate

232, 234, 332, 334, 690

CP1‧‧‧chip package

DA1, DA2‧‧‧Connecting film

SP1‧‧‧Semiconductor package

Z‧‧‧ direction

Claims (1)

A semiconductor package includes: a first chip package, including: a plurality of first semiconductor dies, electrically connected to each other; and a first insulating encapsulant, encapsulating the plurality of first semiconductor dies; a second semiconductor die And a third semiconductor die, which are electrically connected to each other by being connected to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die; and the second An insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Images