TW201928971A - Memory device - Google Patents

Abstract

A memory device includes a plurality of read word lines, a plurality of first write word lines, at least a memory unit and at least a read control circuit. Each memory unit includes a plurality of memory cell groups elongated along a first direction, and each memory cell group includes at least a memory cell, a plurality of local read bit lines, each local read bit line is coupled to the corresponding memory cell group, a read bit line elongated along the first direction for transmitting a to-be-read data, a write bit line elongated along the first direction for transmitting a to-be-written data, a first write column word line elongated along the first direction, and a read column word line elongated along the first direction.

Description

Memory device

The present invention relates to a memory device, and more particularly to a memory device that can address a threshold voltage loss and reduce power consumption.

In general, a static random access memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory elements arranged in an array pattern, wherein each of the write word lines is coupled to a column of memory elements. . Each read bit line is coupled to a row of memory elements. Please refer to FIG. 1 , which is a schematic diagram of a conventional memory component 10 . As shown in FIG. 1, the memory device 10 includes a storage element SC, access transistors T1, T2, T3, and T4, wherein the storage element SC includes a write pull-up transistor WU, and a write pull-down power. The crystal WD, a read pull-up transistor RU, and a read pull-down transistor RD. Each access transistor T1, T2, T3 and T4 is used to control the conduction state between the storage element SC and a write bit line WBL and a read bit line RBL. Therefore, when the access transistors T1, T2, T3, and T4 are turned on, the storage element SC can be coupled to the bit line for a read or write operation.

However, since the write bit line WBL to a node QB has the write pull-up transistor WU and the write pull-down transistor WD, when the signal 0 is to be written, the potential of the write bit line WBL is 0, however, The transistors T3 and T4 are twice as large as the case where only one write transistor is used. Therefore, the voltage at the QB point is too high, making it difficult for the write pull-up transistor WU to be turned on to cause writing 0. In addition to this, when the signal 1 is to be written, in addition to the problem of writing difficulty similar to the write signal 0, there is a problem of threshold voltage loss, which makes writing 1 difficult. Therefore, the prior art does have the need for improvement.

Accordingly, it is an object of the present invention to provide a memory device for addressing a threshold voltage loss of a static random access memory device to ameliorate the disadvantages of the prior art.

The invention discloses a memory device comprising a plurality of read word lines; a plurality of first write word lines; at least one memory unit, wherein each memory unit comprises a plurality of memory element groups, along a first direction setting, and each memory element group includes at least one memory element; a plurality of areas read bit lines, and each area read bit line is coupled to a corresponding memory element group; a read bit line disposed along the first direction for transmitting a read data; a write bit line disposed along the first direction for transmitting a written data; a first write An entry word line disposed along the first direction; and a read line word line disposed along the first direction; wherein each memory element includes a write inverter including a write pullup The transistor is connected in series with a write-down transistor; a read inverter includes a read pull-up transistor in series with a read pull-down transistor; a first write access transistor coupled to the write Into the inverter and the write bit line, the write access transistor includes Having two control terminals, one of the at least two control terminals being coupled to the corresponding first write word line, the other end coupled to the first write line word line; and a read access The transistor is coupled to the read inverter and the corresponding area read bit line, the read access transistor includes at least one control end, and the at least one control end is coupled to the corresponding read word line An output of one of the read inverters is coupled to an input of the write inverter, and an input of the read inverter is coupled to an output of the write inverter And a read control circuit, wherein each read control circuit includes a first control end coupled to the corresponding area read bit line; a second control end coupled to the read line word An input end coupled to a bias voltage; and an output end coupled to the read bit line.

The present invention further discloses a memory device comprising a read word line; a first write word line; a read bit line disposed along a first direction for transmitting a read data; Writing a bit line, disposed along the first direction for transmitting a written data; a first write line word line disposed along the first direction; and a memory element including a write reverse The phase device comprises a write pull-up crystal in series with a write pull-down transistor; a read inverter comprising a read pull-up transistor in series with a read pull-down transistor; a first write save The first write access transistor includes at least two control terminals, and one of the at least two control terminals is coupled to the write transistor and the write bit line. a first write word line, the other end of which is coupled to the first write line word line; and a read access transistor coupled to the read inverter and a read bit line, The read access transistor includes at least one control end coupled to the read word line; wherein the read One-phase output terminal is coupled to one input terminal of the inverter is written, and one of the read input of the inverter coupled to the output end of one of the write inverter.

The present invention further discloses a memory device comprising a plurality of read word lines; at least one memory unit, wherein each memory unit comprises: a plurality of memory element groups disposed along a first direction and each a memory component group includes at least one memory component; a plurality of regions read bit lines, each region read bit line is coupled to a corresponding memory component group; and a read bit line is along The first direction is configured to transmit a read data; a read line word line is disposed along the first direction; and at least one read control circuit, wherein each read control circuit is an independent double gate The pole transistor includes a first control end coupled to the corresponding area read bit line; a second control end coupled to the read line word line; and an input end coupled to a bias And an output coupled to the read bit line.

Please refer to FIG. 2, which is a schematic diagram of a memory device 20 according to an embodiment of the present invention. As shown in FIG. 2, the memory device 20 includes a plurality of read row word lines RCWL, a plurality of first write line word lines FWCWL, a plurality of read word lines RWL, and a plurality of write characters. Line WWL and a plurality of memory units MU. In an embodiment, each memory cell MU can correspond to a different bit line (not shown) to select a corresponding memory through the read row word line RCWL or the first write line word line FWCWL. Body unit MU. Next, please refer to FIG. 3, which is a schematic diagram of a memory unit MU according to an embodiment of the present invention. As shown in FIG. 3, each memory cell MU is disposed along an X-axis direction, and includes a write bit line WBL, a read bit line RBL, a first write line word line FWCWL, A read row word line RCWL, a plurality of stripe read bit lines LRBL, at least one memory element group MG ₁ to MG _m, and at least one read control circuit RCC ₁ to RCC _m . The write bit line WBL, the read bit line RBL, the first write line word line FWCWL, and the read line word line RCWL are disposed along the X-axis direction. The memory element groups MG ₁ to MG _{m are} used to store data for performing data reading operations when data transfer between the memory element groups MG ₁ to MG _m and the bit lines is enabled.

In detail, the memory element groups MG ₁ to MG _m include a plurality of memory elements MC ₁₁ to MC _mn for receiving a written data from the write bit line WBL and from the read bit line RBL. One of the materials was read. In addition, each read control circuit RCC ₁ ~ RCC _m through the read bit line region coupled to a corresponding LRBL memory element groups MG ₁ ~ MG _m, and the corresponding selected memory through the read word line RWL The elements MC ₁₁ to MC _mn perform operations of reading or writing data. Since each of the memory element groups MG ₁ to MG _m is composed of a plurality of memory elements MC, the memory element MC outputs data through the corresponding area read bit line LRBL and the corresponding read control circuit RCC. Go to the read bit line RBL. In addition, in one embodiment, the memory element may be implemented by a Stationary Random Access Memory Cell (SRAM Cell), but is not limited thereto. The writing method of the memory unit MU may be other types, and any method capable of writing to the memory unit MU is applicable to the present invention.

Please refer to FIG. 4, which is a schematic diagram of a memory device MC according to an embodiment of the present invention. The memory element MC includes a write inverter WI, a read inverter RI, a first write access transistor FWAT and a read access transistor RAT, and the write inverter WI is composed of a The write pull-up transistor WU is formed in series with a write pull-down transistor WD. The read inverter RI is composed of a read pull-up transistor RU and a read pull-down transistor RD in series. The first write access transistor FWAT includes two control terminals WA and CWA. The control terminal WA is coupled to the corresponding write word line WWL, and the control terminal CWA is coupled to the first write line word line FWCWL. The read access transistor RAT is coupled to the read inverter RI and the corresponding area read bit line LRBL, and the read access transistor RAT includes at least one control end, wherein at least one control end is coupled to the corresponding Read word line RWL. In addition, an output terminal of the read inverter RI is coupled to one input terminal of one of the write inverters WI, and one input terminal of the read inverter RI is coupled to the write inverter WI. One of the outputs is coupled to a node QB. In an embodiment, the writing end of each memory element MC ₁₁ ～ MC _mn of the memory unit MU may be a double gate transistor (Double-Gate Transistor) or a separate double gate transistor (Independent Double- Gate Transistor) implementation. In this case, when the write bit line WBL is to be written with the logic signal 0 or 1 (corresponding to a low potential or a high potential), the write word line WWL is simultaneously with the first write line word line FWCWL. Greater than a threshold voltage to turn on the first write access transistor FWAT and write data into the memory element MC; similarly, when reading is performed, the voltage of the read word line RWL is greater than The threshold voltage is turned on to turn on the read access transistor RAT, and the data is output to the read bit line RBL. In this way, the memory unit MU realizes the writing end of each of the memory elements MC ₁₁ to MC _mn as a double gate transistor, and the voltage difference between the two transistors with respect to FIG. 1 , the present invention The memory cell MU has only one transistor voltage difference, thereby reducing the problem of threshold voltage loss (Threshold Voltage Loss).

On the other hand, as shown in FIG. 3, the read control circuit RCC ₁ includes an input coupled to a bias RB ₁ , an output coupled to the read bit line RBL, and a first control terminal C _{11 .} The second read terminal LRBL and the second control terminal C _{12 are} coupled to the read row word line RCWL. The read control circuit RCC ₁ operates according to the first control terminal C ₁₁ and the second control terminal C ₁₂ to operate in an output enable state and an output disable state (Disable State). Similarly, the read control circuit RCC ₂ operates according to a first control terminal C ₂₁ and a second control terminal C ₂₂ to operate in an output enable state and an output disable state, and so on.

In detail, please refer to Figure 3 for the operation principle of the read control circuit RCC. Taking the read control circuit RCC ₁ as an example, when the initial read bit line RBL is pre-charged to the potential 0, the bias RB ₁ controls the read bit line RBL to be the potential 1 and is read by the character. when line RWL corresponding to the selected memory cell MC is turned on, at this time, the bias RB ₁ nonconducting, LRBL area reading bit line potential is determined by the selected memory cell MC. For example, when the data of the selected memory element MC ₁₁ is 0, the area read bit line LRBL is at potential 0, the read control circuit RCC _{1 is} turned on, and the read bit line RBL is charged to the potential. 1; conversely, when the data of the selected memory element MC is 1, the area read bit line LRBL is at potential 1, the read control circuit RCC _{1 is} not turned on, and the read bit line RBL is maintained at the potential 0. Therefore, when the read control circuit RCC operates in the output enable state through the two control terminals, the bias voltage RB ₁ is output. Therefore, the memory element MC output data to the read bit line RBL is commonly selected by the read word line RWL and the read line word line RCWL. It should be noted that, in an embodiment, an inverter may be added to the read bit line RBL, or the opposite data may be written to the write end to make the input data coincide with the data output by the memory element MC. Alternatively, the read control circuit RCC and the bias voltage RB may be implemented by an NMOS transistor and a bias potential 0 such that the read bit line RBL is precharged to a potential 1 (ie, a VDD or a high potential) when precharged.

It is worth noting that the write access transistor and the read access transistor are connected in groups to the corresponding bit lines, or the write access transistor and the read access power are compared to the prior art. The crystals are individually connected to the corresponding bit lines, and each of the first write access transistors FWAT of the memory device MC of the present invention is connected to the write bit line WBL, and the read access transistor RAT is The group bit (ie, memory element group MG) is connected to the read bit line RBL and the read control circuit RCC to achieve power consumption and area optimization of the memory device 20.

In addition, compared with the memory element 10 of FIG. 1 , the memory element 10 is moved by two bit lines each time, and the power consumption is large. The memory element MC of the present invention is written by one bit line. In, another bit line is responsible for reading, with lower power consumption.

The foregoing embodiments are provided to illustrate the concept of the present invention, and those skilled in the art can make various modifications, and are not limited thereto. For example, the transistor of the bias RB can also be implemented with a large resistance to eliminate the bias control, or the read control circuit RCC and the first write access transistor FWAT, which can be independent double gates. Crystals or Multi-Gate Transistors, which meet the requirements of the present invention, fall within the scope of the present invention.

Specifically, in another embodiment, please refer to FIG. 5 and FIG. 6 simultaneously. FIG. 5 is a schematic diagram of another memory unit MU according to an embodiment of the present invention, and FIG. 6 is another embodiment of the present invention. A schematic diagram of a memory element MC. Different from the memory unit MU of FIG. 3 and the memory element MC of FIG. 4, the memory unit MU further includes a second write line word line SWCWL coupled to each memory of each memory unit MU. Element MC. In detail, as shown in FIG. 6, each memory element MC further includes a second write access transistor SWAT coupled to the write bit line WBL and coupled to the write inverter WI. Node QBN. The second write access transistor SWAT includes control terminals WAN and CWAN to be respectively coupled to a second write word line SWWL and a second write line word line SWCWL. In this way, the memory element MC of the memory cell MU can use the pair of transistors (ie, the first write access transistor FWAT and the second write memory) between the write bit line WBL and the memory element MC. The transistor SWAT) increases/maintains the drive capability of writing logic 1 to avoid the problem of threshold voltage loss. It should be noted that, in an embodiment, the first write access transistor FWAT and the second write access transistor SWAT may be N-type transistors or P-type transistors, respectively, and are not limited thereto.

In detail, in the case where the first write access transistor FWAT is an N-type transistor and the second write access transistor SWAT is a P-type transistor, when the logic signal 1 (corresponding to a high potential) is When writing to the memory element MC, the gate voltage of the second write access transistor SWAT can be controlled to be low, and the second write access transistor SWAT can be turned ON. At this time, since the second write access transistor SWAT is a PMOS transistor, the current flowing through the second write access transistor SWAT is controlled by the voltage V _SG between the source and the gate because the node QBN The voltage rises with time, because the voltage V _SG between the write bit line WBL and the gate is not affected, so the current flowing through the second write access transistor SWAT is not weakened by the voltage rise of the node QBN. . In other words, the memory element MC of the memory cell MU uses the second write access transistor SWAT to increase/maintain the drive capability of the write logic 1, avoiding the problem of threshold voltage loss.

It should be noted that the first write access transistor FWAT or the second write access transistor SWAT may be an Independent Double-Gate Transistor or a Multi-Gate Transistor (Multi). -Gate Transistor), which satisfies the requirements of the present invention, is within the scope of the present invention.

In summary, the memory device of the present invention selects a corresponding memory unit and a memory element through a read control circuit to reduce power consumption of the memory device, and is paired between the bit line and the memory element. The transistor increases/maintains the access capability of the SRAM and avoids the problem of threshold voltage loss. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, MC, MC ₁₁ ~ MC _1n , MC ₂₁ ~ MC _2n , MC _m1 ~ MC _mn ‧ ‧ memory components

C ₁₁ ~ C _m1 ‧‧‧ first control end

C ₁₂ ~ C _m2 ‧‧‧second control end

FWAT‧‧‧first write access transistor

FWCWL‧‧‧First write line word line

LRBL‧‧‧ area read bit line

MG, MG ₁ ~ MG _m ‧‧‧ memory component group

MU‧‧‧ memory unit

Q, QB, QBN‧‧‧ nodes

RAT‧‧‧Read access transistor

RB, RB ₁ ~ RB _m ‧ ‧ bias

RBL‧‧‧Read bit line

RCC, RCC ₁ ~ RCC _m ‧‧‧ read control circuit

RCWL‧‧‧Read line word line

RD‧‧‧Read pull-down transistor

RI‧‧‧Reading inverter

RU‧‧‧Read pull-up crystal

RWL‧‧‧Read word line

SC‧‧‧Storage components

SWAT‧‧‧Second write access transistor

SWCWL‧‧‧Second write line word line

SWWL‧‧‧second write word line

T1, T2, T3, T4‧‧‧ transistors

WA, CWA, WAN, CWAN‧‧‧ control terminal

WBL‧‧‧Write bit line

WD‧‧‧Write pull-down transistor

WI‧‧‧Write inverter

WU‧‧‧Write pull-up crystal

WWL‧‧‧Write word line

Figure 1 is a schematic diagram of a conventional memory component. FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a memory unit according to an embodiment of the present invention. Figure 4 is a schematic diagram of a memory element in accordance with an embodiment of the present invention. FIG. 5 is a schematic diagram of another memory unit according to an embodiment of the present invention. Figure 6 is a schematic illustration of another memory component in accordance with an embodiment of the present invention.

Claims (20)

A memory device comprising: a plurality of read word lines; a plurality of first write word lines; at least one memory unit, wherein each memory unit comprises: a plurality of memory element groups, along a The first direction is set, and each memory element group includes at least one memory element; the plurality of areas read the bit line, and each of the area read bit lines is coupled to the corresponding memory element group; Reading a bit line disposed along the first direction for transmitting a read data; a write bit line disposed along the first direction for transmitting a written data; a first write a row word line disposed along the first direction; and a read row word line disposed along the first direction; wherein each memory element comprises: a write inverter comprising a write The pull transistor is connected in series with a write pull-down transistor; a read inverter includes a read pull-up transistor in series with a read pull-down transistor; a first write access transistor coupled to the Writing to the inverter and the write bit line, the write access transistor Included in the at least two control terminals, one of the at least two control terminals is coupled to the corresponding first write word line, the other end is coupled to the first write line word line; The read transistor is coupled to the read inverter and the corresponding area read bit line, the read access transistor includes at least one control end, and the at least one control end is coupled to the corresponding read character An output of one of the read inverters is coupled to one of the input terminals of the write inverter, and one of the input terminals of the read inverter is coupled to one of the write inverters And a read control circuit, wherein each of the read control circuits includes: a first control end coupled to the corresponding area read bit line; a second control end coupled to the read An input word line; an input end coupled to a bias voltage; and an output end coupled to the read bit line. The memory device of claim 1, wherein the at least one read control circuit operates in an output enable state and an output disable state according to a voltage of the first control terminal and the second control terminal, wherein The bias is output to the output when the at least one read control circuit is in an enabled state. The memory device of claim 1, wherein the first write access transistor system is a double gate transistor (Double-Gate Transistor). The memory device of claim 1, wherein the first write access transistor system is an Independent Double-Gate Transistor. The memory device of claim 1, further comprising: a plurality of second write word lines; the at least one memory unit further comprising a second write line word line, and each memory element further comprises There is: a second write access transistor coupled to the write inverter and the write bit line, the second write access transistor comprising at least two control terminals, the at least two controls One of the terminals is coupled to the corresponding second write word line, and the other end is coupled to the second write line word line; wherein the first write access transistor system is an NMOS transistor and the The second write accesses the transistor system to a PMOS transistor. The memory device of claim 5, wherein the second write access transistor system is a double gate transistor (Double-Gate Transistor). The memory device of claim 5, wherein the second write access transistor system is an Independent Double-Gate Transistor. The memory device of claim 1, wherein the at least one read control circuit is a double gate transistor. The memory device of claim 1, wherein the at least one read control circuit is a separate dual gate transistor. The memory device of claim 1, wherein the plurality of first write word lines and the plurality of read word lines are the same. The memory device of claim 1, further comprising at least one bias circuit coupled to the corresponding region read bit line. A memory device comprising: a read word line; a first write word line; a read bit line, disposed along a first direction for transmitting a read data; a line along the first direction for transmitting a written data; a first write line word line disposed along the first direction; and a memory element including: a write inversion The device includes a write pull-up transistor in series with a write pull-down transistor; a read inverter including a read pull-up transistor in series with a read pull-down transistor; a first write access a transistor coupled to the write inverter and the write bit line, the first write access transistor includes at least two control terminals, and one of the at least two control terminals is coupled to the first a write word line, the other end is coupled to the first write line word line; and a read access transistor coupled to the read inverter and a read bit line, the read The access transistor includes at least one control terminal, and the at least one control terminal is coupled to the read word line; wherein the reading One-phase output terminal is coupled to one input terminal of the inverter is written, and one of the read input of the inverter coupled to the output end of one of the write inverter. The memory device of claim 12, wherein the first write access transistor system is a double-gate transistor (Double-Gate Transistor). The memory device of claim 12, wherein the first write access transistor system is an Independent Double-Gate Transistor. The memory device of claim 12, further comprising: a second write row word line disposed along the first direction; a second write word line; and the memory component further comprising: a second write access transistor coupled to the write inverter and the write bit line, the second write access transistor comprising at least two control terminals, wherein the at least two control terminals are One of the first write word line is coupled to the second write word line; the other end is coupled to the second write line word line; wherein the first write access transistor system is an NMOS transistor and the second write Access to the electro-crystalline system a PMOS transistor. The memory device of claim 15, wherein the second write accesses the gate system to a double gate transistor (Double-Gate Transistor). The memory device of claim 15, wherein the second write access transistor system is an Independent Double-Gate Transistor. The memory device of claim 12, wherein the first write word line is the same as the read word line. A memory device comprising: a plurality of read word lines; and at least one memory unit, wherein each memory unit comprises: a plurality of memory element groups disposed along a first direction and each memory The body component group includes at least one memory component; the plurality of regions read the bit line, each of the region read bit lines is coupled to the corresponding memory component group; and the read bit line is along the first a direction setting for transmitting a read data; a read line word line disposed along the first direction; and at least one read control circuit, wherein each read control circuit is an independent double gate The crystal includes: a first control end coupled to the corresponding area read bit line; a second control end coupled to the read line word line; an input end coupled to a bias And an output coupled to the read bit line. The memory device of claim 19, further comprising: a plurality of write word lines; at least one write bit line disposed along the first direction for transmitting a written data; and at least one bias The voltage circuit is connected to the corresponding area read bit line.