TW201926702A - Trench metal oxide semiconductor device - Google Patents

Abstract

A trench metal oxide semiconductor device including a substrate, a first dielectric layer, a first lower electrode, a second lower electrode, a first upper electrode and a second upper electrode is provided. The substrate has a trench. The trench has a first sidewall and a second sidewall opposite to each other. The first dielectric layer is disposed on a surface of the trench. A top portion of the first dielectric layer is lower than a top portion of the trench. The first lower electrode is disposed on the first dielectric layer located on the first sidewall. The second lower electrode is disposed on the first dielectric layer located on the second sidewall. The first upper electrode is disposed on the first sidewall above the first dielectric layer. The second upper electrode is disposed on the second sidewall above the first dielectric layer. The first lower electrode, the second lower electrode, the first upper electrode, the second upper electrode and the substrate are electrically insulated from each other in the trench.

Description

Grooved metal oxide semiconductor component

This invention relates to a semiconductor component, and more particularly to a trench MOS device.

With the development of the semiconductor industry and product requirements, trench MOS devices with shield gates are widely used in power switch components. Since the trench MOS device having the shield gate has many excellent properties, it is more advantageous in some applications than the conventional MOS transistor switch structure. For example, trench MOS devices with shield gates have lower transistor gate leakage capacitance, lower on-resistance, and provide higher breakdown voltage.

In general, a conventional trench MOS device has a lower electrode and an upper electrode in a single trench, and the lower electrode serves as a shield gate. However, the conventional trench MOS device has a complicated process and a high process cost. Therefore, how to reduce the number of processes and reduce the manufacturing cost is an active goal of the industry.

The present invention provides a trench MOS device and a method of manufacturing the same, which can effectively reduce the number of processes and reduce the manufacturing cost.

The present invention provides a trench MOS device including a substrate, a first dielectric layer, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode. The substrate has a groove. The trench has a first sidewall and a second sidewall opposite to each other. The first dielectric layer is disposed on a surface of the trench. The top of the first dielectric layer is lower than the top of the trench. The first lower electrode is disposed on the first dielectric layer on the first sidewall. The second lower electrode is disposed on the first dielectric layer on the second sidewall. The first upper electrode is disposed on the first sidewall above the first dielectric layer. The second upper electrode is disposed on the second sidewall above the first dielectric layer. The first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode are electrically insulated from each other in the trench.

According to an embodiment of the present invention, in the trench MOS device, a second dielectric layer and a third dielectric layer may be further included. The second dielectric layer is disposed between the first upper electrode and the substrate. The third dielectric layer is disposed between the second upper electrode and the substrate.

According to an embodiment of the present invention, in the trench MOS device, the second dielectric layer and the third dielectric layer may respectively extend to a top surface of the substrate.

According to an embodiment of the present invention, in the trench MOS device, a fourth dielectric layer may be further included. The fourth dielectric layer fills the trench and covers the first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode.

The present invention provides a method of fabricating a trench MOS device, comprising the following steps. A substrate is provided having a trench having first and second sidewalls opposite each other. A first dielectric layer is formed on the surface of the trench, the top of the first dielectric layer being lower than the top of the trench. A first lower electrode is formed on the first dielectric layer on the first sidewall. A second lower electrode is formed on the first dielectric layer on the second sidewall. A first upper electrode is formed on the first sidewall above the first dielectric layer. A second upper electrode is formed on the second sidewall above the first dielectric layer. The first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode are electrically insulated from each other in the trench.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the method of forming the first dielectric layer may include the following steps. A conformal first layer of dielectric material is formed in the trench. A photoresist layer is formed on the first dielectric material layer. The top of the photoresist layer is lower than the top of the trench. The first layer of dielectric material not covered by the photoresist layer is removed.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the method of forming the photoresist layer includes the following steps. A layer of photoresist filled with a trench is formed on the first layer of dielectric material. An etch back process is performed on the photoresist layer.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the method of forming the first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode may include the following steps . An electrode material layer is conformally formed on the first dielectric layer and on the first sidewall above the first dielectric layer and on the second sidewall. An etch back process is performed on the electrode material layer.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the following steps may be further included. A second dielectric layer is formed between the first upper electrode and the substrate. A third dielectric layer is formed between the second upper electrode and the substrate.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the second dielectric layer and the third dielectric layer may be formed on the top surface of the substrate.

According to an embodiment of the present invention, in the method of fabricating the trench MOS device, the fourth dielectric layer filling the trench may be further formed. The fourth dielectric layer covers the first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode.

Based on the above, in the trench MOS device and the method of fabricating the same, the first lower electrode, the second lower electrode, the first upper electrode and the second upper electrode may be provided in the same trench. That is, there may be two sets of shielding gates and two sets of channel gates in the same trench, so that the number of processes and the manufacturing cost can be effectively reduced.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1G are cross-sectional views showing a manufacturing process of a trench MOS device according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 includes a germanium substrate, and may further include an epitaxial germanium layer disposed on the germanium substrate. The substrate 100 has a trench 102. The trench 102 has a first sidewall SW1 and a second sidewall SW2 that are opposite to each other. The trenches 102 can be formed by patterning the substrate 100 using a combination of a lithography process and an etch process.

A conformal layer of dielectric material 104 can then be formed in the trenches 102. The material of the dielectric material layer 104 may be ruthenium oxide. The method of forming the dielectric material layer 104 may be a thermal oxidation method or a chemical vapor deposition method.

Referring to FIG. 1B, a photoresist material layer 106 filling the trenches 102 may be formed on the dielectric material layer 104. The material of the photoresist layer 106 can be a positive photoresist material, a negative photoresist or any known photoresist material. The method of forming the photoresist layer 106 may be a spin coating method.

Referring to FIG. 1C, the photoresist layer 106 may be etched back, whereby the photoresist layer 106a may be formed on the dielectric material layer 104. The top of the photoresist layer 106a is lower than the top of the trench 102. The etch back process for the photoresist layer 106 can be a dry etch process or a wet etch process.

Referring to FIG. 1D, the dielectric material layer 104 not covered by the photoresist layer 106a may be removed, whereby the dielectric layer 104a may be formed on the surface of the trench 102. The top of the dielectric layer 104a is lower than the top of the trench 102. The method of removing the dielectric material layer 104 that is not covered by the photoresist layer 106a may be a dry etching method or a wet etching method.

Referring to FIG. 1E, the photoresist layer 106a is removed. The method of removing the photoresist layer 106a may be a dry photoresist process or a wet photoresist process.

Next, a dielectric layer 108a may be formed on the sidewall SW1 above the dielectric layer 104a, and a dielectric layer 108b may be formed on the sidewall SW2 above the dielectric layer 104a. In addition, the dielectric layer 108a and the dielectric layer 108b may be formed on the top surface of the substrate 100. The method of forming the dielectric layer 108a and the dielectric layer 108b may be a thermal oxidation method.

Thereafter, the electrode material layer 110 may be conformally formed on the sidewall SW1 above the dielectric layer 104a, the sidewall SW1 above the dielectric layer 104a, and the electrode material layer 110 may cover the dielectric layer 108a and the dielectric layer 108b. The material of the electrode material layer 110 may be doped polysilicon. The doping polysilicon can be formed by first forming an undoped polysilicon, then doping the undoped polysilicon, or using an in-situ doping chemical vapor deposition method.

Referring to FIG. 1F, the electrode material layer 110 is etched back to remove a portion of the electrode material layer 110. Thereby, the lower electrode BG1 can be formed on the dielectric layer 104a on the sidewall SW1, and the lower electrode BG2 can be formed on the dielectric layer 104a on the sidewall SW2, which can be on the sidewall SW1 above the dielectric layer 104a. The upper electrode TG1 is formed, and the upper electrode TG2 can be formed on the side wall SW2 above the dielectric layer 104a. The lower electrode BG1 and the lower electrode BG2 can respectively serve as shielding gates, and the upper electrode TG1 and the upper electrode TG2 can respectively serve as channel gates. Further, the upper electrode TG1 may be on the dielectric layer 108a, and the upper electrode TG2 may be on the dielectric layer 108b. The etch back process performed on the electrode material layer 110 may be a dry etch process.

In addition, the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, the upper electrode TG2, and the substrate 100 are electrically insulated from each other in the trench 102. For example, the dielectric layer 104a can be disposed between the lower electrode BG1 and the substrate 100 and between the lower electrode BG2 and the substrate 100 by separating the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode TG2. The dielectric layer 108a is disposed between the upper electrode TG1 and the substrate 100, and the dielectric layer 108b is disposed between the upper electrode TG2 and the substrate 100, so that the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode The TG 2 and the substrate 100 are electrically insulated from each other in the trench 102.

Referring to FIG. 1G, a dielectric layer 112 filling the trenches 102 can be formed. The dielectric layer 112 covers the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode TG2. The material of the dielectric layer 112 may be ruthenium oxide. The method of forming the dielectric layer 112 may be a chemical vapor deposition method.

According to the above embodiment, the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode TG2 can be formed in the same trench 102 by the method of manufacturing the trench MOS device 10.

Hereinafter, the structure of the trench MOS device 10 of the present embodiment will be described with reference to FIG. 1G.

Referring to FIG. 1G, the trench MOS device 10 includes a substrate 100, a dielectric layer 104a, a lower electrode BG1, a lower electrode BG2, an upper electrode TG1 and an upper electrode TG2, and further includes a dielectric layer 108a and a dielectric layer 108b. And at least one of the dielectric layers 112. The substrate 100 has a trench 102 having side walls SW1 and sidewalls SW2 opposite to each other. The dielectric layer 104a is disposed on the surface of the trench 102, and the top of the dielectric layer 104a is lower than the top of the trench 102. The lower electrode BG1 is disposed on the dielectric layer 104a on the side wall SW1, and the lower electrode BG2 is disposed on the dielectric layer 104a on the side wall SW2. The upper electrode TG1 is disposed on the sidewall SW1 above the dielectric layer 104a, and the upper electrode TG2 is disposed on the sidewall SW2 above the dielectric layer 104a. The dielectric layer 108a is disposed between the upper electrode TG1 and the substrate 100, the dielectric layer 108b is disposed between the upper electrode TG2 and the substrate 100, and the dielectric layer 108a and the dielectric layer 108b extend to the top surface of the substrate 100, respectively. . The lower electrode BG1, the lower electrode BG2, the upper electrode TG1, the upper electrode TG2, and the substrate 100 are electrically insulated from each other in the trench 102 by the dielectric layer 104a, the dielectric layer 108a, and the dielectric layer 108b. The dielectric layer 112 fills the trench 102 and covers the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode TG2.

Further, materials, formation methods, effects, and the like of the respective members in the trench oxynitride device 10 have been described in detail in the above embodiments, and thus the description thereof will not be repeated.

According to the above embodiment, in the trench MOS device 10 and the method of manufacturing the same, the lower electrode BG1, the lower electrode BG2, the upper electrode TG1, and the upper electrode TG2 may be provided in the same trench 102, that is, The same trench 102 can have two sets of shielding gates and two sets of channel gates, thereby effectively reducing the number of processes and reducing manufacturing costs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Grooved MOS components

100‧‧‧Base

102‧‧‧ trench

104‧‧‧ dielectric material layer

104a, 108a, 108b, 112‧‧‧ dielectric layer

106‧‧‧Photoresist layer

106a‧‧‧ photoresist layer

110‧‧‧electrode material layer

BG1, BG2‧‧‧ lower electrode

TG1, TG2‧‧‧ upper electrode

SW1, SW2‧‧‧ side wall

1A to 1G are cross-sectional views showing a manufacturing process of a trench MOS device according to an embodiment of the present invention.

Claims (11)

A trench MOS device, comprising: a substrate having a trench, and the trench has first and second sidewalls opposite to each other; a first dielectric layer disposed on a surface of the trench, wherein a top of the first dielectric layer is lower than a top of the trench; a first lower electrode is disposed on the first dielectric layer on the first sidewall; a second lower electrode is disposed On the first dielectric layer on the second sidewall; a first upper electrode disposed on the first sidewall above the first dielectric layer; and a second upper electrode disposed on On the second sidewall above the first dielectric layer, wherein the first lower electrode, the second lower electrode, the first upper electrode, the second upper electrode, and the substrate are The trenches are electrically insulated from one another. The trench MOS device of claim 1, further comprising: a second dielectric layer disposed between the first upper electrode and the substrate; and a third dielectric layer disposed on Between the second upper electrode and the substrate. The trench MOS device of claim 2, wherein the second dielectric layer and the third dielectric layer respectively extend to a top surface of the substrate. The trench MOS device of claim 1, further comprising a fourth dielectric layer, wherein the fourth dielectric layer fills the trench and covers the first lower electrode And the second lower electrode, the first upper electrode, and the second upper electrode. A method of fabricating a trench MOS device, comprising: providing a substrate having a trench, and the trench has first and second sidewalls opposite to each other; forming a first dielectric on a surface of the trench An electrical layer, wherein a top of the first dielectric layer is lower than a top of the trench; a first lower electrode is formed on the first dielectric layer on the first sidewall; Forming a second lower electrode on the first dielectric layer on the second sidewall; forming a first upper electrode on the first sidewall above the first dielectric layer; and Forming a second upper electrode on the second sidewall above the electrical layer, wherein the first lower electrode, the second lower electrode, the first upper electrode, the second upper electrode, and the substrate are The trenches are electrically insulated from one another. The method for fabricating a trench MOS device according to claim 5, wherein the method for forming the first dielectric layer comprises: forming a conformal first dielectric material layer in the trench; Forming a photoresist layer on the first dielectric material layer, wherein a top of the photoresist layer is lower than a top of the trench; and removing the first dielectric not covered by the photoresist layer Electrical material layer. The method for fabricating a trench MOS device according to claim 6, wherein the method for forming the photoresist layer comprises: forming light filling the trench on the first dielectric material layer a resistive material layer; and an etch back process for the photoresist material layer. The method of manufacturing a trench MOS device according to claim 5, wherein the first lower electrode, the second lower electrode, the first upper electrode, and the second upper electrode are The forming method includes: forming an electrode material layer conformally on the first sidewall above the first dielectric layer and the second sidewall on the first dielectric layer; and the electrode material The layer is subjected to an etch back process. The method for fabricating a trench MOS device according to claim 5, further comprising: forming a second dielectric layer between the first upper electrode and the substrate; and the second upper portion A third dielectric layer is formed between the electrode and the substrate. The method of fabricating a trench MOS device according to claim 9, wherein the second dielectric layer and the third dielectric layer are formed on a top surface of the substrate. The method for fabricating a trench MOS device according to claim 5, further comprising forming a fourth dielectric layer filling the trench, wherein the fourth dielectric layer covers the first lower layer a portion electrode, the second lower electrode, the first upper electrode, and the second upper electrode.