TW201926349A - Program flow control method and memory verification method - Google Patents

Abstract

A program flow control method/a memory verification method is provided to combine a soft program algorithm and a normal program algorithm together to save the testing time in ROM and program/erase time in Flash. In the proposed method(s), an S (soft program) state is programmed with other states during a program period to save the time of soft program.

Description

Write process control method and method of verifying memory

The present invention relates to a write flow control method and/or a method for verifying a memory, and more particularly to a write flow control method including a soft write algorithm and a normal write algorithm having a complex state and/or a The method of verifying the memory.

If the threshold voltage (Vth) of the memory cell becomes too low after erasing, there is a problem of "hole migration", which is too low for Vth to make adjacent cells (near neighbors) The Vth of the same word line WL becomes lower, resulting in a "data retention" problem.

Traditionally, a soft program is used to make this too low Vth go high. It is known to those skilled in the art that: 1. The strength of the verify voltage applied by the soft write is lower than the strength of the write voltage applied by the normal program; 2. The purpose of soft write is to converge Data, such that the Vth of the memory cell is lower than the lower bound of the soft program verify voltage (SPV), and can be converged to the defined distribution due to the Vth being boosted. Within (distribution).

The first figure is a schematic diagram of the distribution definition of a conventional multi-level cell (MLC) Vth in a normal write algorithm. In the first figure, the horizontal axis is the Vth value, and its value increases from left to right. EV stands for Erase Verify status. A, B, and C are the three states of the normal write algorithm. In the first figure, when writing normally, only the A, B, C states are written. The heights of the states EV, A, B, and C perpendicular to the horizontal axis direction represent the number of memory cells having the Vth value. 11, 10, 00 and 01 are the logical bit values of the states of EV, A, B, C, and the like.

The second figure is a schematic diagram showing the distribution definition of a conventional multi-level cell Vth in a soft write algorithm. In the EV state, only the Vth value of the memory cell is lower than the soft write verify voltage, so that the Vth that is too low is raised to be greater than or equal to the SPV value. As shown in the first and second figures, in the conventional write algorithm, soft writes are executed first, and then the normal write A, B, and C states are sequentially executed. Soft write is generally followed by erasing, avoiding over erase, which writes data.

However, increasing the soft write algorithm wastes the test time in the read-only memory (ROM) and the program/erase time in the flash memory.

As a result of the job, the inventor, in view of the lack of prior art, thought of and improved the idea of invention, and finally invented the "writing process control method and method of verifying memory" in this case.

The main purpose of the present invention is to provide a method for writing a flow control method/verification memory to combine a soft write algorithm and a normal write algorithm to save one test time in a read-only memory with a fast One of the flash memory write/erase times. In the proposed method, the sensed data used for soft writes and the test data used for normal writes are combined to write their indices, and a soft write state will be along with other states during a write. Write to save time on soft writes.

Another main object of the present invention is to provide a program flow control method for a multi-layer cell having a plurality of memory cells, comprising: providing a soft write for boosting a threshold voltage of each of the memory cells a soft program and a normal program having a complex state; reading the corresponding sensing data of the threshold voltage of each of the memory cells and each corresponding test data of each of the complex states; The soft write verification and save each of the sensing data to determine whether each threshold voltage of each of the memory cells is lower than a predetermined value; combining each of the sensing data and each of the test data to write An indicator; using the soft write to increase each threshold voltage of each of the memory cells below the predetermined value, simultaneously writing each of the complex states and testing with each of the test data; and when the soft write At the end of the operation, if each of the plural states has not been completed, the process proceeds to the end.

Another main object of the present invention is to provide a write flow control method for a multi-layer cell having a plurality of memory cells, comprising: providing a soft write and a function for boosting a threshold voltage of each of the memory cells Normal writing of the complex state; verifying and storing the corresponding sensing data of the threshold voltage of each memory cell by the soft writing, and determining whether the threshold voltage of each memory cell is lower than a predetermined value; Using the soft write to raise each threshold voltage of each of the memory cells below the predetermined value, and simultaneously writing each of the complex states and testing corresponding test data of each of the complex states; and when the soft At the end of the write operation, if each of the plural states has not been completed, the process proceeds to the end.

A main object of the present invention is to provide a write flow control method for a multi-layer cell having a plurality of memory cells, comprising: providing a soft write and a threshold for boosting a threshold voltage of each of the memory cells Normal writing of a complex state; using the soft write to raise each threshold voltage of each memory cell below a predetermined value, and simultaneously writing each of the complex state and the corresponding test data of each of the complex states The test is performed; and when the soft write operation ends, if each of the plural states has not been completed, the process continues to the end.

A further main object of the present invention is to provide a write flow control method for a multi-level cell having a plurality of memory cells, comprising: providing a soft write state and a complex state, wherein the soft write state uses a boost a soft write of a threshold voltage of the memory cell, and the complex state is included in a normal write; writing the soft write state to find a sensed value of each threshold voltage of each of the memory cells is lower than And a predetermined value is raised to the predetermined value, the complex state of the normal write is synchronously written, and each corresponding test data of each of the complex states is verified; and when the soft write operation ends, each When the plural state has not been completed, it continues to its end.

Another main object of the present invention is to provide a method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a gate voltage, an erase state, and at least a information storage threshold voltage and at least one information storage state, comprising: writing each erase state in a soft write, and writing each information storage state in a normal write; detecting each of the memory cells Erasing the threshold voltage is lower than the soft write verify voltage; and if so, increasing the erase threshold voltage and the at least one information storage threshold voltage by a certain amount of voltage, so that the erase threshold voltage is higher than the soft write verify voltage .

Another main object of the present invention is to provide a method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a gate voltage, an erase state, and at least a information storage threshold voltage and at least one information storage state, comprising: writing each erase state and each information storage state by a unified program; detecting whether the erase threshold voltage of each of the memory cells is lower than the soft Writing a verify voltage; and if so, increasing the erase threshold voltage and the at least one information storage threshold voltage by a voltage amount such that the erase threshold voltage is higher than the soft write verify voltage.

A main object of the present invention is to provide a method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a gate voltage, an erase state, and at least The information storage threshold voltage and the at least one information storage state include: distinguishing the verification method into a fast phase, a test data time, and a slow phase; Writing to each of the erased state and the fast phase; detecting whether the erase threshold voltage of each of the memory cells is lower than the soft write verify voltage; and if so, increasing the erase threshold voltage by a certain amount of voltage and At least one information stores the threshold voltage such that the erase threshold voltage is higher than the soft write verify voltage.

The above described objects, features, and advantages of the present invention will become more apparent and understood.

The third figure is a schematic diagram showing the distribution definition of the Vth of a multi-layer cell in accordance with a preferred embodiment of the present invention in the proposed write algorithm. In the proposed write algorithm of the present invention, there is a new soft program state.

As shown in the third figure, the write algorithm proposed by the present invention includes: (1) soft write verification (SPV) and retention sensing data; (2) writing a page data into a page buffer; (3) Combine the data obtained by the SPV with the test data contained in the page data; (4) Perform the writing. That is, the proposed write algorithm includes: verifying and storing each of the sensing data by the soft write, and determining whether each threshold voltage of each of the memory cells is lower than a predetermined value; Sensing data and each of the test data to write its index; and using the soft write to raise each threshold voltage of each of the memory cells below the predetermined value, and simultaneously writing each of the complex states and Test with each test data.

In the third figure, the 0 on the left side of the line indicating the SPV is a logical bit value, indicating that the Vth of the memory cell having the value is lower than SPV, and needs to be soft-written to increase its Vth value; The 1 on the right side of the straight line indicating the SPV is also a logical bit value, indicating that the Vth of the memory cell having the value is not lower than the SPV and does not need to be written.

The fourth diagram (a) is a diagram showing a write algorithm according to a preferred embodiment of the present invention. When the S state is written, the A, B, and C states are also simultaneously written. As shown in the fourth figure (a), in the initial Vth distribution definition, after the page data is written and verified by the "soft write verify voltage" SPV, the page buffer will calculate each of the sensed data. Each threshold voltage of the memory unit is lower than the predetermined value to obtain a set of soft write data (SPGM data); the soft write includes a soft write state S and a soft write phase (SPGM phase) And in the soft write phase, the soft write data is written according to the set to write the soft write state S and the synchronous write A, B, C state. The set of soft write data is a data set formed by each of the memory cells having a logical bit value of 0 in the third figure.

The fourth diagram (b) is a diagram showing a write algorithm according to a preferred embodiment of the present invention. When the S state verification is completed, the A, B, and C states are still continuously written. As shown in the fourth diagram (b), after the soft write phase, each of the A, B, C states is still written to reduce subsequent write times. In the fourth figure (b), after the soft write phase is completed, each of the A, B, C states can save incremental step pulse programming (ISPP) information, or reset the ISPP information. .

The fifth figure is a flow chart showing a write algorithm in accordance with a preferred embodiment of the present invention. The write process in Figure 5 combines soft writes with normal writes. As shown in the fifth figure, the flow chart includes: 1. write start; 2. write page data; 3. SPV; 4. soft write completion?; if not, then 5.S, A, B, C write; if yes, 6.A, B, C write; 7.PVA, PVB, PVC (slightly PV algorithm); 8.PVA, B, C are completed? If not, then 6.S, A, B, C are written; if yes, then 9. Write is terminated. In the fifth figure, the 3.SPV (soft write verification) step includes: (1) finding out that each threshold voltage of each of the memory cells is lower than the predetermined value, and (2) lifting each by soft write Each of the threshold voltages of the memory unit is lower than the predetermined value. The steps of 7.PVA, PVB, PVC (slightly PV algorithm) include: (1) verifying A, B, C state (PVA, PVB, PVC) with test data, and then entering 8.PVA, B, C is complete? Step; or (2) skipping the entire PV algorithm, then it will be completed by 8.PVA, B, C? Step, and enter 9. Write termination step.

When the present invention is applied to a ROM, two-stage writing is used. As previously mentioned, the write algorithm proposed by the present invention includes soft write and normal write. The normal write includes a first stage write and a second stage write, the first stage write includes performing a fast program and verifying a set of corresponding tester data, the second Stage writing includes performing a slow progam and verifying the corresponding test data for the group. The test time of the set corresponding to the test data is longer than a first write time at which the fast write is performed, but shorter than a second write time at which the slow write is performed. Therefore, the soft write and the first stage write can be combined and executed simultaneously. However, since the test time is longer than the first write time, the soft write is performed synchronously with the first stage write without increasing the time required for the first stage write. As a result, when WS (Wafer Sort) or FT (Final Testing), performing soft writes will not require extra time.

The write algorithm proposed by the present invention can also be applied to flash memory. The flash memory includes a controller and the control method is performed by the controller.

In summary, the present invention provides a method for writing a flow control method/verifying memory to combine a soft write algorithm and a normal write algorithm to save one test time in a read-only memory. One of the flash memory write/erase times. In the proposed method, the sensed data used for soft writes and the test data used for normal writes are combined to write their indices, and a soft write state will be along with other states during a write. Write to save time in soft writing, so it is indeed progressive and novel.

Therefore, even though the present invention has been described in detail by the above-described embodiments, it can be modified by those skilled in the art, and is not intended to be protected as claimed.

0, 1, 11, 10, 00, 01‧‧‧ logical bit values

SPV‧‧‧Soft Write Verification Voltage

S‧‧‧soft write status

A, B, C‧‧‧Normal write status

First Figure: A schematic diagram showing the distribution definition of a conventional multi-level cell Vth in a normal write algorithm. Second: It is a schematic diagram showing the distribution definition of a conventional multi-level cell Vth in a soft write algorithm. Third Figure: A schematic diagram showing the distribution of the Vth of a multi-layer cell in accordance with a preferred embodiment of the present invention in the proposed write algorithm. Fourth Figure (a): This shows a schematic diagram of a write algorithm in accordance with a preferred embodiment of the present invention. When the S state is written, the A, B, and C states are also simultaneously written. Fourth Figure (b): This shows a schematic diagram of a write algorithm in accordance with a preferred embodiment of the present invention. When the S-state verification is completed, the A, B, and C states are still continuously written. Fifth Figure: A flowchart showing a write algorithm in accordance with a preferred embodiment of the present invention.

Claims (10)

A program flow control method for a multi-layer cell having a plurality of memory cells, comprising: providing a soft program for boosting a threshold voltage of each of the memory cells and having a normal program of the complex state; reading each corresponding sensing data of the threshold voltage of each of the memory cells and each corresponding test data of each of the complex states; verifying and saving each by the soft write The sensing data is used to know whether each threshold voltage of each of the memory cells is lower than a predetermined value; combining each of the sensing data and each of the test data to write its index; using the soft write to Elevating each threshold voltage of each of the memory cells below the predetermined value, simultaneously writing each of the complex states simultaneously and testing with each test data; and when the soft write operation ends, such as the plural When the status has not been completed, it continues to its end. The method of claim 1, wherein the step of verifying and saving each of the sensing data by the soft writing further comprises: writing a page data to a page buffer, wherein each of the test data is included in the page data. The step of combining the sensing data and each of the test data to write the index further includes: the page buffer calculating, according to each of the sensing data, each threshold voltage of each of the memory cells being lower than the predetermined value Obtaining a set of soft write data; the soft write includes a soft write state and a soft write phase, and the using the soft write step further comprises: according to the set of soft writes during the soft write phase Data is written to the soft write state. A write flow control method for a multi-level cell having a plurality of memory cells, comprising: providing a soft write for boosting a threshold voltage of each of the memory cells and a normal write having a complex state; The soft write verification and storing the corresponding sensing data of the threshold voltage of each memory unit, and determining whether the threshold voltage of each memory unit is lower than a predetermined value; using the soft write to enhance each Each threshold voltage of the memory unit is lower than the predetermined value, and simultaneously written to each of the complex states and tested by corresponding test data of each of the complex states; and when the soft write operation ends, such as When the plural state has not been completed, it continues to its end. A write flow control method for a multi-level cell having a plurality of memory cells, comprising: providing a soft write for boosting a threshold voltage of each of the memory cells and a normal write having a complex state; The soft write is performed to raise each threshold voltage of each of the memory cells below a predetermined value, and simultaneously write each of the complex states and test corresponding test data of each of the complex states; and when the soft write At the end of the operation, if the plural status has not yet been completed, it will continue until the end. A write flow control method for a multi-level cell having a plurality of memory cells, comprising: providing a soft write state and a complex state, wherein the soft write state uses a threshold voltage for boosting each of the memory cells Soft writing, and the complex state is included in a normal write; writing the soft write state to find that a sensed value of each threshold voltage of each memory cell is lower than a predetermined value and is raised to the a predetermined value, synchronously writing each of the plural states of the normal write and verifying each of the corresponding test data of each of the complex states; and when the soft write operation ends, if each of the complex states has not been operated yet, Then proceed to the end. The method of claim 5, wherein the multi-layer unit is a read-only memory (ROM) or a flash memory (Flash), and the step of providing a soft write state and a complex state includes: writing Entering a page data, wherein the page data includes each of the corresponding test data, and the page data is written into a page buffer; the step of writing the soft write state further comprises: verifying each of the corresponding test data The plural state or the verification of each of the plurality of states corresponding to the test data; wherein when the multi-layer cell is the read-only memory, the normal write includes a first-stage write and a second-stage write, The first stage of writing includes performing a fast write and verifying a set of corresponding test data, and the second stage of writing comprises performing a slow write and verifying the set of corresponding test data, wherein the test time of the set of corresponding test data is longer than Performing a first write time of the fast write, but shorter than a second write time of performing the slow write, and the step of writing the soft write state further comprises: performing the write synchronously Write status Writing with the first stage such that the writing to the soft write state is shorter than the sum of the first write time and the test time; wherein when the multi-layer unit is the flash memory, the fast The flash memory includes a controller, and the control method is executed by the controller. A method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a erase threshold voltage, an erase state, at least one information storage threshold voltage, and at least one The information storage state includes: writing each erase state with a soft write, and writing each of the information save states with a normal write; detecting whether the erase threshold voltage of each of the memory cells is lower than the Soft writing the verify voltage; and if so, increasing the erase threshold voltage and the at least one information storage threshold voltage by a certain amount of voltage such that the erase threshold voltage is higher than the soft write verify voltage. The method of claim 7, wherein each of the memory units further includes at least one information storage verification voltage, and the verification method ends when the at least one information storage threshold voltage is higher than the at least one information storage verification voltage . A method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a erase threshold voltage, an erase state, at least one information storage threshold voltage, and at least one The information storage state includes: writing, by a unified program, each of the erased state and each of the information storage states; detecting whether the erase threshold voltage of each of the memory cells is lower than the soft write verification voltage; and if so, The erase threshold voltage and the at least one information storage threshold voltage are increased by a certain amount of voltage such that the erase threshold voltage is higher than the soft write verify voltage. A method for verifying a memory, wherein the memory has a soft write verify voltage and a plurality of memory cells, and each of the memory cells has a erase threshold voltage, an erase state, at least one information storage threshold voltage, and at least one The information storage state includes: distinguishing the verification method into a fast phase, a tester data time, and a slow phase; writing the erased state in a combination program and The fast phase; detecting whether the erase threshold voltage of each of the memory cells is lower than the soft write verify voltage; and if so, increasing the erase threshold voltage and the at least one information storage threshold voltage by a certain amount of voltage, so that The erase threshold voltage is higher than the soft write verify voltage.