TW201917591A - Storage device and interface chip thereof - Google Patents

Abstract

A storage device and an interface chip thereof are provided, where the interface chip is applicable to the storage device. The interface chip includes a slave interface circuit, a master interface circuit, and a control circuit. The storage device includes a memory controller and a non-volatile (NV) memory, and the NV memory includes a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device includes the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.

Description

Storage device and its interface chip

The present invention relates to flash memory control, and more particularly to a storage device and its interface wafer.

With regard to the development of high-performance and high-endurance solid state drive (SSD) products such as enterprise-grade solid-state drives (enterprise SSD) products, some problems have arisen in the related art. For example, when trying to increase the storage capacity of an enterprise-class SSD by increasing the number of flash memory chips in an enterprise-class SSD, one of the enterprise-class SSDs is controlled. The throughput of one of the key data paths is greatly increased, but the controller's existing architecture cannot handle such a large throughput. Since the related art cannot simultaneously ensure both performance and reliability, there is a tradeoff between performance and reliability. For another example, an increase in the amount of calculation of the related data protection may cause the controller to be hot, so an additional heat dissipation mechanism needs to be provided to the controller, wherein the heat dissipation mechanism takes up extra space. Therefore, a novel architecture is needed to break through the bottleneck of the development of this type of storage device.

It is an object of the present invention to provide a storage device and an interface wafer thereof to solve the above problems.

Another object of the present invention is to provide a storage device and an interface wafer thereof to maximize the storage capacity of the storage device while ensuring the performance and reliability of the storage device.

At least one embodiment of the present invention provides an interface wafer, wherein the interface wafer is applied to a storage device. The interface chip includes: a slave interface circuit; a master interface circuit; and a control circuit coupled between the slave interface circuit and the main interface circuit. The servant interface circuit can be used to couple the interface chip to a memory controller, wherein the storage device includes the memory controller and a non-volatile (NV) memory, and the non-volatile memory A plurality of non-volatile memory chips are included. The memory controller can access the non-volatile memory through the interface chip in response to a master device command from a host device, and the host device is located outside the storage device. The main interface circuit can be used to couple the interface chip to a set of non-volatile memory chips in the plurality of non-volatile memory chips, wherein a hierarchical structure of the storage device includes the memory A controller, the interface wafer, and the set of non-volatile memory chips. The control circuit can be used to control the operation of the interface chip, wherein the interface chip accesses the set of non-volatile memory chips for the memory controller under the control of the control circuit.

At least one embodiment of the present invention provides a storage device. The storage device includes: a non-volatile memory, wherein the non-volatile memory comprises a plurality of non-volatile memory chips; a memory controller; and a plurality of interface wafers coupled to the memory controller and Between the non-volatile memories. The non-volatile memory can be used to store information, and the memory controller can be used to control the operation of the storage device. In addition, any one of the plurality of interface wafers includes: a servant interface circuit; a main interface circuit; and a control circuit coupled between the servant interface circuit and the main interface circuit. The servant interface circuit can be configured to couple the interface chip to the memory controller, wherein the memory controller can access the non-volatile memory through the interface chip according to a main device command from a host device. And the main device is located outside the storage device. The main interface circuit can be used to couple the interface chip to a set of non-volatile memory chips in the plurality of non-volatile memory chips, wherein a hierarchical structure of the storage device includes the memory controller, The interface wafer and the set of non-volatile memory chips. The control circuit can be used to control the operation of the interface chip, wherein the interface chip accesses the set of non-volatile memory chips for the memory controller under the control of the control circuit.

At least one embodiment of the present invention provides an interface wafer, wherein the interface wafer is applied to a storage device. The interface chip includes: a servant interface circuit; a plurality of bypass interface circuits; and a control circuit coupled between the servant interface circuit and the plurality of bypass interface circuits. The servant interface circuit can be used to couple the interface chip to a memory controller, wherein the storage device includes the memory controller and a non-volatile memory, and the non-volatile memory includes a plurality of non-volatile memories Body wafer. The memory controller can access the non-volatile memory through the interface chip in response to a master device command from a host device, and the host device is located outside the storage device. The plurality of interface chips are respectively coupled to the plurality of other interface chips in the storage device, wherein the plurality of other interface chips are respectively coupled to the plurality of non-volatile memory chips A complex array of non-volatile memory chips. The control circuit can be used to control the operation of the interface chip, wherein the interface chip bypasses at least one of the command and the data between the memory controller and the plurality of other interface chips under the control of the control circuit And accessing the complex array non-volatile memory chip to the memory controller through the plurality of other interface chips.

At least one embodiment of the present invention provides a storage device. The storage device includes: a non-volatile memory, wherein the non-volatile memory comprises a plurality of non-volatile memory chips; a memory controller; and a plurality of interface wafers coupled to the memory controller and Between the non-volatile memories, the plurality of interface wafers comprise a plurality of first layer interface wafers and a plurality of second layer interface wafers. The non-volatile memory can be used to store information, and the memory controller can be used to control the operation of the storage device. In addition, any one of the plurality of first-layer interface wafers includes: a servant interface circuit; a plurality of bypass interface circuits; and a control circuit coupled to the servant interface circuit and the plurality of bypass interface circuits between. The servant interface circuit can be configured to couple the interface chip to the memory controller, wherein the memory controller can access the non-volatile memory through the interface chip according to a main device command from a host device. And the main device is located outside the storage device. The plurality of bypass interface circuits can be used to couple the interface wafers to a plurality of other interface wafers, wherein the plurality of other interface wafers are a set of second layer interface wafers of the plurality of second layer interface wafers, and The plurality of other interface chips are respectively coupled to the plurality of non-volatile memory chips in the plurality of non-volatile memory chips. The control circuit can be used to control the operation of the interface chip, wherein the interface chip bypasses at least one of the command and the data between the memory controller and the plurality of other interface chips under the control of the control circuit And accessing the complex array non-volatile memory chip to the memory controller through the plurality of other interface chips.

One of the advantages of the present invention is that the interface wafer of the present invention can increase the storage capacity of the storage device and avoid various problems in the related art. In addition, the interface wafer of the present invention can ensure the performance and reliability of the storage device. In addition, the interface wafer and the storage device of the present invention can perform multi-layer data protection to effectively reduce the uncorrectable bit error rate (UBER) of the storage device.

In the related art, the word "chip" may represent a bare die or represent at least one die protected within a package. For ease of understanding, the term "wafer" in the present invention may mean a die of an integrated circuit ("IC"). For example, the term "non-volatile (NV) memory chip" can represent the grain of a non-volatile memory IC. For another example, the word "flash chip" can represent the die of a flash memory IC. For another example, the term "interface wafer" can refer to a die that interfacing the IC. In accordance with certain embodiments, one or more wafers, such as one or more dies, may be disposed in one package.

1 is a schematic diagram of a storage device 100 in accordance with an embodiment of the present invention. For example, the storage device 100 can be a solid state drive (SSD), such as an enterprise-class solid state drive (enterprise SSD). As shown in FIG. 1, the storage device 100 includes a dynamic random access memory (DRAM) 105, a memory controller 110, an interface chipset 120, and a non-volatile memory (abbreviated as "NV memory") 130. The memory controller 110 includes a microprocessor 110P, an interface circuit 112, a data buffer 114, at least one other buffer 115, and an access circuit 116. The access circuit 116 can include a plurality of sub-circuits. For example, a read channel circuit 116R and a write channel circuit 116W (labeled as "read channel" and "write channel" in FIG. 1 respectively). Microprocessor 110P can control various components in memory controller 110, such as interface circuitry 112, data buffer 114, other buffers 115, and access circuitry 116. The interface chipset 120 includes interface wafers 122-1, 122-2, ..., and 122-N, and the NV memory 130 includes a plurality of NV memory chips, such as a plurality of flash memory chips, which may be referred to as fast A flash wafer in which the symbol "N" can represent a positive integer greater than one. For example: N = 16; another example: N = 8; again, for example, N may be equal to other values as long as it does not interfere with the implementation of the invention.

According to the embodiment, the NV memory 130 (eg, the NV memory chips such as the flash chips) can be used to store information, and the memory controller 110 can be used to control the operation of the storage device 100. In addition, the interface chips 122-1, 122-2, ..., and 122-N can access the NV memory chips such as the flash chips for the memory controller 110, respectively, and perform error correction. Data errors have been corrected before data is transferred from one or more of the flash wafers to the memory controller 110. Therefore, the interface chipset 120 can control the NV memory 130 to provide a plurality of error free modules 150-1, 150-2, ... and 150-N to the memory controller 110, wherein the errorless module 150 Any one of the -1, 150-2, ..., and 150-N modules 150-n can provide error-free data to the memory controller 110, and the symbol "n" can represent the falling interval [1, N] Positive integer. According to the embodiment, the error-free module 150-1 includes an interface chip 122-1 and a plurality of flash chips coupled to the interface chip 122-1. The error-free module 150-2 includes 122-2 and is coupled to 122-2. A plurality of flash chips, and so on; and the error-free module 150-N includes 122-N and a plurality of flash chips coupled to 122-N.

Based on the architecture shown in FIG. 1, a hierarchical architecture in the storage device 100 includes a memory controller 110, interface chips {122-1, 122-2, ..., 122-N}, and an error-free module {150. The flash chips in -1, 150-2, ..., 150-N}. Additionally, the storage device 100 can be coupled to a host device; the host device (not shown) is external to the storage device 100. The memory controller 110 can access the NV memory through any one of the interface chips 122-1, 122-2, ..., and 122-N via the interface chip 122-n in response to a master command from the host device. 130. For example, the primary device can be a server, such as a storage server, wherein the storage device 100 can be considered as one of the storage systems. In addition, when the primary device accesses the storage device 100, the primary device can transmit a logical address to the storage device 100 to indicate the data to be accessed by the primary device. The memory controller 110 can convert the logical address of the primary device into a physical address, and then transfer the physical address to the interface chip 122-n to access the data in the NV memory 130. In addition, the memory controller 110 may be provided with an encoding and decoding function of a Cyclic Redundancy Check Code (CRC code), and may perform cyclic redundancy check code encoding when needed. / Decode operation to check the correctness of the data.

FIG. 2 is a diagram showing the implementation details of the storage device 100 shown in FIG. 1 in an embodiment. According to the embodiment, the error-free modules 150-1, 150-2, ..., and 150-N can be respectively implemented with the packaged error-free modules 250-1, 250-2, ..., and 250-N. For ease of understanding, the bases 252-1, 252-2, ..., and 252-N of the packages are respectively shown below the flash wafers. A wafer stack formed by a plurality of flash wafers may be disposed on any of the pedestals 252-1, 252-2, ..., and 252-N, and the wafer stack is disposed in the wafer stack Each of the flash wafers can be coupled to the interface wafer 122-n by wire/wiring bonding. For example, the wafer stack can contain 16 flash wafers. As another example, the wafer stack can include 8 flash wafers, or other number of flash wafers. When desired, the interface chip 122-n can utilize a chip enable (CE) signal to control whether a flash chip is enabled. Under the control of the memory controller 110, the storage device 100 may have a plurality of channels, such as N channels Ch(0), Ch(1), ..., and Ch(N-1), wherein each channel may be provided An error-free module. For channel Ch(n-1), memory controller 110 can access any of the wafer stacks on pedestal 252-n through interface wafer 122-n. For example, in the case where N=16 and the wafer stack contains 16 flash wafers, the memory controller 110 can access 256 flash wafers through the interface wafer set 120. Please note that the architecture of these error-free modules can be changed. In accordance with certain embodiments, a plurality of interface wafers can be disposed within a package. For example, one of the wafer stacks on the base of the package can include eight flash wafers, and two interface wafers can be disposed on the base. The two interface wafers can be respectively coupled to the upper four flash chips and the lower four flash chips in the wafer stack, and the memory controller 110 can access the wafer stack through the two interface wafers, respectively. According to some embodiments, each of the plurality of channels may correspond to a plurality of interface wafers. For example, the value N can be a multiple of the channel count of the plurality of channels.

The interface wafer of the present invention can reduce channel capacitance compared to related art. For example, in the related art, due to the higher channel capacitance, it can only be limited to 8 flash chips per channel, and the typical channel capacitance can reach 20 pF (picofarad). Based on the architecture of the present invention, 32 flash wafers per channel can be achieved with a typical channel capacitance of approximately 5 pF.

According to some embodiments, a plurality of wafer stacks and a plurality of interface wafers may be disposed in one package, and each of the wafer stacks includes a plurality of flash wafers, wherein one of the interface wafers may be separately coupled The other of the interface wafers can be coupled between the memory controller 110 and the portion of the interface wafer. Under the control of the memory controller 110, the storage device 100 can have N channels Ch(0), Ch(1), ..., and Ch(N-1), wherein all of the flash wafers in this package can be The operation is performed on any one of the N channels, and the other interface chip can access the flash chips on the channel through the partial interface chip for the memory controller 110.

3 is a schematic diagram of an interface wafer 300 according to an embodiment of the invention, wherein the interface wafer 300 can be applied to the storage device 100 shown in FIG. The interface wafer 300 can be used as an example of any one of the interface wafers {122-1, 122-2, ..., 122-N}, and the interface wafer 300 can be coupled to the plurality of NV memory chips. A set of NV memory chips, such as the flash chips in the error-free module 150-n. Thus, the hierarchical architecture can include a memory controller 110, an interface wafer 300, and the set of NV memory chips. For ease of understanding, in the case where the interface wafer 112-n is implemented as the interface wafer 300, other wafers other than the interface wafer 112-n among the interface wafers {122-1, 122-2, ..., 122-N} may be implemented. It has the same circuit architecture as the interface wafer 300. For example, the interface wafers {122-1, 122-2, ..., 122-N} may be products of the same type, such as products having the same circuit design and produced under the same process and the same conditions; these products may be regarded as identical products to each other. , which ignores the possible small differences between these products (due to process and other factors). Assuming that the interface wafer 300 represents one of a plurality of interface wafers {300}, and the plurality of interface wafers {300} represent products of the same model, the plurality of interface wafers {300} can be used as the interface wafer {122-1, An example of 122-2, ..., 122-N}. In addition to the memory controller 110, the interface chip 300, and the set of NV memory chips, the hierarchical architecture may further include a plurality of other interface chips in the plurality of interface wafers {300}, and further include the plurality of NV memories. Other sets of NV memory chips in the wafer, such as the flash chips in other error-free modules in the uncorrected modules {150-1, 150-2, ..., 150-N}, wherein the plurality of other interface chips They can be coupled between the memory controller 110 and the other sets of NV memory chips, respectively.

As shown in FIG. 3, the interface chip 300 includes a slave interface circuit 310, a control circuit 320, a master interface circuit 330, and M bypass interface circuits {340-1, 340- 2, ..., 340-M}, where the symbol "M" can represent a positive integer greater than one. The control circuit 320 is coupled between the servant interface circuit 310 and the main interface circuit 330 to manage a plurality of instruction paths and data paths between the servant interface circuit 310 and the main interface circuit 330, such as shaded in FIG. 6 vertical paths. The servant interface circuit 310 includes a parallel interface circuit 310P and a serial interface circuit 310S, and the serial interface circuit 310S can be a Serializer/Deserializer (SerDesializer) circuit. In addition, the control circuit 320 includes a sequence-by-parallel controller 321, an instruction converter 322, an instruction buffer 323, a Cyclic Redundancy Check Circuit ("CRC circuit") 320CRC, a data The buffer 326, an error correction code circuit (Error Correction Code circuit (referred to as "ECC circuit") 320ECC and a bypass mode control circuit 329, wherein the CRC circuit 320CRC includes a check circuit 324 and a re-encoding circuit 325, ECC circuit 320ECC An encoder 327 and a decoder 328 are included, and the bypass mode control circuit 329 includes a repeater 329R and a switching circuit 329SW. The sequence-to-parallel controller 321 controls the conversion operation between the sequence data and the parallel data. The instruction buffer 323 can be used to buffer instructions from the memory controller 110, and the instruction converter 322 can convert the instructions or respond to the memory controller 110 as needed. The data buffer 326 can be used to buffer data, and the CRC circuit 320CRC and the ECC circuit 320ECC can perform operations on data protection. The bypass mode control circuit 329 can control the operation of the data/instruction bypass. Based on these mechanisms, the interface wafer 300 can manage the set of NV memory chips in response to a request from the memory controller 110.

According to the present embodiment, the servant interface circuit 310 can be used to couple the interface chip 300 to the memory controller 110, and the main interface circuit 330 can be used to couple the interface chip 300 to the set of NV memory chips, such as the error-free module 150. The flash chips in -n. Control circuit 320 can control the operation of interface wafer 300. Under the control of the control circuit 320, the interface chip 300 can access the set of NV memory chips for the memory controller 110. For example, when the memory controller 110 has the capability of parallel transmission, the interface chip 300 can communicate with the memory controller 110 through the parallel interface circuit 310P. Two of the six longitudinal paths pass through the parallel interface circuit 310P, the CRC circuit 320CRC, and the ECC circuit 320ECC, and the downward and upward paths of the two paths correspond to the write operation and the read operation, respectively. For another example, when the memory controller 110 has the capability of serial transmission, the interface chip 300 can communicate with the memory controller 110 through the serial interface circuit 310S. Two of the six longitudinal paths pass through the sequence interface circuit 310S, the CRC circuit 320CRC, and the ECC circuit 320ECC, and the downward and upward paths of the two paths correspond to the write operation and the read operation, respectively. The data from the memory controller 110 can be a serial transmission of data. The sequence interface circuit 310S (eg, the sequencer/de sequencer circuit) can deserialize the sequence transmission data for use by the interface wafer 300 and serialize the parallel transmission data in the interface wafer 300. (serialization) operates for transmission to the memory controller 110.

In addition, the ECC circuit 320ECC can perform an operation related to an error correction code (ECC-related operation), wherein the control circuit 320 can perform the operation of the error correction code for the memory controller 110 by using the ECC circuit 320ECC to correct at least a part of the data. error. The control circuit 320 (eg, the ECC circuit 320ECC) can perform soft decoding, hard decoding, error recovery control, read error handling, and Read at least a portion of operations such as read retry, threshold voltage tracking ("Vth Tracking"), etc., to obtain a correctable codeword for use when needed Correct the data error to obtain the correct information. According to the embodiment, the error correction code operation capability (ECC calculation capability) of the interface wafer 300 is higher than the error correction code operation capability of the memory controller 110. For example, the memory controller 110 can have the ability to detect and correct errors through error correction code operations, and the error bit count that the interface chip 300 can correct when performing error correction code operations is higher than the memory. The number of error bits that the body controller 110 can correct when performing an error correction code operation. For another example, the memory controller 110 can have the ability to detect errors through error correction code operations, rather than correcting errors through error correction code operations. The memory controller 110 can rely on the interface chip 300 for error correction. Ability. Regardless of whether the memory controller 110 has the ability to correct errors through error correction code operations, the control circuit 320 enables the interface wafer 300 and the set of NV memory chips (such as the error-free module 150-n by means of the ECC circuit 320ECC). The combination of flash chips) is like an error free NV memory chip set to the memory controller 110. According to some embodiments, the interface wafer 300 and the set of NV memory chips (such as the flash chips in the error-free module 150-n) may be located in a package. With the ECC circuit 320ECC, the interface wafer 300 encapsulates the package to the memory controller 110 as an error-free NV memory chip.

Please note that the architecture of the memory controller 110 can be varied, and the interface die 300 can be designed as a multi-function wafer to accommodate various possible variations in the architecture of the memory controller 110. For example, when the memory controller 110 transmits the data and the parity-check code of the data to the interface chip 300, the control circuit 320 can discard the parity code and utilize the ECC circuit 320ECC ( In particular, the encoder 327 therein generates a new parity code according to the data, and writes the data and the new parity code to the set of NV memory chips (such as the error-free module 150-n). At least one NV memory chip of the flash chips. For another example, when the memory controller 110 transmits the data to the interface chip 300, the control circuit 320 can generate a parity code according to the data by using the ECC circuit 320ECC (especially the encoder 327 therein), and the data is The parity code is written to at least one of the NV memory chips of the set of NV memory chips (such as the flash chips in the error-free module 150-n).

In addition, the CRC circuit 320CRC can perform a CRC-related operation, wherein the control circuit 320 can check the correctness of the data from the memory controller 110 using the CRC circuit 320CRC. For example, the master device command can write a command to a master device. According to the master write command, the memory controller 110 transmits the data and one of the data CRC codes to the interface chip 300. The CRC circuit 320 CRC (especially the inspection circuit 324 therein) may perform a cyclic redundancy check calculation on the data to produce a calculation result. When the calculation result is equivalent to the cyclic redundancy check code, the control circuit 320 can generate a parity code based on the data by using the ECC circuit 320ECC (especially the encoder 327 therein) and pass the main interface circuit 330 to the group. At least one NV memory chip of the NV memory chip (such as the flash chips in the error-free module 150-n) transmits a write command to write the data and the parity code to the at least one NV The memory chip; otherwise, the control circuit 320 can request the memory controller 110 to retransmit the data and the cyclic redundancy check code. For another example, the master device command can be a master device read command. Based on the master read command, the memory controller 110 requests the interface wafer 300 to perform a corresponding read operation. In the corresponding read operation, the control circuit 320 transmits the at least one NV memory chip of the set of NV memory chips (such as the flash chips in the error-free module 150-n) through the main interface circuit 330. And reading the instruction, so that the at least one NV memory chip transfers the read data corresponding to the read command and the parity code of the read data to the interface chip 300. The control circuit 320 can use the ECC circuit 320ECC (especially the decoder 328 therein) to correct any errors in the read data according to the read data and the parity code to obtain error-free data. The CRC circuit 320CRC (especially the re-encoding circuit 325 therein) may perform a cyclic redundancy check calculation on the error-free data to generate a cyclic redundancy check code to allow the memory controller 110 to obtain from the interface chip 300. The correctness of the error-free data is checked according to the cyclic redundancy check code (for example, when reading) the error-free data, wherein the cyclic redundancy check code ensures that the error-free data is correctly received. The memory controller 110 can check whether the error-free data is correctly received according to the cyclic redundancy check code. If there is an error, the memory controller 110 can retrieve (e.g., re-read) the error-free data and the cyclic redundancy check code from the interface wafer 300.

As previously described, the interface wafer 300 can be designed as the multi-function wafer. The control circuit 320 (eg, the bypass mode control circuit 329) is coupled between the slave interface circuit 310 and the M bypass interface circuits {340-1, 340-2, ..., 340-M} to control the interface chip. The operation of 300. In one of the bypass modes of the interface die 300, the bypass mode control circuit 329 can bypass the command and data through the corresponding bypass path, and the repeater 329R can amplify the signal strength on the bypass paths. For example, the right two of the six longitudinal paths pass through the parallel interface circuit 310P, the repeater 329R, and the main interface circuit 330, and the downward and upward paths of the two paths correspond to the write operation and the read, respectively. Take the operation, where these two paths can be used as examples of these bypass paths. For another example, the switching circuit 329SW can perform a switching operation to couple the bypass paths to any one of the M bypass interface circuits {340-1, 340-2, ..., 340-M}. 340-m, where the symbol "m" can represent a positive integer falling within the interval [1, M]. Thus, the bypass paths can pass through the parallel interface circuit 310P, the repeater 329R, the switching circuit 329SW, and the bypass interface circuit 340-m. Note that this bypass mode can also be applied to sequence transfers. For example, the bypass paths may pass through the sequence interface circuit 310S, the repeater 329R, and the main interface circuit 330. For another example, the bypass paths may pass through the sequence interface circuit 310S, the repeater 329R, the switching circuit 329SW, and the bypass interface circuit 340-m.

Under the control of the control circuit 320 (eg, the bypass mode control circuit 329), the interface chip 300 can bypass an instruction from the memory controller 110 to the NV memory in the set of NV memory chips in the bypass mode. a chip, and bypassing the data in the bypass mode (eg, bypassing data from the memory controller 110 to the NV memory chip in one of the writing operations of the storage device 100, or reading in one of the storage devices 100) The data is bypassed from the NV memory chip to the memory controller 110).

FIG. 4 is a diagram showing the data processing scheme of the interface wafer 300 shown in FIG. 3 in an embodiment. The sub-circuits of the access circuit 116 may include arbiter 414 and 415, and further include a plurality of direct memory access circuits (referred to as "DMA circuits"), such as respectively located in the write Two sets of DMA circuits {416-1, 416-2, ..., 416-K} and {417-1, 417-2, ..., 417-K} of the channel circuit 116W and the read channel circuit 116R. For the sake of brevity, the two sets of DMA circuits can be labeled "DMA" in Figure 4. The arbiter 414 can control the operation of the set of DMA circuits {416-1, 416-2, ..., 416-K} to transfer data from the data buffer 114 to the interface wafer 300. The arbiter 415 can control the operation of the DMA circuits {417-1, 417-2, ..., 417-K} to retrieve data from the interface wafer 300 and temporarily store the data in the data buffer 114. As shown in FIG. 4, a portion of the circuit of the interface wafer 300, such as the ECC circuit 320ECC, can be coupled to the access circuit 116 of the memory controller 110, wherein other portions of the interface wafer 300 are not shown for simplicity. In Figure 4. For example, the set of DMA circuits {416-1, 416-2, ..., 416-K} can write data to the data buffer 326 via the servant interface circuit 310. When the data is received from the set of DMA circuits {416-1, 416-2, ..., 416-K} through the servant interface circuit 310, the interface chip 300 can buffer the data in the data buffer 326 and can be utilized. Inspection circuit 324 checks if the data is received correctly. When the inspection result indicates that the data is correctly received, the interface wafer 300 can encode the data using the encoder 327. For another example, the interface chip 300 can decode the codewords from the set of NV memory chips (such as the flash chips in the error-free module 150-n) by using the decoder 328 to obtain the correct read data and The read data is buffered in the data buffer 326, and the read data can be protected by the re-encoding circuit 325 to generate a corresponding cyclic redundancy check code. Thus, the set of DMA circuits {417-1, 417-2, ..., 417-K} can read the protected read data in the data buffer 326 through the servant interface circuit 310.

According to this embodiment, the encoder 327 may include a group of encoding circuits {327-1, 327-2, ..., 327- corresponding to the set of DMA circuits {416-1, 416-2, ..., 416-K}, respectively. K}, and the decoder 328 may include a set of decoding circuits {328-1, 328-2, ..., 328-K corresponding to the set of DMA circuits {417-1, 417-2, ..., 417-K}, respectively. } and a set of Digital Signal Processing Engine ("DSP Engine") {428-1, 428-2, ..., 428-K}. For example, the set of NV memory chips (such as the flash chips in the error-free module 150-n) may include K flash chips, and the K flash chips may be coupled to the group through the main interface circuit 330. The encoding circuits {327-1, 327-2, ..., 327-K} are also coupled to the set of DSP engines {428-1, 428-2, ..., 428-K} through the main interface circuit 330. In addition, the group of encoding circuits {327-1, 327-2, ..., 327-K} can respectively perform error correction code encoding operations on the data to be written into the K flash chips to generate respective parity of the data. The code is verified, and corresponding code words are respectively written into the K flash chips to protect the data, wherein the code words include the data and the parity codes. When the interface chip 300 reads the data from the K flash chips for the memory controller 110, the read data read by the interface chip 300 from the K flash chips may include the read versions of the code words. Ben, where the read versions may have errors. Any one of the set of DSP engines {428-1, 428-2, ..., 428-K} may perform at least one of the at least one of the operations described above (such as soft decoding, hard decoding, when needed) , error recovery control, read error handling, read retry, and/or Vth tracking) to obtain a correctable codeword so that decoding circuit 328-k can successfully perform error correction code based on the correctable codeword The decoding operation corrects the error, where the symbol "k" represents a positive integer falling within the interval [1, K]. Thus, the set of decoding circuits {328-1, 328-2, ..., 328-K} can obtain the correct version of the data.

According to some embodiments, the decoding circuit {328-1, 328-2, ..., 328-K} may perform a low-density parity-check (LDPC) code; simply referred to as an "LDPC code" The encoding operation is performed, and the parity codes may be LDPC codes.

In some embodiments, control circuitry 320 can access the K flash chips through main interface circuitry 330 in accordance with a physical address, such as a block physical address or a page physical address. For example, the memory controller 110 can specify the physical addresses in a write operation or a read operation. Thus, the interface chip 300 can access certain blocks or pages of the K flash chips for the memory controller 110 according to the physical addresses. Additionally, with respect to read error handling, control circuit 320 (e.g., ECC circuit 320ECC) can perform error correction of any of a plurality of word lines (WL lines) to provide error-free information to memory controller 110. For example, the memory controller 110 can be any physical address of some physical addresses, only issue a read command to the interface chip 300, and then wait for the error-free data from the interface chip 300. In addition, control circuitry 320 (e.g., ECC circuitry 320ECC) may be responsible for performing read retry, LDPC soft decoding, and various other types of data protection operations.

FIG. 5 is a diagram showing a data protection scheme of the interface wafer 300 shown in FIG. 3 in an embodiment. Under the control of the control circuit 320, the interface chip 300 can combine the set of NV memory chips (for example, the flash chips in the error-free module 150-n, such as the K flash chips) into a fault-tolerant disk array. a Redundant Array of Independent Disks ("RAID") for storing a parity code of a set of data in at least one NV memory chip in the set of NV memory chips, wherein the set of data is distributed in the group In other NV memory chips in NV memory chips. For example, in the case of K=16, the K flash chips may include a set of flash chips {430-1, 430-2, ..., 430-16}, and the interface chip 300 may utilize the wafer enable signals respectively. CE0, CE1, ... and CE15 control whether flash chips 430-1, 430-2, ... and 430-16 are enabled. The control circuit 320 can control the interface chip 300 to read the materials D1, D2, ..., and D15 from the flash chips 430-1, 430-2, ..., and 430-15, respectively, and generate data according to the materials D1, D2, ..., and D15. One of the parity codes RP of D1, D2, ..., D15} to protect the data {D1, D2, ..., D15} by writing the parity code RP to the flash chip 430-16, wherein the parity code RP Can be considered a RAID parity code. For example, when any of the materials {D1, D2, ..., D15} has an error, the interface chip 300 can correct the error according to the parity code RP to ensure the correctness of the data {D1, D2, ..., D15}.

The data protection scheme shown in Fig. 5 can be applied to the interface wafers {122-1, 122-2, ..., 122-N} shown in Fig. 1, respectively. Based on the data protection scheme, the interface chips {122-1, 122-2, ..., 122-N} can respectively perform the flash chips of the error-free modules {150-1, 150-2, ..., 150-N} respectively. RAID protection. Therefore, in this hierarchical architecture, this data protection mechanism can be considered as lower layer RAID protection. According to some embodiments, the RAID belongs to a layer of RAIDs in the storage device 100, such as a lower layer RAID. The interface chips {122-1, 122-2, ..., 122-N} can respectively form the flash chips of the error-free modules {150-1, 150-2, ..., 150-N} into N RAIDs (N RAIDs). ), wherein the N RAIDs belong to the layer RAID, and the N RAIDs comprise the RAID. In addition, the memory controller 110 can combine the plurality of NV memory chips into another layer of RAID, such as a higher layer RAID, wherein the other layer of RAID is different from the layer of RAID.

FIG. 6 is a diagram showing the data protection scheme of the storage device 100 shown in FIG. 1 in an embodiment. According to this embodiment, there are at least two layers of RAID in the storage device 100, such as the layer RAID (which includes the N RAIDs) and the other layer of RAID. Regarding this layer of RAID, any of the N RAIDs can perform the lower layer RAID protection shown in FIG. For example, this RAID can generate the parity code RP of the data {D1, D2, ..., D15} according to the data D1, D2, ... and D15 to protect the data {D1, D2, ..., D15 through the parity code RP. }. In the case of K = 16 and N = 16, the N RAIDs such as RAID {RAID(0), RAID(1), ..., RAID(15)} may correspond to the channel {Ch(0), Ch(1, respectively). ), ..., Ch(15)}. For the sake of understanding, the symbols "D1", "D2", ... "D15" and "RP" are indicated at the top of Figure 6, to indicate that the N RAIDs can perform the lower layer RAID protection shown in Figure 5. The nth RAID RAID (n - 1) corresponds to the channel Ch(n - 1), and the data {D1(n) is generated according to the data {D1(n), D2(n), ..., D15(n)}, The parity code RP(n) of D2(n), ..., D15(n)}. For example: the first RAID RAID (0) generates data {D1 (1), D2 (1), ..., D15 (1)} parity code RP (1), the second RAID RAID (1) generates data {D1(2), D2(2), ..., D15(2)} parity code RP(2), ... and the 15th RAID RAID (14) generates data {D1(15), D2(15) , ..., D15 (15)} parity code RP (15).

Regarding the other layer of RAID, the memory controller 110 can perform higher layer RAID protection. As shown in FIG. 6, the lower layer RAID protection may correspond to a data arrangement direction, such as landscape, and the higher layer RAID protection may correspond to another data arrangement direction, such as portrait. The memory controller 110 can generate the data according to the data of the corresponding pages in the previous (N - 1) RAID {RAID(0), RAID(1), ..., RAID(N - 2)} of the N RAIDs. The parity code, and uses the parity code as the material of the page corresponding to one of the Nth RAID RAIDs (N-1) of the N RAIDs. In the case of K = 16 and N = 16, the Nth RAID RAID (N-1) is the 16th RAID RAID (15). For example, the memory controller 110 can use the parity code of the data {D1(1), D1(2), ..., D1(15)} as the material D1(16), and the data {D2(1), D2( The parity code of 2), ..., D2(15)} is used as the data D2(16), ... and the parity code of the data {D15(1), D15(2), ..., D15(15)} is used as the parity code Information D15 (16). After that, the 16th RAID RAID (15) can perform the lower layer RAID protection according to the data {D1(16), D2(16), ..., D15(16)} (such as generated by the higher layer RAID protection mechanism). The parity codes) generate a parity code RP (16).

FIG. 7 illustrates a bypass control scheme of the interface wafer 300 of FIG. 3 in an embodiment. Based on the bypass control scheme, the interface wafer set 120 can be replaced with a multi-layer interface wafer set, and the flash wafers in the NV memory 130 can be extended to a larger number of flash wafers to achieve more One of the large storage capacity storage devices. According to this embodiment, the bypass interface circuits {340-1, 340-2, ..., 340-M} can be used to respectively couple the interface wafers 300 to a plurality of other interface wafers in the storage device, such as an interface wafer {300- 1, 300-2, ..., 300-M}, wherein the interface wafer 300 is between the memory controller 110 and the plurality of other interface wafers under the control of the control circuit 320 (e.g., the bypass mode control circuit 329) Passing at least one of the at least one instruction and the data, and accessing the multi-array NV memory chip in the storage device by the memory controller 110 through the plurality of other interface chips. For example, any of the interface wafers {300-1, 300-2, ..., 300-M} may have the same circuit architecture as the interface wafer 300, and the interface wafers {300-1, 300-2, ..., 300 -M} respective servant interface circuits {310-1, 310-2, ..., 310-M} can be respectively coupled to the bypass interface circuits of the interface wafer 300 {340-1, 340-2, ..., 340-M }. The bypass path shown by a broken line in Fig. 7 can be taken as an example of the bypass paths mentioned in the embodiment shown in Fig. 3. For example, a main interface circuit of any of the interface chips 300-m of the interface chip {300-1, 300-2, ..., 300-M} can be used to couple a set of NV memory in the complex array NV memory chip. A wafer, such as a plurality of flash wafers in an error-free module. In this case, the layer count of the multi-layer interface chip set can be equal to two layers. For another example, M bypass interface circuits of any of the interface wafers 300-m of the interface wafers {300-1, 300-2, ..., 300-M} can be used to couple M additional interface wafers respectively (its The same circuit architecture as the interface wafer 300 can be used, wherein the M additional interface wafers and interface wafers 300 can be the same type of products, such as products having the same circuit design and produced under the same process and the same conditions, to The M additional interface chips are coupled to a plurality of sets of NV memory chips in the complex array NV memory chip, such as a plurality of flash chips in a plurality of error-free modules. In this case, the number of layers of the multi-layer interface wafer set can be greater than two layers.

According to this embodiment, a hierarchical structure of the storage device may include a memory controller 110, an interface chip 300, and a plurality of other interface chips (such as interface chips {300-1, 300-2, ..., 300-M }) and the complex array of NV memory chips. The interface wafer 300 can be a multi-function interface wafer, and can have a plurality of functions corresponding to a plurality of configurations, respectively, and the plurality of other interface wafers (such as interface wafers {300-1, 300-2, ... Any of the 300-M}) may have the same circuit architecture as the interface wafer 300, wherein the plurality of other interface wafers operate according to one of the plurality of configurations, and the interface wafer 300 is based on The second configuration of one of the plurality of configurations operates. For example, the plurality of other interface wafers (such as interface wafers {300-1, 300-2, ..., 300-M}) and the interface wafer 300 may be of the same type, such as having the same circuit design and having the same process and the same conditions. Products to be produced; these products can be considered as identical products to each other, ignoring the possible small differences between these products (due to process and the like). As can be seen from the architecture shown in FIG. 3, the main interface circuit 330 of the interface chip 300 has an NV memory chip coupling function. For example, according to the second configuration, the main interface circuit 330 of the interface wafer 300 is idle. For another example, according to the first configuration, one of the other interface wafers of any one of the other interface wafers corresponds to a main interface circuit, such as an interface chip {300-1, 300-2, ..., 300-M} The main interface circuit of any one of the interface chips 300-m can be coupled to the set of NV memory chips in the complex array NV memory chip to allow the other interface chips to be accessed by the memory controller 110. The set of NV memory chips (such as a plurality of flash chips in an error-free module), wherein a plurality of corresponding bypass interface circuits of the other interface wafers are idle according to the first configuration.

Under the control of the memory controller 110, the storage device may have the plurality of channels, such as N channels Ch(0), Ch(1), ..., and Ch(N-1), wherein each channel may With multiple correct modules. The plurality of NV memory chips managed by the multi-layer interface chip set (such as the above-mentioned larger number of flash chips) may respectively correspond to the plurality of channels, and the complex array NV memory chips may correspond to the complex number One of the channels. For example, the interface wafer 300 and the plurality of other interface wafers (such as interface wafers {300-1, 300-2, ..., 300-M}) may correspond to the channel. For another example, the interface wafer 300, the plurality of other interface wafers (such as interface wafers {300-1, 300-2, ..., 300-M}) and the complex array NV memory wafer may belong to the channel instead of the plurality Any of the other channels.

Additionally, the storage device includes the multi-layer interface wafer set. According to some embodiments, the interface wafer 300 belongs to a layer of interface wafers in the multi-layered interface wafer set, such as a first layer of interface wafers, and the plurality of other interface wafers (such as interface wafers {300-1, 300-2) , ..., 300-M}) another layer of interface chips in the multi-layer interface chip set, such as a second layer interface chip set, wherein the first layer interface chip set can operate according to the second configuration, and The second level interface chip set can operate in accordance with the first configuration. The first layer of interface chips can access the plurality of NV memory chips (such as the above-described larger number of flash chips) for the memory controller 110 through the second layer of interface chips. For example, any two interface wafers in the multi-layer interface wafer set may have the same circuit architecture, and the interface wafer 300 may be one of the two interface wafers, but the invention is not limited thereto. When the two interface wafers are disassembled from the storage device, the two interface wafers are exchangeable in the hierarchical architecture for mutual replacement. For example, the multi-layer interface chip set can be the same type of product, such as products having the same circuit design and produced under the same process and the same conditions; these products can be regarded as the same product, which is ignored (due to process and the like) The smallest possible difference between these products.

According to some embodiments, the interface chip in the first layer interface chip group can be regarded as a plurality of first layer interface wafers, and the interface chip in the second layer interface chip group can be regarded as a plurality of second layer interface wafers, wherein The plurality of other interface wafers (such as interface wafers {300-1, 300-2, ..., 300-M}) are a set of second layer interface wafers of the plurality of second layer interface wafers. For example, the plurality of second layer interface wafers comprise a complex array of second layer interface wafers, and the set of second layer interface wafers is a group of the second array of interface layers of the plurality of layers. The hierarchical architecture includes a memory controller 110, the plurality of first layer interface wafers, the complex array second layer interface wafer, and the plurality of NV memory chips (such as the larger number of flash wafers described above).

FIG. 8 is a schematic diagram of a storage device 600 according to another embodiment of the present invention, wherein the bypass control scheme shown in FIG. 7 is applicable to the storage device 600. The storage device 600 can be used as an example of the storage device having a larger storage capacity as described in the embodiment shown in FIG. 7, and the first layer interface chip set 620-1 and the second layer interface chip group 620-2 can be used as the multilayer layer. An example of an interface chipset, and a complex array of NV memories managed by any of the interface wafers 122-n of the interface wafers {122-1, 122-2, ..., 122-N} of the first layer of the chipset 620-1 Body wafer (such as M error-free modules {650-(M*(n-1)+1), 650-(M*(n-1)+2), ..., 650-(M*n)} The flash wafer can be used as an example of the complex array NV memory chip accessed by the interface wafer 300 through the plurality of other interface wafers (such as interface wafers {300-1, 300-2, ..., 300-M}).

Based on the architecture shown in FIG. 8, the present invention can maximize the storage capacity of the storage device 600 while ensuring the performance and reliability of the storage device 600. Compared with the storage device 100, the number of error-free modules in the storage device 600 can be expanded to (M * N), among which non-volatile memory (referred to as "NV memory") 630 (M * N) Group NV memory chips (such as error-free modules {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N-1)+1), 650-(M* (N-1)+2), ..., 650-(M*N)}} respective flash wafers may represent a larger number of flash wafers as described above. For example: error-free module {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N-1)+1), 650-(M*(N-1)+ Any of the 2), ..., 650-(M*N)}} modules can be similar to the error-free module 150-n. Another example: uncorrected modules {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N-1)+1), 650-(M*(N-1) Any of the +2), ..., 650-(M*N)}} modules can be identical to the error-free module 150-n. In addition, the coupling relationship between the first layer interface chip set 620-1 and the second layer interface chip group 620-2 can be implemented according to the bypass control scheme. For example, when the interface wafer 300 shown in FIG. 7 represents the interface wafer 122-1 shown in FIG. 8, the interface wafers {300-1, 300-2, ..., 300-M} shown in FIG. 7 can represent Uncorrected modules {650-1, 650-2, ..., 650-M} respective interface wafers; and so on. For another example, when the interface wafer 300 shown in FIG. 7 represents the interface wafer 122-N shown in FIG. 8, the interface wafers {300-1, 300-2, ..., 300-M} shown in FIG. 7 may be Represents the correct interface module {650-(M*(N-1)+1), 650-(M*(N-1)+2), ..., 650-(M*N)} respective interface wafers. Further, the first layer interface chip set 620-1 includes interface wafers {122-1, 122-2, ..., 122-N}. The coupling relationship between the interface wafers {122-1, 122-2, ..., 122-N} of the first interface chipset 620-1 and the memory controller 110 can be compared with the interface wafer of the interface chipset 120. The coupling relationship between -1, 122-2, ..., 122-N} and memory controller 110 is the same, with related implementation details being implemented in some of the foregoing embodiments (such as shown in Figures 1, 3 through 4) Example). For example, the interface of each of the interface chips {122-1, 122-2, ..., 122-N} of the interface chipset 620-1 can be coupled to the access circuit 116 of the memory controller 110. According to the embodiment, the first layer interface chip set 620-1 can access the (M*N) group NV memory chips in the NV memory 630 for the memory controller 110 through the second layer interface chip set 620-2 ( Such as the error-free module {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N-1)+1), 650-(M*(N-1)+2 ), ..., 650-(M*N)}} respective flash chips).

According to some embodiments, the interface wafer 122-n can control the complex array of NV memory chips managed by the interface wafer 122-n under the control of the control circuit (such as the control circuit 320) in the interface wafer 122-n ( Such as the M error-free modules {650-(M*(n-1)+1), 650-(M*(n-1)+2), ..., 650-(M*n)} respective flashes Chips are combined into a RAID to store one of a set of data parity codes in at least one NV memory chip in the complex array NV memory chip, wherein the set of data is distributed in the complex array NV memory chip At least a portion of the NV memory wafer. In particular, the at least one NV memory chip may include all of the NV memory chips in a set of NV memory chips in the complex array NV memory chip, such as a flash chip of the error-free module 650-(M*n). And the at least a portion of the NV memory chips may include other sets of NV memory chips in the complex array of NV memory chips, such as the previous (M-1) error-free modules of the M error-free modules (ie, the M Incorrect modules {650-(M*(n-1)+1), 650-(M*(n-1)+2), ..., 650-(M*n)} except for the error-free module 650- The remaining error-free modules (M*n) are the respective flash chips. In addition, the parity code includes a plurality of partial parity codes, and the plurality of partial parity codes are respectively stored in the set of NV memory chips (such as the error-free module 650-(M*n). Corresponding page in the flash chip). Since the interface chips {122-1, 122-2, ..., 122-N} can be respectively correct for the {{650-1, 650-2, ..., 650-M}, ..., {650-(M*( N-1) +1), 650-(M*(N-1)+2), ..., 650-(M*N)}} respective flash chips are RAID protected, so in this hierarchical architecture, This data protection mechanism can be considered as a lower level RAID protection.

According to some embodiments, this RAID belongs to a layer of RAIDs in storage device 600, such as a lower layer RAID. The interface chips {122-1, 122-2, ..., 122-N} can respectively be error-free modules {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N -1) +1), 650-(M*(N-1)+2), ..., 650-(M*N)}} respective flash chips constitute N RAIDs (N RAIDs), wherein the N RAID belongs to this layer of RAID, and the N RAIDs contain the RAID. In addition, the memory controller 110 can combine the (M*N) group of NV memory chips in the NV memory 630 into another layer of RAID, such as a higher layer RAID, wherein the other layer of RAID is different from the layer of RAID.

FIG. 9 is a diagram showing the data protection scheme of the first layer interface chip set 620-1 shown in FIG. 8 in an embodiment. For example: M = 4, and the storage device 700 can be used as an example of the storage device 600 shown in FIG. 8, wherein the first layer of the interface chip set 720-1, the second layer of the interface chip set 720-2, and the non-volatile memory ( Referred to as "NV memory" 730, it can be used as an example of the first layer interface chip set 620-1, the second layer interface chip set 620-2 and the NV memory 630, respectively, and the error-free module {750-1, 750- 2, 750-3, 750-4, ...} can be used as an error-free module {{650-1, 650-2, ..., 650-M}, ..., {650-(M*(N-1)+1) , 650-(M*(N-1)+2), ..., 650-(M*N)}}. One of the first interface chip sets 720-1, such as the interface chip 722-1, can utilize a wafer enable signal (such as a wafer enable signal) through one of the interface chips of the second interface chip set 720-2. CE0, CE1, ..., etc.) to control whether the flash chips are enabled. For example, the control circuit (such as the control circuit 320) of the interface chip 722-1 can control the interface chip 722-1 to read the data D from the respective flash chips of the error-free modules 750-1, 750-2, and 750-3, respectively. 1, 1), D(1, 2) and D(1, 3), and generate data {D(1, 1) based on data D(1, 1), D(1, 2) and D(1, 3) ), one of the D(1, 2), D(1, 3)} parity codes RP'(1), to write the parity code RP'(1) into the flash of the error-free module 750-4 The chip protects the data {D(1, 1), D(1, 2), D(1, 3)}, wherein the parity code RP'(1) can be regarded as a RAID parity code. For example, when any of the data {D(1, 1), D(1, 2), D(1, 3)} has an error, the interface chip 722-1 can be based on the parity code RP'(1). Correct the error to ensure the correctness of the data {D(1, 1), D(1, 2), D(1, 3)}.

FIG. 10 is a diagram showing the data protection scheme of the storage device 600 shown in FIG. 8 in an embodiment. For ease of understanding, the relevant parameters (for example, M = 4) in the embodiment shown in Fig. 9 and the corresponding symbols are used for explanation. In accordance with the present embodiment, there are at least two levels of RAID in the storage device 600, such as the layer RAID and the other layer of RAID described in the embodiments based on the architecture shown in FIG. Any of the N RAIDs of the layer RAID can perform the lower layer RAID protection shown in FIG. In the case of M=4 and N=16, the N RAIDs such as RAID {RAID'(0), RAID'(1), ..., RAID'(15)} may correspond to the channel {Ch(0), respectively. Ch(1), ..., Ch(15)}, and the nth RAID RAID '(n - 1) corresponds to the channel Ch(n - 1) and depends on the material {D(n, 1), D(n , 2), D(n, 3)} generates the parity code RP'(n) of the data {D(n, 1), D(n, 2), D(n, 3)}. For example: the first RAID RAID '(0) generates the parity code RP'(1) of the data {D(1, 1), D(1, 2), D(1, 3)}, the second RAID RAID'(1) generates the parity code RP'(2),... and the 15th RAID RAID' of the data {D(2, 1), D(2, 2), D(2, 3)} The parity code RP' (15) of the data {D(15, 1), D(15, 2), D(15, 3)} is generated.

Regarding this other layer of RAID, the memory controller 110 can perform higher layer RAID protection. As shown in FIG. 10, the lower layer RAID protection may correspond to a data arrangement direction, such as a landscape orientation, and the higher layer RAID protection may correspond to another data arrangement direction, such as a portrait orientation. The memory controller 110 can be based on the data of the corresponding pages in the previous (N - 1) RAID {RAID'(0), RAID'(1), ..., RAID'(N - 2)} of the N RAIDs. A parity code of the data is generated, and the parity code is used as data of a page corresponding to one of the Nth RAID RAID's (N-1) of the N RAIDs. In the case of M = 4 and N = 16, the Nth RAID RAID' (N - 1) is the 16th RAID RAID' (15). For example, the memory controller 110 can use the parity code of the data {D(1, 1), D(2, 1), ..., D(15, 1)} as the data D(16, 1), the utilization data. The parity code of {D(1, 2), D(2, 2), ..., D(15, 2)} is used as the data D(16, 2), and the data {D(1, 3), D is utilized. The parity code of (2, 3), ..., D(15, 3)} is used as the material D (16, 3). After that, the 16th RAID RAID '(15) can perform the lower layer RAID protection according to the data {D(16, 1), D(16, 2), D(16, 3)} (such as the higher layer) The parity codes generated by the RAID protection mechanism generate a parity code RP' (16). The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100,600,700‧‧‧ storage devices

105‧‧‧Dynamic random access memory

110‧‧‧ memory controller

110P‧‧‧Microprocessor

112‧‧‧Interface circuit

114‧‧‧Data buffer

115‧‧‧Other buffers

116‧‧‧Access circuit

116R‧‧‧Read channel circuit

116W‧‧‧Write channel circuit

120‧‧‧Interface chipset

122-1,122-2,...,122-N,300,300-1,300-2,...,300-M,722-1,...‧‧‧Interface Wafer

130,630,730‧‧‧ Non-volatile memory

150-1,150-2,...,150-N,650-1,650-2,...,650-M,...,650-(M*(N-1)+1),650-(M*(N-1) +2),...,650-(M*N),750-1,750-2,750-3,750-4,‧‧‧

310,310-1,310-2,...,310-M‧‧‧ servant interface circuit

310P‧‧‧Parallel interface circuit

310S‧‧‧Sequence Interface Circuit

320‧‧‧Control circuit

320CRC‧‧‧cyclic redundancy check circuit

320ECC‧‧‧Error Correcting Code Circuit

321‧‧‧Sequence to parallel controller

322‧‧‧Command Converter

323‧‧‧ instruction buffer

324‧‧‧Check circuit

325‧‧‧ Re-encoding circuit

326‧‧‧Data buffer

327‧‧‧Encoder

327-1, 327-2,...,327-K‧‧‧Code Circuit

328‧‧‧Decoder

328-1,328-2,...,328-K‧‧‧ decoding circuit

329‧‧‧Bypass mode control circuit

329R‧‧‧ Repeater

329SW‧‧‧Switching circuit

330‧‧‧Main interface circuit

340-1, 340-2, ..., 340-M‧‧‧ bypass interface circuit

414,415‧‧‧ arbitrator

416-1,416-2,...,416-K,417-1,417-2,...,417-K‧‧‧Direct memory access circuit

428-1,428-2,...,428-K‧‧‧Digital Signal Processing Engine

430-1, 430-2, ..., 430-15, 430-16‧‧‧ flash chip

620-1, 720-1‧‧‧ first layer interface chipset

620-2, 720-2‧‧‧Second layer interface chipset

CE0, CE1, ..., CE15‧‧‧ wafer enable signal

Ch(0), Ch(1),...,Ch(15)‧‧‧ channels

D1, D2, ..., D15, D1 (1), D2 (1), ..., D15 (1), D1 (2), D2 (2), ..., D15 (2), ..., D1 (15), D2 (15),...,D15(15),D1(16),D2(16),...,D15(16),D(1,1),D(1,2),D(1,3),D (2,1), D(2,2), D(2,3),...,D(15,1),D(15,2),D(15,3),D(16,1), D(16,2), D(16,3)‧‧‧ Information

RP, RP (1), RP (2), ..., RP (15), RP (16), RP ' (1), RP ' (2), ..., RP ' (15), RP ' (16) ‧ ‧‧Parity code

1 is a schematic view of a storage device in accordance with an embodiment of the present invention. FIG. 2 is a diagram showing the implementation details of the storage device shown in FIG. 1 in an embodiment. 3 is a schematic diagram of an interface wafer according to an embodiment of the invention, wherein the interface wafer can be applied to the storage device shown in FIG. FIG. 4 is a diagram showing the data processing scheme of the interface wafer shown in FIG. 3 in an embodiment. FIG. 5 is a diagram showing the data protection scheme of the interface wafer shown in FIG. 3 in an embodiment. FIG. 6 is a diagram showing the data protection scheme of the storage device shown in FIG. 1 in an embodiment. FIG. 7 is a diagram showing a bypass control scheme of the interface wafer shown in FIG. 3 in an embodiment. FIG. 8 is a schematic diagram of a storage device according to another embodiment of the present invention, wherein the bypass control scheme shown in FIG. 7 is applicable to the storage device. FIG. 9 is a diagram showing the data protection scheme of the first layer interface chip set shown in FIG. 8 in an embodiment. FIG. 10 is a diagram showing the data protection scheme of the storage device shown in FIG. 8 in an embodiment.

Claims (24)

An interface chip is applied to a memory device, the interface chip includes: a slave interface circuit for coupling the interface chip to a memory controller, wherein the memory device includes the memory a body controller and a non-volatile (NV) memory, the non-volatile memory comprising a plurality of non-volatile memory chips, and the memory controller is responsive to a master device command from a host device Accessing the non-volatile memory through the interface chip; at least one bypass interface circuit for coupling the interface chip to at least one other interface chip in the storage device; and a control circuit And being coupled between the slave interface circuit and the at least one bypass interface circuit for controlling operation of the interface chip, wherein the interface chip is in the memory controller and the at least one other interface under the control of the control circuit At least one of the instructions and the data is bypassed between the wafers. The interface chip of claim 1, wherein the at least one bypass interface circuit comprises a plurality of bypass interface circuits, the at least one other interface wafer comprises a plurality of other interface wafers, and the plurality of bypass interface circuits are The interface wafers are respectively coupled to the plurality of other interface wafers. The interface chip of claim 2, wherein the plurality of other interface chips are respectively coupled to the plurality of non-volatile memory chips in the plurality of non-volatile memory chips; and the control circuit The interface chip accesses the complex array of non-volatile memory chips for the memory controller through the plurality of other interface chips. The interface chip of claim 1, wherein the at least one other interface chip is coupled to at least one of the plurality of non-volatile memory chips; and the storage device A hierarchical architecture includes the memory controller, the interface wafer, the at least one other interface wafer, and the at least one set of non-volatile memory wafers. The interface wafer of claim 4, wherein the interface wafer is a multi-function interface wafer and has a plurality of functions respectively corresponding to a plurality of configurations; any of the at least one other interface wafer One having the same circuit architecture as the interface wafer; and the at least one other interface wafer operating in accordance with one of the plurality of configurations, and the interface wafer is based on one of the plurality of configurations Configuration to operate. The interface chip of claim 5, wherein the at least one bypass interface circuit comprises a plurality of bypass interface circuits, the at least one other interface wafer comprises a plurality of other interface wafers, and the plurality of bypass interface circuits are The interface wafer is respectively coupled to the plurality of other interface wafers; the at least one non-volatile memory wafer comprises a complex array of non-volatile memory wafers; and the interface wafer further comprises: a master interface a circuit having a non-volatile memory chip coupling function, wherein: according to the second configuration, the main interface circuit of the interface chip is idle; and according to the first configuration, the plurality of other A corresponding one of the other interface chips in the interface chip is coupled to one of the non-volatile memory chips in the plurality of non-volatile memory chips to allow the other interface chip to be The memory controller accesses the set of non-volatile memory chips in the complex array of non-volatile memory chips. The interface wafer of claim 6, wherein a plurality of corresponding ones of the other interface wafers are idle according to the first configuration. The interface wafer of claim 1, wherein the at least one other interface chip is coupled to at least one of the plurality of non-volatile memory chips; and the plurality of non-volatile memory chips The volatile memory wafers respectively correspond to a plurality of channels of the storage device, and the at least one set of non-volatile memory chips corresponds to one of the plurality of channels. The interface wafer of claim 8, wherein the interface wafer and the at least one other interface wafer correspond to the channel. The interface wafer of claim 8, wherein the interface wafer, the at least one other interface wafer, and the at least one set of non-volatile memory wafers belong to the channel instead of any of the plurality of channels aisle. The interface wafer of claim 1, wherein the storage device comprises a multi-layer interface wafer group, the interface wafer belongs to a layer interface chip group of the multi-layer interface wafer group, and the at least one other interface wafer belongs to the multi-layer interface Another layer of interface chips in the wafer set. The interface wafer of claim 11, wherein the layer of the interface chip accesses the plurality of non-volatile memory chips to the memory controller through the other layer of the interface chip. The interface wafer of claim 12, wherein any two interface wafers of the multi-layered interface wafer have the same circuit architecture; and when the two interface wafers are disassembled from the storage device The two interface chips are exchangeable in the hierarchical architecture for mutual replacement. The interface wafer of claim 1, wherein the at least one other interface chip is coupled to at least one of the plurality of non-volatile memory chips; and the control circuit Under control, the at least one set of non-volatile memory chips is combined into a Redundant Array of Independent Disks (RAID) to set a parity-check code of a set of data. Storing at least one non-volatile memory chip in the at least one non-volatile memory chip, wherein the set of data is distributed in at least a portion of the non-volatile memory chips of the at least one set of non-volatile memory chips . The interface chip of claim 14, wherein the at least one bypass interface circuit comprises a plurality of bypass interface circuits, the at least one other interface wafer comprises a plurality of other interface wafers, and the plurality of bypass interface circuits are The interface wafer is respectively coupled to the plurality of other interface wafers; the at least one non-volatile memory wafer comprises a complex array of non-volatile memory wafers; and the at least one non-volatile memory wafer comprises the plurality a non-volatile memory chip in a group of non-volatile memory chips in a non-volatile memory chip, and the at least a portion of the non-volatile memory chip includes the other of the plurality of non-volatile memory chips a non-volatile memory chip; and the parity code includes a plurality of partial parity codes, and the plurality of partial parity codes are respectively stored in the complex array non-volatile memory chip A corresponding page in a group of non-volatile memory chips. The interface wafer of claim 14, wherein the fault-tolerant disk array belongs to a layer fault-tolerant disk array; and the memory controller combines the plurality of non-volatile memory chips into another A layer of fault tolerant disk array, wherein the other layer of fault tolerant disk array is different from the layer of fault tolerant disk array. The interface wafer of claim 16, wherein the storage device comprises a multi-layer interface wafer group, the interface wafer belongs to a layer interface chip group of the multi-layer interface wafer group, and the at least one other interface wafer belongs to the multi-layer interface Another layer of the interface chip set in the chip set; and the layer interface chip set operates according to one of a plurality of configurations, and the other layer interface chip set operates according to another configuration of the plurality of configurations . A storage device comprising: a non-volatile (NV) memory for storing information, wherein the non-volatile memory comprises a plurality of non-volatile memory chips; and a memory controller is used Controlling the operation of the storage device; and a plurality of interface wafers coupled between the memory controller and the non-volatile memory, wherein the plurality of interface wafers comprise a plurality of first layer interface chips and a plurality of The second layer interface wafer, and any one of the plurality of first layer interface wafers comprises: a slave interface circuit for coupling the interface wafer to the memory controller, wherein the memory The controller accesses the non-volatile memory through the interface chip according to a master device command from a master device; at least one bypass interface circuit for coupling the interface chip to at least one other An interface chip, wherein the at least one other interface chip belongs to the plurality of second layer interface wafers; and a control circuit coupled to the interface circuit and Between at least one of the bypass interface circuits for controlling the operation of the interface chip, wherein the interface chip bypasses at least one instruction between the memory controller and the at least one other interface chip under the control of the control circuit At least one of the materials. The storage device of claim 18, wherein the at least one bypass interface circuit comprises a plurality of bypass interface circuits, the at least one other interface wafer comprises a plurality of other interface wafers, and the plurality of bypass interface circuits are The interface wafers are respectively coupled to the plurality of other interface wafers, wherein the plurality of other interface wafers are a set of second layer interface wafers of the plurality of second layer interface wafers. The storage device of claim 19, wherein the plurality of other interface chips are respectively coupled to the plurality of non-volatile memory chips in the plurality of non-volatile memory chips; and the control circuit The interface chip accesses the complex array of non-volatile memory chips for the memory controller through the plurality of other interface chips. The storage device of claim 18, wherein the at least one other interface chip is coupled to at least one of the plurality of non-volatile memory chips; and the storage device A hierarchical architecture includes the memory controller, the interface wafer, the at least one other interface wafer, and the at least one set of non-volatile memory wafers. The storage device of claim 21, wherein the interface chip is a multi-function interface chip and has a plurality of functions respectively corresponding to a plurality of configurations; wherein the at least one other interface chip One having the same circuit architecture as the interface wafer; and the at least one other interface wafer operating in accordance with one of the plurality of configurations, and the interface wafer is based on one of the plurality of configurations Configuration to operate. The storage device of claim 21, wherein the plurality of second layer interface wafers comprise a plurality of second layer interface wafers, and the at least one other interface wafer belongs to one of the second array interface wafers of the complex array And the hierarchical architecture includes the memory controller, the plurality of first layer interface wafers, the complex array second layer interface wafer, and the plurality of non-volatile memory chips. The storage device of claim 18, wherein the at least one other interface chip is coupled to at least one of the plurality of non-volatile memory chips; and the plurality of non-volatile memory chips The volatile memory wafers respectively correspond to a plurality of channels of the storage device, and the at least one set of non-volatile memory chips corresponds to one of the plurality of channels.