TW201911984A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board includes a first substrate, a thermal conductive substrate, and a second substrate stacked together in that order. The first substrate defines a cavity that passes through the first substrate. An electrical component is received in the cavity. A first conductive wiring layer and a second conductive wiring layer are formed on the first substrate and the second substrate, respectively. A first dielectric layer and a second dielectric layer are formed on the first conductive wiring layer and the second conductive wiring layer, respectively. A third conductive wiring layer and a fourth conductive wiring layer are formed on the first dielectric layer and the second dielectric layer, respectively. A first solder mask layer and a second solder mask layer are formed on the third conductive wiring layer and the fourth conductive wiring layer, respectively. A thermal conductive hole is defined from at least one of the first solder mask layer and the second solder mask layer. The thermal conductive hole exposes the thermal conductive substrate. Thermal conductive material is filled in the thermal conductive hole, thereby forming at least one thermal conductive portion.

Description

Circuit board and manufacturing method thereof

The invention relates to a circuit board and a manufacturing method of the circuit board.

In recent years, electronic products have been widely used in daily work and life, and light, thin and small electronic products have become more and more popular. As the main component of electronic products, circuit boards occupy a large space of electronic products. Therefore, the volume of circuit boards affects the volume of electronic products to a large extent. Large-volume circuit boards are bound to be difficult to meet the lightness and thinness of electronic products. , Short, small trends.

By burying the passive components (such as resistors and capacitors) of the circuit board inside the circuit substrate, it is beneficial to reduce the overall thickness of the circuit board, thereby reducing the thickness of the electronic product. However, the heat generated during the operation of the embedded passive components will be difficult to dissipate, which will cause the core layer of the circuit board to expand thermally and damage the circuit board.

In view of this, it is necessary to provide a circuit board capable of solving the above problems.

In addition, it is necessary to provide a method for manufacturing the circuit board.

The invention provides a method for manufacturing a circuit board, which includes: providing a circuit substrate. The circuit substrate includes a first single panel, a thermally conductive substrate, and a second single panel that are sequentially laminated. A cavity penetrates the first single panel. Panel, the first single panel includes a first copper foil disposed away from the thermally conductive substrate, and the second single panel includes a second copper foil disposed away from the thermally conductive substrate; the first copper foil and the second A first electroplated copper layer is formed by electroplating on the copper foil; the first electroplated copper layer and the first copper foil and the second copper foil located between the first electroplated copper layers are etched to obtain a first conductive circuit. Layer and a second conductive circuit layer; an electronic component is placed in the cavity, and a first dielectric layer and a second dielectric are laminated on the first conductive circuit layer and the second conductive circuit layer, respectively An electrical layer; a third conductive circuit layer and a fourth conductive circuit layer are formed on the first dielectric layer and the second dielectric layer, respectively, the third conductive circuit layer and the first conductive circuit layer and the electrons The device is electrically connected, and the fourth conductive circuit layer is in contact with the first conductive line layer. The conductive circuit layer is electrically connected; a first solder mask layer and a second solder mask layer are formed on the third conductive circuit layer and the fourth conductive circuit layer, respectively; and at least from the first solder mask layer and the first solder mask layer One of the two solder mask layers is provided with a thermally conductive hole penetrating the first solder mask layer and the first dielectric layer, or the second solder mask layer and the second dielectric layer, thereby exposing the thermally conductive substrate. Material, and then each thermally conductive hole is filled with a thermally conductive material to form at least one thermally conductive portion thermally connected to the thermally conductive substrate, thereby obtaining the circuit board.

The present invention also provides a circuit board including a first substrate, a thermally conductive substrate, and a second substrate that are sequentially stacked. The first substrate is formed with a cavity therethrough, and an electronic component is disposed in the cavity. A first conductive circuit layer and a second conductive circuit layer are formed on the first substrate and the second substrate, respectively. The first conductive circuit layer and the second conductive circuit layer are covered with a first dielectric layer and a first conductive layer, respectively. Two dielectric layers, a third conductive circuit layer and a fourth conductive circuit layer are formed on the first dielectric layer and the second dielectric layer, respectively, the third conductive circuit layer and the first conductive circuit layer and the The electronic components are electrically connected, the fourth conductive circuit layer is electrically connected to the second conductive circuit layer, and a first solder resist layer and a second solder resist layer are formed on the third conductive circuit layer and the fourth conductive circuit layer, respectively. A soldering layer is provided with at least one of the first solder resist layer and the second solder resist layer having a thermal conductive hole penetrating through the first solder resist layer and the first dielectric layer or through the second solder resist layer. Solder layer and the second dielectric layer, thereby Expose the thermally conductive substrate, the thermal via filled with a thermally conductive material, to form at least a thermally conductive portion.

In the above circuit board, the heat generated by the electronic component can be dissipated to the external environment through the thermally conductive substrate and the thermally conductive portion. Since the heat can be buffered when it reaches the thermally conductive substrate, thermal expansion of the core layer can be avoided.

Referring to FIGS. 1 to 14, a first embodiment of the present invention provides a method for manufacturing a circuit board 100, including the following steps:

Step one, referring to FIG. 1, a first single panel 11, a second single panel 12 and a thermally conductive substrate 13 are provided. The first single panel 11 includes a first substrate 110 and a first copper foil 111 coupled to the first substrate 110. A cavity 112 penetrates the first substrate 110 and the first copper foil 111. The second single panel 12 includes a second substrate 120 and a second copper foil 121 bonded to the second substrate 120. The thickness of the first copper foil 111 and the second copper foil 121 are both d1.

In this embodiment, the material of the thermally conductive substrate 13 is a thermally conductive resin composition having good electrical insulation properties. More specifically, the material of the thermally conductive substrate 13 may be selected from a thermally conductive resin composition filled with a nano-carbon material and a ring. At least one of an oxyresin-based thermally conductive resin composition, a polycarbonate-based thermally-conductive resin composition, an acrylic thermally-conductive resin composition, and the like. The thermal conductivity of the thermally conductive resin composition is K1.

Step two, referring to FIG. 2, the first single-sided panel 11 and the second single-sided panel 12 are respectively pressed on two opposite surfaces of the thermally conductive substrate 13 so that the first copper foil 111 and the second copper foil 121 are respectively pressed. The circuit board 20 is formed away from the thermally conductive substrate 13.

Step three, referring to FIG. 3, at least one opening 21 penetrating through the first single panel 11, the second single panel 12 and the thermally conductive substrate 13 is opened in an area of the circuit substrate 20 except the cavity 112. A first conductive seed layer 22 is formed on the inner wall of each of the openings 21 and the inner wall of the cavity 112.

In this embodiment, the opening 21 can be formed by laser drilling. In this embodiment, the first conductive seed layer 22 can be formed by chemical plating or sputtering.

Step four, please refer to FIG. 4, a patterned photoresist layer 30 is covered on the first copper foil 111 and the second copper foil 121, respectively. The openings (not shown) defined by the patterned photoresist layer 30 are used for A portion of the first copper foil 111 and the second copper foil 121 is exposed, the openings 21 where the first conductive seed layer 22 is formed, and the first conductive seed layer 22 where the first conductive seed layer 22 is formed. Cavity 112.

In this embodiment, the patterned photoresist layer 30 is formed by an exposure and development process to form a desired pattern. More specifically, the patterned photoresist layer 30 is a dry film.

Step five, referring to FIG. 5, copper is electroplated on the exposed areas of the first copper foil 111 and the second copper foil 121, so as to form electroplating on the first copper foil 111 and the second copper foil 121, respectively. First electroplated copper layer 40. Part of the first electroplated copper layer 40 is filled in the openings 21 where the first conductive seed layer 22 is formed to form first conductive holes 23 for electrically connecting the two first electroplated copper layers 40. A part of the first electroplated copper layer 40 is further formed in the cavity 112.

Wherein, the thickness of the first electroplated copper layer 40 is d2, and d2 ≧ d1.

Step 6: Referring to FIG. 6, the patterned photoresist layer 30 is removed, and the first electroplated copper layer 40 and the first copper foil 111 located between the first electroplated copper layer 40 are etched using an exposure and development technique. And the second copper foil 121 to obtain a first conductive circuit layer 51 and a second conductive circuit layer 52.

The thicknesses of the first conductive circuit layer 51 and the second conductive circuit layer 52 are both d2. The thickness of the first electroplated copper layer 40 in the cavity 112 after the etching is d2-d1.

Step 7. Referring to FIG. 7, an electronic component 63 is placed on the first electroplated copper layer 40 located in the cavity 112, and the electronic component 63 has a distance from the first electroplated copper layer located in the cavity 112. 40 of two contact pads 630. Then, a first dielectric layer 61 and a second dielectric layer 62 are laminated on the first conductive circuit layer 51 and the second conductive circuit layer 52, respectively, and the first dielectric layer 61 is flowed and filled. The space between the first conductive circuit layer 51 and the electronic component 63, and the second dielectric layer 62 is caused to flow and fill the space between the second conductive circuit layer 52. The electronic component 63 may be a resistor or a capacitor.

In this embodiment, a material of the first dielectric layer 61 and the second dielectric layer 62 is resin, and the resin may be selected from polypropylene, epoxy resin, polyurethane, phenol resin, urea resin, and melamine-formaldehyde. At least one of a resin, an unsaturated resin, and polyimide.

Step eight, referring to FIG. 8, a through hole 610 is opened in the first dielectric layer 61 to expose the first conductive circuit layer 51 and the contact pad 630 of the electronic component 63, and in the second dielectric layer 62 A through hole 620 is opened to expose the second conductive circuit layer 52.

Step Nine, referring to FIG. 9, a second conductive seed layer 64 is formed on an inner wall of each of the through holes 610 and 620, and then electroplated on the first dielectric layer 61 and the second dielectric layer 62. Copper, so that a second electroplated copper layer 65 is formed on the first dielectric layer 61 and the second dielectric layer 62 respectively, and a part of the second electroplated copper layer 65 is filled with the second conductive seed Each of the through holes 610, 620 of the layer 64 forms a second conductive hole 66.

Step 10, referring to FIG. 10, a desired conductive circuit is etched in the second electroplated copper layer 65 by using an exposure and development technology, so that a first dielectric layer 61 and a second dielectric layer 62 are formed respectively. The third conductive circuit layer 71 and a fourth conductive circuit layer 72. The third conductive circuit layer 71 is electrically connected to the first conductive circuit layer 51 and the contact pad 630 of the electronic component 63 through the second conductive hole 66. The fourth conductive circuit layer 72 is electrically connected to the second conductive circuit layer 52 through the second conductive hole 66.

In this embodiment, the through holes 610 and 620 may be formed by laser drilling.

Step eleven, referring to FIG. 11, a first solder resist layer 81 and a second solder resist layer 82 are respectively formed on the third conductive circuit layer 71 and the fourth conductive circuit layer 72.

In this embodiment, the first solder resist layer 81 and the second solder resist layer 82 are ink layers or dry films.

Step twelve, referring to FIGS. 12 and 13, a heat conducting hole 91 is opened from at least one of the first solder resist layer 81 and the second solder resist layer 82, and the heat conducting hole 91 penetrates the first solder resist layer 81. , The first dielectric layer 61 and the first substrate 110, or penetrate the second solder resist layer 82, the second dielectric layer 62, and the second substrate 120, thereby exposing the thermally conductive substrate 13. Then, each thermally conductive hole 91 is filled with a thermally conductive material to form at least one thermally conductive portion 90 thermally connected to the thermally conductive substrate 13.

In this embodiment, two heat conducting holes 91 are opened from the first solder resist layer 81 (that is, the heat conducting holes 91 are located on the same side, as shown in FIG. 10). The thermally conductive material filled in the thermally conductive portion 90 is similar to the material of the thermally conductive substrate, and has a thermal conductivity of K2, and K2 ≧ K1.

In another embodiment, a heat conducting hole 91 is opened from the first solder resist layer 81 and the second solder resist layer 82 (that is, the heat conducting holes 91 are located on different sides, as shown in FIG. 11), and The thermal conductive holes 91 opened from the solder resist layer 81 and the thermal conductive holes 91 opened from the second solder resist layer 82 are staggered.

The projected area of the electronic component 63 on the thermally conductive substrate 13 is A1, and the contact area of the two thermally conductive portions 90 and the thermally conductive substrate 13 is A2, and A2 ≧ A1.

Step thirteen, please refer to FIG. 14, an end portion of each thermally conductive portion 90 away from the thermally conductive substrate 13 is covered with a heat sink 92, so that the heat sink 92 and the thermally conductive substrate 13 conduct heat through the thermally conductive portion 90. Sexually connected to obtain the circuit board 100. Wherein, when heat conducting holes 91 are opened from the first solder resist layer 81, the ends of each heat conducting hole 91 may be covered by a single heat sink 92.

In this embodiment, the thermal conductivity of the heat sink 92 is K3, and K3 ≧ K2. The material of the heat sink 92 is metal. More specifically, the material of the heat sink 92 may be selected from at least one of gold, silver, copper, lead, nickel, and tin.

Referring to FIG. 14, a first embodiment of the present invention further provides a circuit board 100. The circuit board 100 includes a first substrate 110, a thermally conductive substrate 13, and a second substrate 120 stacked in this order. A cavity 112 is formed in the first substrate 110. At least one first conductive hole 23 penetrates the first substrate 110, the second substrate 120, and the thermally conductive substrate 13. The inner wall of each of the conductive holes 23 and the inner wall of the cavity 112 includes a first conductive seed layer 22.

A first conductive circuit layer 51 and a second conductive circuit layer 52 are formed on the first substrate 110 and the second substrate 120, respectively. The first conductive circuit layer 51 and the second conductive circuit layer 52 are electrically connected through the first conductive hole 23. The first conductive circuit layer 51 includes a first copper foil 111 formed on the first substrate 110 and a first copper plated copper layer 40 formed on the first copper foil 111. The first copper plated copper layer 40 is further The first conductive seed layer 22 is formed on the cavity 112. The second conductive circuit layer 52 includes a second copper foil 121 formed on the second substrate 120 and a first electroplated copper layer 40 formed on the second copper foil 121. The thicknesses of the first conductive circuit layer 51 and the second conductive circuit layer 52 are both d2. The thickness of the first electroplated copper layer 40 in the cavity 112 is d2-d1.

An electronic component 63 is disposed on the first electroplated copper layer 40 in the cavity 112, and the electronic component 63 has two contact pads 630 away from the first electroplated copper layer 40 in the cavity 112.

The first conductive circuit layer 51 and the second conductive circuit layer 52 are covered with a first dielectric layer 61 and a second dielectric layer 62, respectively. The first dielectric layer 61 fills the first conductive circuit layer 51 and The gap between the electronic components 63 and the second dielectric layer 62 fill the gap between the second conductive circuit layers 52.

The first dielectric layer 61 defines a second conductive hole 66 for exposing the first conductive circuit layer 51 and the contact pad 630 of the electronic component 63. A second conductive hole 66 is defined in the second dielectric layer 62 to expose the second conductive circuit layer 52. An inner wall of each of the second conductive holes 66 includes a second conductive seed layer 630.

A third conductive circuit layer 71 and a fourth conductive circuit layer 72 are formed on the first dielectric layer 61 and the second dielectric layer 62, respectively. The third conductive circuit layer 71 is electrically connected to the first conductive circuit layer 51 and the contact pad 630 of the electronic component 63 through the second conductive hole 66. The fourth conductive circuit layer 72 is electrically connected to the second conductive circuit layer 52 through the second conductive hole 66.

A first solder resist layer 81 and a second solder resist layer 82 are formed on the third conductive circuit layer 71 and the fourth conductive circuit layer 72, respectively. A heat conducting hole 91 is opened at least from one of the first solder resist layer 81 and the second solder resist layer 82, and the heat conducting hole 91 penetrates the first solder resist layer 81, the first dielectric layer 61 and the first The substrate 110 or the second solder resist layer 82, the second dielectric layer 62, and the second substrate 120 are exposed to expose the thermally conductive substrate 13, and the thermally conductive hole 91 is filled with a thermally conductive material to form at least one thermally conductive material.部 90。 90.

An end of each heat conducting portion 90 remote from the heat conducting substrate 13 is covered with a heat sink 92, and the heat sink 92 is thermally connected to the heat conducting substrate 13 through the heat conducting portion 90.

A second embodiment of the present invention provides a method for manufacturing a circuit board 100 ′, which is different from the method for manufacturing the circuit board 100 in the first embodiment described above. The first conductive seed layer is not formed in the cavity 112. 22 and the first electroplated copper layer 40, specifically, in step three: referring to FIG. 15, at least one of the circuit substrate 20 except the cavity 112 is opened through the single panel 11 and the second After the single panel 12 and the opening 21 of the thermally conductive substrate 13, a photoresist 113 is covered on the cavity 112, and a first conductive seed layer 22 is formed on the inner wall of each of the openings 21. The photoresist 113 can be used to prevent copper from being deposited on the inner wall of the cavity 112 during copper electroplating.

Referring to FIG. 16, a second embodiment of the present invention further provides a circuit board 100 ′. Unlike the above-mentioned circuit board 100, the first conductive seed layer 22 and the first electroplated copper are not formed in the cavity 112. The layer 40, that is, the electronic component 63 directly contacts the bottom of the cavity 112.

Since the electronic component 63 is buried in the cavity 112, the thickness of the entire product can be reduced. The heat generated by the electronic component 63 can be dissipated to the external environment through the thermally conductive substrate 13, the thermally conductive portion 90 and the heat sink 92 in order. Since the heat can be buffered when the heat reaches the thermally conductive substrate 13, thermal expansion of the core layer can be avoided.

Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that the technical solution of the present invention Modifications or equivalent replacements should not depart from the spirit and scope of the technical solution of the present invention.

11‧‧‧The first single panel

12‧‧‧Second single panel

13‧‧‧ Thermally conductive substrate

20‧‧‧circuit board

21‧‧‧ opening

22‧‧‧ the first conductive seed layer

23‧‧‧first conductive hole

30‧‧‧graphic photoresist layer

40‧‧‧The first copper plating

51‧‧‧The first conductive circuit layer

52‧‧‧Second conductive circuit layer

61‧‧‧First dielectric layer

62‧‧‧Second dielectric layer

63‧‧‧Electronic components

64‧‧‧Second conductive seed layer

65‧‧‧Second electroplated copper layer

66‧‧‧Second conductive hole

71‧‧‧ the third conductive circuit layer

72‧‧‧ Fourth conductive circuit layer

81‧‧‧First solder resist

82‧‧‧Second solder mask

90‧‧‧Heat conduction department

91‧‧‧Heat conduction hole

92‧‧‧ heat sink

100, 100’‧‧‧ circuit board

110‧‧‧first substrate

111‧‧‧The first copper foil

112‧‧‧ Cavity

120‧‧‧second substrate

121‧‧‧Second copper foil

610,620‧‧‧through hole

630‧‧‧contact pad

FIG. 1 is a schematic structural diagram of a first single panel, a second single panel, and a thermally conductive substrate used in a method for manufacturing a circuit board according to a preferred embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a circuit substrate obtained by laminating the first single panel, the second single panel, and a thermally conductive substrate shown in FIG. 1.

FIG. 3 is a schematic diagram of a structure after openings are formed in the circuit substrate shown in FIG. 2 and a first conductive seed layer is formed.

FIG. 4 is a schematic structural diagram of a patterned photoresist layer covered on both sides of the circuit substrate shown in FIG. 3.

FIG. 5 is a schematic structural diagram of electroplating copper in the opening of the patterned photoresist layer shown in FIG. 4 to form a first electroplated copper layer.

FIG. 6 is a schematic structural diagram of etching the first electroplated copper layer shown in FIG. 5 to obtain a first conductive circuit layer and a second conductive circuit layer.

FIG. 7 is a schematic structural diagram of an electronic component placed in the cavity of the first single panel shown in FIG. 6 and the first dielectric layer and the second dielectric layer are laminated.

FIG. 8 is a schematic diagram of a structure after a through hole is opened in the first dielectric layer and the second dielectric layer shown in FIG. 7.

FIG. 9 is a schematic structural diagram of forming a second conductive seed layer in the through hole shown in FIG. 8 and electroplating copper on the first dielectric layer and the second dielectric layer to form a second electroplated copper layer.

FIG. 10 is a schematic structural view of the second electroplated copper layer shown in FIG. 9 to obtain a third conductive circuit layer and a fourth conductive circuit layer.

FIG. 11 is a schematic structural diagram of a first solder resist layer and a second solder resist layer formed on the third conductive circuit layer and the fourth conductive circuit layer shown in FIG. 10.

FIG. 12 is a schematic structural diagram of a thermal conductive hole opened from the first solder resist layer shown in FIG. 11 and filled with a thermal conductive material to form a thermal conductive portion.

FIG. 13 is a schematic structural diagram of a thermal conductive hole opened from a first solder resist layer and a second solder resist layer shown in FIG. 11 and filled with a thermally conductive material to form a thermally conductive portion.

FIG. 14 is a schematic structural diagram of a circuit board obtained by covering an end portion of a heat conducting portion shown in FIG. 12 with a heat sink.

FIG. 15 is a schematic structural view of another embodiment in which an opening is formed in the circuit substrate shown in FIG. 2 and a first conductive seed layer is formed, and a cavity of the first single-panel is covered with a photoresist. .

FIG. 16 is a schematic structural diagram of another circuit board obtained on the circuit substrate shown in FIG. 15.

Claims (14)

A method for manufacturing a circuit board includes: providing a circuit substrate, the circuit substrate including a first single panel, a thermally conductive substrate, and a second single panel laminated in sequence; a cavity penetrating the first single panel; The first single panel includes a first copper foil disposed away from the thermally conductive substrate, and the second single panel includes a second copper foil disposed away from the thermally conductive substrate; on the first copper foil and the second copper foil Forming a first electroplated copper layer by electroplating; etching the first electroplated copper layer and the first copper foil and the second copper foil located between the first electroplated copper layers to obtain a first conductive circuit layer and a A second conductive circuit layer; placing an electronic component in the cavity, and laminating a first dielectric layer and a second dielectric layer on the first conductive circuit layer and the second conductive circuit layer, respectively; A third conductive circuit layer and a fourth conductive circuit layer are formed on the first dielectric layer and the second dielectric layer, respectively. The third conductive circuit layer, the first conductive circuit layer, and the electronic component are electrically conductive. Connected, the fourth conductive circuit layer and the second conductive The circuit layers are electrically connected; a first solder mask layer and a second solder mask layer are formed on the third conductive circuit layer and the fourth conductive circuit layer, respectively; and at least from the first solder mask layer and the second solder mask layer One of the solder resist layers is provided with a thermally conductive hole penetrating the first solder resist layer and the first dielectric layer, or the second solder resist layer and the second dielectric layer, thereby exposing the thermally conductive substrate. Then, each thermally conductive hole is filled with a thermally conductive material to form at least one thermally conductive portion thermally connected to the thermally conductive substrate, thereby obtaining the circuit board. The method for manufacturing a circuit board according to item 1 of the scope of patent application, further comprising: covering a heat sink at an end of each heat conducting portion remote from the heat conducting substrate, so that the heat sink and the heat conducting substrate are borrowed. It is thermally connected by the heat-conducting part. The method for manufacturing a circuit board according to item 1 of the scope of patent application, wherein the thermally conductive material of the thermally conductive portion and the material of the thermally conductive base material are both selected from a nano-carbon material-filled thermally conductive resin composition and an epoxy-based thermally conductive resin. At least one of a composition, a polycarbonate-based thermally conductive resin composition, and an acrylic thermally conductive resin composition, the thermal conductivity of the thermally conductive resin composition is K1, and the thermal conductivity of the thermally conductive material of the thermally conductive portion is K2, K2 ≥ K1 . The method for manufacturing a circuit board according to item 1 of the scope of patent application, wherein before the step "plating a first copper plating layer on the first copper foil and the second copper foil", the method further includes: before the circuit substrate At least one opening through the first veneer, the second veneer, and the thermally conductive substrate is opened in a region other than the cavity; and an inner wall of each of the openings and an inner wall of the cavity A first conductive seed layer is formed. The method for manufacturing a circuit board according to item 4 of the scope of patent application, wherein the step "plating a first copper plating layer on the first copper foil and the second copper foil" further includes: The copper foil and the second copper foil are covered with a patterned photoresist layer, and an opening defined by the patterned photoresist layer is used to expose a part of the first copper foil and the second copper foil, and the first copper foil is formed. The openings of the conductive seed layer and the cavity in which the first conductive seed layer is formed; copper is plated on the exposed areas of the first copper foil and the second copper foil, so that The first copper plating layer is formed on the copper foil and the second copper foil, and a part of the first copper plating layer is filled in the openings in which the first conductive seed layer is formed to form an electrode for electrical The first conductive holes that are connected to the two first electroplated copper layers are partially connected, and a part of the first electroplated copper layers is further formed in the cavity; and the pattern photoresist layer is removed. The method for manufacturing a circuit board according to item 4 of the scope of patent application, wherein the step "plating a first copper plating layer on the first copper foil and the second copper foil" further includes: on the cavity Covering a photoresist; covering the first copper foil and the second copper foil with a graphic photoresist layer respectively, and openings defined by the graphic photoresist layer are used to expose the first copper foil and the second copper foil A part of the area, and the openings where the first conductive seed layer is formed; copper is plated on the exposed areas of the first copper foil and the second copper foil, so that the first copper foil and the first copper foil are The first copper electroplated layer is formed on two copper foils respectively, and a part of the first copper electroplated layer is filled in the openings in which the first conductive seed layer is formed to form two first electroplated copper layers for electrical connection. A first conductive hole of a copper plating layer; removing the photoresist and the pattern photoresist layer. The method for fabricating a circuit board according to item 5 or 6 of the scope of the patent application, wherein the step "forms a third conductive circuit layer and a fourth conductive layer on the first dielectric layer and the second dielectric layer, respectively. The “circuit layer” further includes: opening a through hole in the first dielectric layer to expose the first conductive circuit layer and the electronic component, and opening a through hole in the second dielectric layer to expose the second conductive circuit layer Forming a second conductive seed layer on the inner wall of each of the through holes, and then electroplating copper on the first dielectric layer and the second dielectric layer, so that the first dielectric layer and the first dielectric layer A second electroplated copper layer is respectively formed on the two dielectric layers, and a part of the second electroplated copper layer is filled in each of the through holes where the second conductive seed layer is formed to form a second conductive hole; The exposure and development technology etches the required conductive circuits in the second electroplated copper layer, thereby forming the third conductive circuit layer and the fourth conductive circuit layer on the first dielectric layer and the second dielectric layer, respectively. , Wherein the third conductive circuit layer passes through the second conductive hole The first wiring layer and the electronic component is electrically connected to a fourth wiring layer by the second conductive via connected to the second wiring layer is electrically conductive. The method for manufacturing a circuit board according to item 1 of the scope of patent application, wherein a projection area of the electronic component on the thermally conductive substrate is A1, and a contact area of any two thermally conductive portions and the thermally conductive substrate is A2, A2 ≥A1. A circuit board includes a first substrate, a thermally conductive substrate, and a second substrate that are sequentially stacked. The first substrate has a cavity formed therethrough, and an electronic component is disposed in the cavity. The first substrate and A first conductive circuit layer and a second conductive circuit layer are formed on the second substrate, respectively, and the first conductive circuit layer and the second conductive circuit layer are covered with a first dielectric layer and a second dielectric layer, respectively. A third conductive circuit layer and a fourth conductive circuit layer are respectively formed on the first dielectric layer and the second dielectric layer, and the third conductive circuit layer is electrically connected to the first conductive circuit layer and the electronic component; Connection, the fourth conductive circuit layer is electrically connected to the second conductive circuit layer, and the third conductive circuit layer and the fourth conductive circuit layer are respectively formed with a first solder resist layer and a second solder resist layer, at least A thermal conductive hole is opened from one of the first solder resist layer and the second solder resist layer, and the thermal conductive hole penetrates the first solder resist layer and the first dielectric layer, or penetrates the second solder resist layer and the first solder resist layer. A second dielectric layer, thereby exposing the thermally conductive substrate The thermal vias are filled with a thermally conductive material, to form at least a thermally conductive portion. The circuit board according to item 9 of the scope of patent application, wherein an end of each heat conducting portion remote from the heat conducting substrate is covered with a heat sink, and the heat sink is thermally connected to the heat conducting substrate through the heat conducting portion. . The circuit board according to item 9 of the scope of patent application, wherein at least one first conductive hole penetrates the first substrate, the second substrate, and the thermally conductive substrate, and an inner wall of each of the conductive holes includes a first The conductive seed layer, the first conductive circuit layer and the second conductive circuit layer are electrically connected through the first conductive hole. The circuit board according to item 11 of the scope of patent application, wherein the first conductive circuit layer includes a first copper foil formed on the first substrate and a first electroplated copper formed on the first copper foil. Layer, the second conductive circuit layer includes a second copper foil formed on the second substrate and a first electroplated copper layer formed on the second copper foil. According to the circuit board of claim 12, wherein the inner wall of the cavity is also formed with the first conductive seed layer, and the first electroplated copper layer is further formed on the first conductive layer of the cavity. The seed layer is so that the electronic component is located on the first electroplated copper layer in the cavity. The circuit board according to item 11 of the scope of patent application, wherein the first dielectric layer is provided with a second conductive hole for exposing the first conductive circuit layer and the electronic component, and the second dielectric layer is provided in the first dielectric layer. There are second conductive holes for exposing the second conductive circuit layer, and an inner wall of each of the second conductive holes includes a second conductive seed layer, and the third conductive circuit layer passes the second conductive hole and The first conductive circuit layer and the electronic component are electrically connected, and the fourth conductive circuit layer is electrically connected to the second conductive circuit layer through the second conductive hole.