TW201909550A - Oscillator and control method - Google Patents

Abstract

An oscillator includes a voltage controlled oscillating circuit and a processing circuit. The voltage controlled oscillating circuit generates an oscillating frequency according to a digital signal. When the digital signal has a first signal value, the oscillating frequency is a first oscillating frequency. The processing circuit determines a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency, to adjust the oscillating frequency to a second oscillating frequency. The processing circuit further performs an interpolation according to a first frequency difference value between the target oscillating frequency and the first oscillating frequency and a second frequency difference value between the second oscillating frequency and the first oscillating frequency to determine a target signal value of the digital signal, in order to adjust the oscillating frequency to the destination oscillating frequency.

Description

   Oscillator and control method   

The embodiments described in this disclosure are related to an oscillator, and more particularly to a voltage-controlled oscillator circuit and a method for controlling its oscillation frequency.

The oscillation frequency of the oscillator is determined by the inductance and capacitance of the resonant tank. Generally speaking, the oscillation frequency of the oscillator can be adjusted by controlling the capacitor value. However, when the environmental conditions (such as temperature and voltage) change, it takes a lot of time to determine the appropriate control signal to set the capacitor value, so that the oscillator operates at the expected oscillation frequency.

One embodiment of the present disclosure relates to an oscillator. The oscillator includes a voltage-controlled oscillation circuit and a processing circuit. The voltage-controlled oscillation circuit is used to generate an oscillation frequency according to a digital signal. When the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency. The processing circuit is configured to determine a second signal value of the digital signal according to the first oscillation frequency and a target oscillation frequency to adjust the oscillation frequency to a second oscillation frequency. The processing circuit further performs an interpolation operation between a first frequency difference and a second frequency difference to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency The difference is a difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is a difference between the second oscillation frequency and the first oscillation frequency.

One embodiment of the present disclosure relates to a control method. The control method includes: generating an oscillation frequency of a voltage controlled oscillation circuit according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; according to the first oscillation frequency and a target oscillation frequency Determining a second signal value of the digital signal to adjust the oscillation frequency to a second oscillation frequency; and performing an interpolation operation based on a first frequency difference and a second frequency difference to determine a target signal of the digital signal Value to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is a difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference is the second oscillation frequency and The difference between the first oscillation frequencies.

In summary, through the at least one embodiment described above, the processing circuit can quickly determine the target signal value to control the voltage-controlled oscillation circuit to operate at the target oscillation frequency.

100‧‧‧ Oscillator

102‧‧‧Voltage Controlled Oscillation Circuit

104‧‧‧Processing circuit

106‧‧‧Register

202‧‧‧Variable capacitor array

500‧‧‧Control method

S520, S540, S560, S580 ‧‧‧ steps

LUT‧‧‧ Lookup Table

C _VAR 1, C _VAR 2, C1, C2, C3, C4, C5, C6, C7‧‧‧ capacitors

N1, N2, N3‧‧‧ nodes

M1, M2, M3, SW1, SW2, SW3‧‧‧ switches

V _SW ‧‧‧ Digital Signal

S _SW 1, S _SW 2‧‧‧ Signal value

S _SW 3‧‧‧ Target signal value

S [1], S [2], S [3] ‧‧‧bits

V _TUNE , V _B ‧‧‧ Control voltage

V _DD ‧‧‧ Supply voltage

F, F1, F2‧‧‧oscillation frequency

F _DES ‧‧‧Target Oscillation Frequency

△ F1, △ F2‧‧‧ Frequency difference

L1‧‧‧Inductor

In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the description of the drawings is as follows: FIG. 1 is a schematic diagram of an oscillator according to some embodiments of the present disclosure; FIG. 2 is a schematic diagram of the voltage-controlled oscillation circuit of FIG. 1 according to some embodiments of the present disclosure; FIG. 3 is a schematic diagram of the variable capacitor array of FIG. 2 according to some embodiments of the present disclosure; FIG. 4 is a schematic diagram showing the relationship between the first oscillation frequency, the second oscillation frequency, and the target oscillation frequency according to some embodiments of the present disclosure; and FIG. 5 is a control method according to some embodiments of the present disclosure. Flowchart.

The following is a detailed description with examples and the accompanying drawings, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of the structure operation is not intended to limit the order of its execution, and any recombination of components The structure of the device and the device with the same effect are all covered by the present disclosure. In addition, the drawings are for illustration purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The term "coupling" used in this article can also refer to "electrical coupling", and the term "connection" can also mean "electrical connection". "Coupled" and "connected" can also mean that two or more components cooperate or interact with each other.

FIG. 1 is a schematic diagram of an oscillator 100 according to some embodiments of the present disclosure. In some embodiments, the oscillator 100 includes a voltage-controlled oscillation circuit 102, a processing circuit 104, and a register 106. The processing circuit 104 is coupled to the voltage-controlled oscillation circuit 102 and the register 106. The processing circuit 104 can provide a digital signal V _SW to the voltage-controlled oscillation circuit 102. The voltage-controlled oscillation circuit 102 generates a corresponding oscillation frequency F according to the digital signal V _SW . The processing circuit 104 can detect the oscillation frequency F when the voltage-controlled oscillation circuit 102 operates based on the digital signal V _SW . For example, in some embodiments, the processing circuit 104 includes a counter. This counter is used for counting according to the signal with the oscillation frequency F generated by the voltage-controlled oscillation circuit 102 to generate different values. In this way, the processing circuit 104 can detect the oscillation frequency F according to the value.

The register 106 is used to record the correspondence between different signal values of the digital signal V _SW and the oscillation frequency F. For example, the above-mentioned corresponding relationships may be implemented in the register 106 by a look-up table (LUT) or the like. In some embodiments, when the processing circuit 104 detects the oscillation frequency F, the processing circuit 104 may read the signal value of the digital signal V _SW corresponding to the oscillation frequency F from the look-up table LUT. For example, the processing circuit 104 may read the signal value of the digital signal V _{SW to} the corresponding address of the lookup table LUT according to the value generated by the counter. The above-mentioned arrangement manners of the processing circuit 104 and the register 106 are merely examples, and the present disclosure is not limited thereto.

FIG. 2 is a schematic diagram of the voltage-controlled oscillation circuit 102 of FIG. 1 according to some embodiments of the present disclosure. In some embodiments, the voltage-controlled oscillation circuit 102 includes a variable capacitor array 202, an inductor L1, a capacitor C _VAR 1, a capacitor C _VAR 2, a switch M1, a switch M2, and a switch M3. The inductor L1 receives a supply voltage V _DD . The variable capacitor array 202 and the inductor L1 are coupled to a node N1 and a node N2. The variable capacitor array 202 receives a digital signal V _SW and determines the capacitance of the variable capacitor array 202 according to the digital signal V _SW . The capacitor C _VAR 1 is coupled between the node N1 and the node N3. The capacitor C _VAR 2 is coupled between the node N3 and the node N2. The node N3 receives the control voltage V _TUNE to determine the capacitance values of the capacitors C _VAR 1 and C _VAR 2. For example, in some embodiments, capacitor C _VAR 1 and capacitor C _VAR 2 may be implemented by a varactor. In some embodiments, the varactor can be implemented by a transistor. In this example, the gate of the transistor used to implement the transformer receives the control voltage V _TUNE . As such, the control voltage V _TUNE changes, and the capacitance values of the capacitors C _VAR 1 and C _VAR 2 change accordingly. The above implementations of the capacitor C _VAR 1 and the capacitor C _VAR 2 are merely examples, and the present disclosure is not limited thereto.

The switches M1 ~ M2 are cross-coupled. That is, a control terminal of the switch M1 and one terminal of the switch M2 are coupled to the node N2, and a control terminal of the switch M2 and one terminal of the switch M1 are coupled to the node N1. The switch M3 is coupled between the switch M1 and the ground, and is coupled between the switch M2 and the ground. The switch M3 receives the control voltage V _B and is used as a constant current source. In some embodiments, the variable capacitance array 202, the inductor L1, the capacitor C _VAR 1, and the capacitor C _VAR 2 are configured as a resonant circuit. The switches M1 ~ M2 are set to generate a negative impedance to cancel the parasitic resistance of the resonant circuit. In this way, the voltage-controlled oscillation circuit 102 can start to generate a signal having an oscillation frequency F.

In some embodiments, the oscillation frequency F of the voltage-controlled oscillation circuit 102 can be obtained by the following formula (1):

Wherein C is the equivalent capacitance value of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2, and L is the inductance value of the inductance L1.

As described previously, the capacitance of the variable capacitor array 202 is determined based on the digital signal V _SW . When the capacitance value of the variable capacitor array 202 is changed, C in the formula (1) will be changed accordingly, thereby changing the oscillation frequency F of the voltage-controlled oscillation circuit 102 accordingly. In other words, the oscillation frequency F of the voltage-controlled oscillation circuit 102 can be changed through the digital signal V _SW .

The above-mentioned voltage-controlled oscillation circuit 102 is only used as an example, and the arrangement of other various voltage-controlled oscillation circuits 102 is also within the scope of the present disclosure.

FIG. 3 is a schematic diagram of the variable capacitor array 202 shown in FIG. 2 according to some embodiments of the present disclosure. In some embodiments, the variable capacitor array 202 is an N-bit variable capacitor array. N is a positive integer. The n-th bit of the variable capacitance array 202 corresponds to 2 ^(n-1) capacitors. n is a positive integer and is less than or equal to N.

In some embodiments, the signal value of the digital signal V _SW is composed of multiple bits, which respectively correspond to an N-bit variable capacitor array. Taking the example in FIG. 3, the first bit S [1] of the signal value of the digital signal V _SW corresponds to the capacitor C1. The second bit S [2] of the signal value of the digital signal V _SW corresponds to the capacitors C2 to C3. The third bit S [3] of the signal value of the digital signal V _SW corresponds to the capacitors C4 to C7.

Specifically, the capacitor C1 and the switch SW1 are connected in series between the node N1 and the node N2, where the switch SW1 is controlled by the first bit S [1] of the signal value of the digital signal V _SW . Capacitor C2 and capacitor C3 are connected in parallel, and capacitors C2 ~ C3 and switch SW2 are connected in series between node N1 and node N2. Switch SW2 is controlled by the second bit S [2] of the signal value of digital signal V _SW . Capacitors C4 ~ C7 are connected in parallel with each other, and capacitors C4 ~ C7 and switch SW3 are connected in series between node N1 and node N2. Switch SW3 is controlled by the third bit S [3] of the signal value of digital signal V _SW . By analogy, the setting manner between the N-bit variable capacitor array and the digital signal V _SW can be derived.

With the above configuration, the capacitance value of the variable capacitor array 202 can be changed by adjusting the digital signal V _SW . When the capacitance value of the variable capacitance array 202 changes, the equivalent capacitance values of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2 will change accordingly. Based on the above formula (1), when the equivalent capacitance value changes, the oscillation frequency F of the voltage-controlled oscillation circuit 102 will change accordingly. The above-mentioned variable capacitor array 202 is merely an example, and various other ways of setting the variable capacitor array 202 are also covered by the present disclosure.

FIG. 4 is a schematic diagram showing the relationship between the oscillation frequency F1, the oscillation frequency F2, and the target oscillation frequency F _DES according to some embodiments of the present disclosure. FIG. 5 is a flowchart of a control method 500 according to some embodiments of the present disclosure. Please refer to Figures 1 to 5 below.

In step S520, the processing circuit 104 detects the oscillation frequency F1 when the voltage-controlled oscillation circuit 102 operates based on the signal value S _SW1 of the digital signal V _SW . In some embodiments, when the oscillator 100 is powered on, the voltage-controlled oscillation circuit 102 generates an initial oscillation frequency (for example, the oscillation frequency F1) according to the signal value S _SW 1 of the digital signal V _SW . In some embodiments, the processing circuit 104 reads the signal value S _SW 1 of the digital signal V _SW corresponding to the oscillation frequency F 1 from the look-up table LUT in the register 106 according to the oscillation frequency F 1.

In step S540, the processing circuit 104 adjusts the digital signal V _SW from the signal value S _SW 1 to the signal value S _SW 2 according to the oscillation frequency F1 and the target oscillation frequency F _DES . In some embodiments, the processing circuit 104 includes a frequency detector for comparing the oscillation frequency F1 and the target oscillation frequency F _DES . When the oscillation frequency F1 is different from the target oscillation frequency F _DES , the processing circuit 104 adjusts the signal value S _SW 1 to the signal value S _SW 2 according to a preset value M.

For example, when the oscillation frequency F1 is smaller than the target oscillation frequency F _DES , the processing circuit 104 generates a signal value S _SW 2 to reduce the capacitance value of the variable capacitor array 202. In this way, the oscillation frequency F1 can be increased to a higher oscillation frequency. Alternatively, when the oscillation frequency F1 is greater than the target oscillation frequency F _DES , the processing circuit 104 generates a signal value S _SW 2 to increase the capacitance value of the variable capacitor array 202. In this way, the oscillation frequency F1 can be reduced.

If the switches SW1 to SW3 of the variable capacitor array 202 are implemented by N-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F _DES , the processing circuit 104 subtracts the signal value S _SW 1 from the preset value M. (Addition) to produce a signal value S _SW 2. Assume that the signal value S _SW 1 is 111 (that is, S [3] = 1, S [2] = 1, S [1] = 1). In this case, the switches SW1 to SW3 are all turned on. At this time, the capacitors C1 to C7 are connected in series with each other. The capacitance value of the variable capacitance array 202 is substantially equal to the sum of the capacitance values of the capacitors C1 to C7. If the oscillation frequency F1 is smaller than the target oscillation frequency F _DES (as shown in FIG. 4), the processing circuit 104 subtracts the digital signal V _SW 1 from the preset value M (for example, M = 6, and the corresponding bit is 110) to The generated signal value S _SW 2 is 001. In this case, the switch SW1 is turned on, but the switches SW2 and SW3 are turned off. At this time, the capacitance value of the variable capacitance array 202 is substantially equal to the capacitance value of the capacitor C1. In other words, the capacitance value of the variable capacitor array 202 decreases to increase the oscillation frequency F1 to the oscillation frequency F2.

Or, in other examples, if the switches SW1 to SW3 of the variable capacitor array 202 are implemented by P-type transistors, when the oscillation frequency F1 is less than (greater than) the target oscillation frequency F _DES , the processing circuit 104 sends a digital signal V _SW 1 is added (subtracted) to a preset value M to generate a digital signal V _SW 2. The operations here can be deduced by analogy according to the above paragraphs, so the description will not be repeated.

In some embodiments, the capacitance values of the capacitors C1 to C7 are the same or partially the same. In some embodiments, the preset value M can be adjusted according to the capacitance values of the capacitors C1 to C7. For example, when the capacitance values of the capacitors C1 to C7 are the same and the larger the capacitance value, the preset value M can be set smaller. In some embodiments, the preset value M may also be determined according to the linearity requirement of the oscillator 100. By considering the linearity requirement of the oscillator to set the preset value M, a more accurate oscillation frequency F2 can be obtained, so as to improve the accuracy of the interpolation operation mentioned later.

In step S560, the processing circuit 104 detects the oscillation frequency F2 when the voltage-controlled oscillation circuit 102 operates based on the signal value S _SW 2 of the digital signal V _SW . In some embodiments, when the signal value of the digital signal V _SW is adjusted from S _SW 1 to S _SW 2, the variable capacitor array 202 generates an oscillation frequency F2 based on the signal value S _SW 2 of the digital signal V _SW . The counter of the processing circuit 104 can detect the oscillation frequency F2 generated by the variable capacitor array 202 accordingly.

In step S580, the processing circuit 104 performs an interpolation operation according to the frequency difference value ΔF2 and the frequency difference value ΔF1 to determine a target signal value S _SW 3 corresponding to the target oscillation frequency F _DES .

In some embodiments, the processing circuit 104 calculates the difference between the oscillation frequency F2 and the oscillation frequency F1 to determine the frequency difference value ΔF1, and calculates the difference between the target oscillation frequency F _DES and the oscillation frequency F1 to determine the frequency difference value Δ F2. As shown in FIG. 3, in some embodiments, the processing circuit 104 may perform an interpolation operation according to the frequency difference value ΔF1 and the frequency difference value ΔF2 to efficiently determine the target signal value corresponding to the target oscillation frequency F _DES S _SW 3.

For example, the processing circuit 104 may calculate the target adjustment value P according to the frequency difference value ΔF1, the frequency difference value ΔF2, and the preset value M described above. In some embodiments, the target adjustment value P can be obtained by the following formula (2):

Based on the above formula (2), the processing circuit 104 calculates the magnitude of the signal value of the digital signal V _SW to be adjusted according to the ratio between the frequency difference ΔF2 and the frequency difference ΔF1 and the preset value M (that is, the target adjustment Value P). Next, the processing circuit 104 generates a target signal value S _SW 3 according to the target adjustment value P and the signal value S _SW 1. In some embodiments, the target signal value S _SW 3 can be obtained by the following formula (3): S _SW 3 = S _SW 1 + P ... (3)

For example, if the signal value S _SW 1 is 001 and P is 3 (its corresponding bit is 011), the target signal value S _SW 3 is 100. According to this, the processing circuit 104 transmits a digital signal V _SW having a target signal value S _SW 3 to the variable capacitor array 202 to determine the states of the switches in the variable capacitor array 202 (for example, on or off). By determining the states of the switches, the capacitance of the variable capacitor array 202 can be adjusted. As such, the equivalent capacitance values of the variable capacitance array 202, the capacitor C _VAR 1 and the capacitor C _VAR 2 can be adjusted to be substantially equal to the target capacitance value. According to this, the target capacitance value and the inductance value L of the inductor L1 can make the oscillation frequency of the voltage-controlled oscillation circuit 102 be the target oscillation frequency F _DES .

In other words, by using the above equations (2) to (3), after obtaining the two oscillation frequencies F1 and F2, the processing circuit 104 may use these oscillation frequencies F1 and F2 and their corresponding signal values S _sw 1 and S _sw 2 Quickly interpolate the target signal value S _SW 3. In some related technologies, when environmental conditions (for example, operating temperature, voltage, etc.) change, a look-up table needs to be re-established. This will take a lot of time. Compared with the related art, the processing circuit 104 can quickly determine the target signal value S _SW 3. In some embodiments, the control method 500 may be repeatedly executed multiple times to increase the accuracy of the target signal value S _SW 3.

The multiple steps of the above control method 500 are merely examples, and are not limited to be performed in the order in this example. Without departing from the operation mode and scope of the embodiments of the present disclosure, various operations under the control method 500 can be appropriately added, replaced, omitted, or performed in a different order.

In summary, through the at least one embodiment described above, the processing circuit can quickly determine the target signal value to control the voltage-controlled oscillation circuit to operate at the target oscillation frequency.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

Claims (10)

    An oscillator includes: a voltage-controlled oscillation circuit for generating an oscillation frequency according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; and a processing circuit For determining a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency to adjust the oscillating frequency to a second oscillating frequency, wherein the processing circuit is further configured for using a first frequency difference An interpolation operation is performed between the value and a second frequency difference to determine a target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is the target oscillation frequency and the first A difference between an oscillation frequency, and the second frequency difference is a difference between the second oscillation frequency and the first oscillation frequency.         The oscillator according to item 1 of the patent application range, wherein the voltage-controlled oscillation circuit includes a variable capacitor array for receiving the digital signal, and a capacitance value of the variable capacitor array is based on the Digital signal decision.         The oscillator according to item 1 of the patent application scope, wherein the processing circuit is further configured to compare the first oscillation frequency and the target oscillation frequency to adjust the digital signal.         The oscillator according to item 3 of the scope of patent application, wherein when the first oscillation frequency is different from the target oscillation frequency, the processing circuit adjusts the digital signal from the first signal value to the first signal value according to a preset value. The second signal value.         The oscillator according to item 4 of the scope of patent application, wherein when the first oscillation frequency is lower than the target oscillation frequency, a capacitance value of the variable capacitor array is reduced according to the second signal value, and when the first When the oscillation frequency is greater than the target oscillation frequency, the capacitance value of the variable capacitor array is increased according to the second signal value.         The oscillator according to item 4 of the scope of patent application, wherein when the first oscillation frequency is less than the target oscillation frequency, the processing circuit generates the second signal according to a difference between the first signal value and the preset value And when the first oscillation frequency is greater than the target oscillation frequency, the processing circuit generates the second signal value according to a sum of the first signal value and the preset value.         The oscillator according to item 4 of the scope of patent application, wherein the processing circuit is further configured to determine the product according to a product of a ratio between the first frequency difference and the second frequency difference and one of the preset values. A target adjustment value, and adding the first signal value to the target adjustment value to generate the target signal value.         The oscillator according to item 1 of the patent application scope further comprises: a register for storing a look-up table, wherein the processing circuit is further configured to read the digits from the look-up table according to the first oscillation frequency. The first signal value of the signal.         A control method includes: generating an oscillation frequency of a voltage-controlled oscillation circuit according to a digital signal, wherein when the digital signal is a first signal value, the oscillation frequency is a first oscillation frequency; and according to the first oscillation frequency And a target oscillation frequency determines a second signal value of the digital signal to adjust the oscillation frequency to a second oscillation frequency; and an interpolation operation is performed according to a first frequency difference and a second frequency difference to determine A target signal value of the digital signal to adjust the oscillation frequency to the target oscillation frequency, wherein the first frequency difference is a difference between the target oscillation frequency and the first oscillation frequency, and the second frequency difference Is the difference between the second oscillation frequency and the first oscillation frequency.         The control method according to item 9 of the scope of patent application, wherein adjusting the digital signal comprises: determining the target adjustment value according to a ratio and a preset value between the first frequency difference and the second frequency difference. ; Adding the first signal value and the target adjustment value to generate the target signal value; and adjusting the digital signal to the target signal value to adjust the oscillation frequency to the target oscillation frequency.