TW201836098A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure including a circuit carrier, at least one chip and an encapsulation layer is provided. The circuit carrier includes a dielectric layer, a plurality of conductive pillars, a circuit layer and a plurality of passivation layers. The conductive pillars penetrate the dielectric layer. Each of the conductive pillars has a first end and a second end opposite to each other. The second end protrudes from the dielectric layer. The circuit layer is deposed on the dielectric layer. The circuit layer is connected to the first end. The passivation layers cover the second end portions of the conductive pillars respectively. The material of the passivation layers is different from that of the conductive pillars. The chip is disposed on the dielectric layer. The chip and the circuit layer are disposed at the same side of the dielectric layer. The chip is electrically connected to the circuit layer. The encapsulation layer is deposed on the dielectric layer and covers the chip. A manufacturing method of a semiconductor package structure is also provided.

Description

Semiconductor package structure and method of manufacturing same

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

With the advancement of technology, the size of electronic products introduced on the market has been shrinking, and the trend toward light, short, and portable is growing. In order to meet the trend toward thinner and lighter electronic products, the size of semiconductor package structures installed in electronic products has also been shrinking.

In the prior art, the package substrate of the semiconductor package structure is composed of a core layer and a circuit layer symmetrically disposed on opposite sides of the core layer, and the thickness of the overall structure is not easily reduced, and it is difficult to meet the development trend of the electronic product toward lightness and thinness. Therefore, a semiconductor package structure with or without a coreless layer is proposed, and the fabrication steps are as follows: First, a first conductive metal layer is formed on the carrier. Next, a dielectric layer is formed on the first conductive metal layer, and a via hole is formed through the dielectric layer, wherein the via hole is connected to the first conductive metal layer. Next, a second conductive metal layer is formed on the dielectric layer, wherein the first conductive metal layer and the second conductive metal layer are respectively located on opposite sides of the dielectric layer, and the second conductive metal layer is connected to the via hole. Next, a solder resist layer is formed on the second conductive metal layer, and the second conductive metal layer is partially exposed. Then, the wafer is electrically connected to the second conductive metal layer by wire bonding or Flip-Chip, and an encapsulation layer is formed on the solder resist layer to cover at least the wafer and the wafer and An electrical junction of the second conductive metal layer. After that, remove the carrier board. So far, the fabrication of the semiconductor package structure without the core layer has been substantially completed.

Taking a semiconductor package structure without a core layer having a single-layer line as an example, after removing the carrier, the first conductive metal can be further removed by etching. Thereafter, a solder bump is formed on the via hole and a reflow process is performed to form a solder ball, and the solder ball and the second conductive metal layer are respectively located on opposite sides of the dielectric layer. However, in the foregoing fabrication process, the etching depth when the first conductive metal is removed is not easily controlled, and the results of the subsequent Ball Shear Test and Ball Pull Test are easily affected. Therefore, how to simplify the manufacturing process of the semiconductor package structure without the core layer to improve its production efficiency and yield has become one of the urgent problems to be solved.

The present invention provides a method of fabricating a semiconductor package structure that can improve fabrication efficiency and yield.

The present invention provides a semiconductor package structure that has good reliability.

The present invention provides a semiconductor package structure including a wiring carrier, at least one wafer, and an encapsulation layer. The line carrier includes a dielectric layer, a plurality of conductive pillars, a wiring layer, and a plurality of protective layers. The conductive pillars extend through the dielectric layer. Each of the conductive posts has opposing first and second ends. The second end protrudes from the dielectric layer. The circuit layer is on the dielectric layer. The circuit layer is connected to the first end. A plurality of protective layers respectively cover the second end of the conductive pillar. The material of the protective layer is different from the material of the conductive column. The wafer is disposed on the dielectric layer. The wafer and wiring layers are on the same side of the dielectric layer. The wafer is electrically connected to the wiring layer. The encapsulation layer is disposed on the dielectric layer and covers the wafer.

The present invention provides a method of fabricating a semiconductor package structure that includes at least the following steps. A substrate is provided. A plurality of depressions are formed on the substrate. A protective layer is formed in each of the recesses. Conductive pillars are respectively formed on the respective protective layers. A dielectric layer is formed on the substrate, wherein the dielectric layer and the conductive pillar are on the same side of the substrate, and the dielectric layer exposes the conductive pillar. A circuit layer is formed on the dielectric layer, wherein the circuit layer and the substrate are on opposite sides of the dielectric layer, and the circuit layer is electrically connected to the conductive pillar. At least one wafer is disposed on the dielectric layer, and the wafer is electrically connected to the wiring layer. An encapsulation layer is formed on the dielectric layer, and the encapsulation layer encapsulates the wafer. The substrate is removed to expose the protective layer.

Based on the above, the method of fabricating the semiconductor package structure of the present invention allows one end portion of the conductive pillar penetrating through the dielectric layer to protrude outside the dielectric layer, and the end portion is covered by the protective layer. Further, the foregoing end portion can be used as a contact point for electrical connection between the subsequent semiconductor package structure and the external component, that is, the semiconductor package structure of the present invention does not need to be additionally provided with solder balls, thereby simplifying the manufacturing process and improving the manufacturing efficiency. With yield.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1I are schematic cross-sectional views showing a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. The manufacturing method of the semiconductor package structure 100 of the present embodiment includes the following steps. First, referring to FIG. 1A, a substrate 10 is provided in which the substrate 10 has a first surface 10a and a second surface 10b opposed to each other. Next, a mask layer 20 is formed on the first surface 10a of the substrate 10, wherein the mask layer 20 has a plurality of openings 21, the openings 21 exposing a portion of the first surface 10a, and the openings may be circular or Square, but the invention is not limited thereto. In this embodiment, the material of the substrate 10 may be copper or other conductive metal.

On the other hand, the mask layer 20 may be a patterned photoresist layer formed by a photolithography process, which may precede the first surface of the substrate 10 in terms of the step of fabricating the patterned photoresist layer. A full layer of photoresist material is coated, printed or transferred on 10a, i.e., the first surface 10a is completely covered by the photoresist material. Then, a portion of the photoresist material is removed through the lithography process to form a patterned photoresist layer having a plurality of openings 21. However, the present invention is not limited to forming a mask layer through a photoresist material. In other embodiments, the mask layer may be a hard mask.

Next, referring to FIG. 1B, portions of the substrate 10 exposed to the openings 21 are removed by processes such as wet etching or dry etching to form on the first surface 10a of the substrate 10. A plurality of depressions 11. In other words, the recesses 11 are respectively aligned with the openings 21. In the present embodiment, the recesses 11 are blind holes or trenches, that is, the recesses 11 do not penetrate the substrate 10.

Referring to FIG. 1C , after the recesses 11 are formed on the first surface 10 a of the substrate 10 , the protective layer 110 is respectively formed in each of the recesses 11 by electroplating, wherein each of the protective layers 110 includes a base portion 111 and sidewalls surrounding the base portion 111 . The portions 112 are connected to the bottom surfaces of the corresponding recesses 11, and the thickness of each of the base portions 111 is smaller than the depth of the corresponding recesses 11. On the other hand, each of the side wall portions 112 extends upward from the bottom surface of the corresponding recess 11 such that the top surface of each of the side wall portions 112 is at least flush with the first surface 10a of the substrate 10. In other embodiments, the top surface of each sidewall portion 112 may extend beyond the first surface 10a of the substrate 10.

Referring to FIG. 1C and FIG. 1D simultaneously, in the present example, the protective layer 110 may be a gold layer, a platinum layer, a nickel gold layer or a nickel platinum layer. After forming the protective layer 110, the conductive pillars 120 are respectively formed on the respective protective layers 110 by electroplating, wherein each of the conductive pillars 120 has opposite first end portions 120a and second end portions 120b, and each of the second end portions 120b The base portion 111 of the corresponding protective layer 110 and the side wall portion 112 are connected. That is, each of the second end portions 120b is located within the recess 11 in which the corresponding protective layer 110 is located. For example, the protective layer 110 is a nickel gold layer, which is formed by forming a gold layer in the recess 11 and then forming a nickel layer on the gold layer, and the nickel layer can be used to enhance the bonding strength between the gold layer and the conductive pillar 120. In the present embodiment, the material of the substrate 10 may be the same as the material of the conductive pillars 120, for example, copper, which is different from the material constituting the protective layer 110.

Next, referring to FIG. 1E, the mask layer 20 is removed and a dielectric layer 130 is formed on the first surface 10a of the substrate 10. The dielectric layer 130 and the conductive pillars 120 are located on the same side of the substrate 10, and are dielectrically Layer 130 exposes the end faces of first end 120a of each of conductive pillars 120. In general, the material of the dielectric layer 130 may include a ceramic or a prepreg (PP) or other suitable dielectric material, which is not limited in the present invention.

Next, referring to FIG. 1F , a circuit layer 140 is formed on the dielectric layer 130 , wherein the circuit layer 140 and the substrate 10 are located on opposite sides of the dielectric layer 130 , and the circuit layer 140 is electrically connected to the conductive pillars 120 . For example, a conductive layer (not shown) may be formed on the dielectric layer 130 by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Next, the conductive layer is patterned by a patterning process to form the wiring layer 140, and the end surface of the first end 120a of the conductive pillar 120 is covered by the wiring layer 140 to be connected to the wiring layer 140.

Next, referring to FIG. 1G and FIG. 1H simultaneously, a solder resist layer 150 is formed on the dielectric layer 130, and the solder resist layer 150 partially covers the circuit layer 140. Next, at least one wafer 160 is disposed on the dielectric layer 130, and the wafer 160 is electrically connected to the wiring layer 140. In the present embodiment, the number of wafers 160 is exemplified, but the present invention does not limit the number of wafers 160. Generally, the wafer 160 can be attached to the solder resist layer 150 through a die attached film. In this embodiment, the plurality of wires 50 are electrically connected to the wafer 160 and the wiring layer 140 by wire bonding. In another embodiment, portions of the wiring layer 140 that are exposed to the solder mask 150 may have connection pads 30 to enhance the bond strength between the circuit layer 140 and the wires 50. In other examples, the wafer 160 can be electrically connected to the wiring layer 140 by flip chip bonding.

Referring to FIG. 1H, an encapsulation layer 170 is formed on the dielectric layer 130 to encapsulate the wafer 160. For example, the encapsulation layer 170 may form a molten molding compound on the dielectric layer 130 through a molding process, and then, the molten molding compound is cooled and solidified to form the encapsulation layer 170. . In the present embodiment, the encapsulation layer 170 encapsulates the wafer 160, the wires 50, and the connection pads 30. In other embodiments, the encapsulation layer 170 encapsulates the wafer 160, the wires 50, and the wiring layer 140 exposed to the solder resist layer 150. In this way, it is possible to prevent the electrical contacts between the wires 50 and the wiring layer 140 and the electrical contacts between the wires 50 and 160 from being wetted or damaged by external forces.

Thereafter, referring to FIG. 1I, the substrate 10 is removed. So far, the fabrication of the semiconductor package structure 100 has been substantially completed. In this embodiment, the substrate 10 can be removed by an etching process, wherein the etching process can be a wet etching process, the etching solution can be an acid solution or an alkali solution, and the acid solution can be a mixture of sulfuric acid and hydrogen peroxide. Since the material of the substrate 10 may include copper, and the material of the protective layer 110 may include at least gold or platinum, when the substrate 10 is removed by the acid solution, the etching rate of the acid to the substrate 10 is greater than that of the acid to the protective layer. Etching rate of 110. As such, the protective layer 110 can serve as an etch barrier for the conductive pillars 120, so that the etching process can terminate at the protective layer 110 without continuing to etch the conductive pillars 120 covered by the protective layer 110.

The semiconductor package structure 100 includes a circuit carrier 60, a wafer 160, and an encapsulation layer 170. The circuit carrier 60 includes a dielectric layer 130, a plurality of conductive pillars 120, a circuit layer 140, and a plurality of protective layers 110, and the conductive pillars 120 are interposed. Electrical layer 130. Each of the conductive pillars 120 has an opposite first end 120a and a second end 120b, wherein end faces of the respective first ends 120a are exposed to the upper surface 131 of the dielectric layer 130, and each of the second ends 120b protrudes from the dielectric The lower surface 132 of the layer 130, and the upper surface 131 and the lower surface 132 are opposed to each other. The wiring layer 140 is located on the upper surface 131 of the dielectric layer 130 and covers the end faces of the first ends 120a of the conductive pillars 120 to be connected to the first ends 120a of the conductive pillars 120. The protective layers 110 respectively cover the second ends 120b of the conductive pillars 120, and the materials of the protective layers 110 are different from the materials of the conductive pillars 120. The wafer 160 is disposed on the dielectric layer 130 , wherein the wafer 160 and the wiring layer 140 are on the same side of the dielectric layer 130 , and the wafer 160 is electrically connected to the wiring layer 140 . The encapsulation layer 170 is disposed on the dielectric layer 130 and covers the wafer 160, the wires 50 electrically connecting the wafer 160 and the circuit layer 140, and the wiring layer 140. As such, the conductive pillars 120 protrude from the second end portion 120b of the lower surface 132 of the dielectric layer 130 and the protective layers 110 coated on the second ends 120b can serve as external conductive terminals of the semiconductor package structure 100. Without the need to additionally set up solder balls, it can simplify the process of production and improve production efficiency and yield.

Although the semiconductor package structure 100 of the present embodiment electrically connects the wires 50 to the wiring layer 140 by wire bonding, in other embodiments, the wafer 160 and the circuit layer 140 may be electrically connected by flip chip bonding. Sexual connection.

With continued reference to FIG. 1I, the end faces of the first ends 120a of the respective conductive pillars 120 may be flush with the upper surface 131 of the dielectric layer 130, and the second ends 120b of the respective conductive pillars 120 protrude from the dielectric layer 130. The lower surface 132 is such that the height H of each of the conductive pillars 120 is greater than the thickness T of the dielectric layer 130. On the other hand, the semiconductor package structure 100 further includes a solder resist layer 150, wherein the solder resist layer 150 is located between the dielectric layer 130 and the wafer 160, and the solder resist layer 150 partially covers the wiring layer 140.

2A is a schematic structural view of the conductive post of FIG. 1I. Referring to FIG. 1I and FIG. 2A simultaneously, in the embodiment, the second end portion 120b of the conductive pillar 120 is parallel to the lower surface 132 of the dielectric layer 130 and the cross-sectional area of the conductive pillar 120 is smaller than the portion of the conductive pillar 120 that penetrates the dielectric layer 130 (ie, The first end 120a) is parallel to the cross-sectional area of the lower surface 132 of the dielectric layer 130, wherein the first end 120a can be a cylinder and the second end 120b can also be a cylinder. In other embodiments, the first end 120a and the second end 120b may each be an elliptical cylinder, a semi-conical body, a square cylinder or other geometric cylinder.

As shown in FIG. 1A to FIG. 1D, since the shape of the opening 21 of the mask layer 20 projected onto the first surface 10a of the substrate 10 is circular, the first of the subsequently formed conductive pillars 120 is formed. The cross-sectional shape of the end portion 120a parallel to the first surface 10a of the substrate 10 may be a corresponding circular shape. Moreover, since the recess 11 on the substrate 10 is formed by removing a portion of the material of the substrate 10 located in the opening 21 of the mask layer 20 through an etching process, the recess 11 is parallel to the first surface 10a of the substrate 10. The cross-sectional shape may be a circle that conforms to or resembles the opening 21. On the other hand, the recess 11 forms the second end portion 120b of the conductive pillar 120 on the protective layer 110 after being partially filled with the protective layer 110, wherein the sidewall portion 112 of the protective layer 110 defines a circular opening, and The cross-sectional area of the circular opening parallel to the first surface 10a of the substrate 10 is smaller than the cross-sectional area of the opening of the mask layer 20 parallel to the first surface 10a of the substrate 10, so that the second end 120b of the conductive post 120 is parallel to The cross-sectional shape of the first surface 10a of the substrate 10 may be a corresponding circular shape, and the cross-sectional area of the second end 120b of the conductive post 120 parallel to the first surface 10a of the substrate 10 is smaller than the first end of the conductive post 120 120a is parallel to the cross-sectional area of the first surface 10a of the substrate 10.

Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2B is a schematic structural view of a conductive post according to another embodiment of the present invention. Referring to FIG. 2B , the conductive pillar 220 of the present embodiment is similar to the conductive pillar 120 of the above embodiment, and the difference is that the first end portion 220 a and the second end portion 220 b of the conductive pillar 220 may be a square cylinder. Therefore, in terms of the process, the shape of the opening of the mask layer for forming the conductive pillars 220 of the present embodiment needs to be correspondingly disposed.

In summary, the manufacturing method of the semiconductor package structure of the present invention firstly forms a protective layer in a recess on the metal substrate, and then forms a conductive pillar on the protective layer, wherein the second end of the conductive pillar is located in the recess. Next, forming a dielectric layer on the metal substrate, exposing the first end of the conductive pillar, subsequently forming a wiring layer electrically connected to the first end, electrically connecting the wafer to the wiring layer, and making the encapsulation layer The steps of coating the wafer and the like. Finally, the metal substrate is removed such that the second end of the conductive post protrudes out of the dielectric layer and the second end is covered by the protective layer. Further, the second end portion covered by the protective layer can serve as a contact point for electrical connection between the subsequent semiconductor package structure and the external component, that is, the semiconductor package structure of the present invention can be simplified without additional solder balls. Improve the production efficiency and yield by creating a process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor package structure

10‧‧‧Substrate

10a‧‧‧ first surface

10b‧‧‧second surface

11‧‧‧ dent

20‧‧‧ mask layer

21‧‧‧ openings

30‧‧‧Connecting mat

40‧‧‧ wafer adhesive film

50‧‧‧ wire

60‧‧‧Line carrier

110‧‧‧Protective layer

111‧‧‧ base

112‧‧‧ Sidewall

120, 220‧‧‧ conductive column

120a, 220a‧‧‧ first end

120b, 220b‧‧‧ second end

130‧‧‧Dielectric layer

131‧‧‧ upper surface

132‧‧‧ lower surface

140‧‧‧Line layer

150‧‧‧ solder mask

160‧‧‧ wafer

170‧‧‧Encapsulation layer

H‧‧‧ Height

T‧‧‧ thickness

1A to 1I are schematic cross-sectional views showing a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. 2A is a schematic structural view of the conductive post of FIG. 1I. 2B is a schematic structural view of a conductive post according to another embodiment of the present invention.

Claims (10)

A manufacturing method of a semiconductor package structure, comprising: providing a substrate; forming a plurality of recesses on the substrate; forming a protective layer in each of the recesses; forming a conductive pillar on each of the protective layers; Forming a dielectric layer on the substrate, wherein the dielectric layer and the conductive pillars are on the same side of the substrate, and the dielectric layer exposes the conductive pillars; forming a circuit layer on the dielectric layer Wherein the circuit layer and the substrate are located on opposite sides of the dielectric layer, and the circuit layer is electrically connected to the conductive pillars; at least one wafer is disposed on the dielectric layer, and the at least one wafer is electrically Connecting to the circuit layer; forming an encapsulation layer on the dielectric layer, and encapsulating the at least one wafer; and removing the substrate to expose the protective layers. The method of fabricating a semiconductor package structure according to claim 1, wherein the step of removing the substrate comprises: removing the substrate through an etching process. The method of manufacturing a semiconductor package structure according to claim 1, wherein the material of the substrate is different from the material of the protective layers. The method for fabricating a semiconductor package structure according to claim 1, further comprising: forming a solder resist layer on the dielectric layer, and the solder resist layer partially covers the circuit layer. The method of fabricating a semiconductor package structure according to claim 1, wherein the forming the recesses comprises: forming a mask layer on the substrate, the mask layer having a plurality of openings to expose a portion of the a substrate; and removing portions of the substrate exposed to the openings to form the depressions. The method of fabricating a semiconductor package structure according to claim 5, wherein the forming the conductive pillars comprises: forming the conductive pillars in the openings; and removing the mask layer. A semiconductor package structure comprising: a line carrier, comprising: a dielectric layer; a plurality of conductive pillars extending through the dielectric layer, wherein each of the conductive pillars has a first end and a second end And the second end protrudes from the dielectric layer; a circuit layer is disposed on the dielectric layer, and the circuit layer is connected to the first end; and a plurality of protective layers respectively covering the conductive pillars The second end portion, and the material of the protective layer is different from the material of the conductive pillars; at least one wafer is disposed on the dielectric layer, wherein the at least one wafer and the circuit layer are located on the dielectric layer The same side, and the at least one chip is electrically connected to the circuit layer; and an encapsulation layer disposed on the dielectric layer and covering the at least one wafer. The semiconductor package structure of claim 7, further comprising: a solder resist layer between the dielectric layer and the at least one wafer, and the solder resist layer partially covers the circuit layer. The semiconductor package structure of claim 7, wherein a cross-sectional area of the second end of each of the conductive pillars is smaller than a cross-sectional area of a portion of the conductive pillar that penetrates the dielectric layer. The semiconductor package structure of claim 7, further comprising: a plurality of connection pads between the package layer and the circuit layer, and the connection pads partially cover the circuit layer.