TW201834200A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW201834200A TW201834200A TW107108189A TW107108189A TW201834200A TW 201834200 A TW201834200 A TW 201834200A TW 107108189 A TW107108189 A TW 107108189A TW 107108189 A TW107108189 A TW 107108189A TW 201834200 A TW201834200 A TW 201834200A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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Abstract
本發明的半導體裝置100具有：包含多個多晶矽電阻器單元10的分壓電阻電路元件102、以個別地覆蓋多個多晶矽電阻器單元10的各個的方式分割為多個的第一金屬膜103、覆蓋分壓電阻電路元件102的整體的一體的第二金屬膜104、以及形成於第二金屬膜104上的氮化矽膜105，多個第一金屬膜103的各個於多晶矽電阻器單元10中包含覆蓋電極部11A的部分與覆蓋電極部11A以外的部分，覆蓋電極部11A以外的第一金屬膜103與各自覆蓋的多晶矽電阻器單元10進行電性連接。本發明提供一種可防止向分壓電阻電路整體的氫的浸入，且可抑制構成分壓電阻電路的各電阻器單元的電阻值調變的不均的半導體裝置。The semiconductor device 100 of the present invention includes a voltage dividing resistor circuit element 102 including a plurality of polysilicon resistor units 10, and a first metal film 103 divided into a plurality of layers so as to individually cover each of the plurality of polysilicon resistor units 10, An integral second metal film 104 covering the entire portion of the voltage dividing resistor circuit element 102, and a tantalum nitride film 105 formed on the second metal film 104, each of the plurality of first metal films 103 in the polysilicon resistor unit 10 The portion including the portion covering the electrode portion 11A and the portion other than the cover electrode portion 11A is electrically connected to the first metal film 103 other than the electrode portion 11A and the polysilicon resistor unit 10 covered. The present invention provides a semiconductor device capable of preventing the intrusion of hydrogen into the entire voltage dividing resistor circuit and suppressing the variation in the resistance value of each resistor unit constituting the voltage dividing resistor circuit.
Description
本發明是有關於一種半導體裝置。The present invention relates to a semiconductor device.
檢測電壓器等的類比（analog）積體電路（Integrated circuit，IC）以將電晶體與電阻器組合而輸出所需的特性的方式，具備例如包含多晶矽的薄膜電阻器的分壓（bleeder）電阻電路，並調整其電阻分壓比。於該薄膜電阻器上形成有層間絕緣膜及最終保護膜，但已知有如下問題：於其形成過程中因擴散的氫的浸入，導致分壓電阻電路的電阻分壓比於晶圓面內不均，良率下降。一般的半導體裝置於薄膜電阻器上無接縫地配置大面積的金屬配線，避免該氫浸入的問題。An analog integrated circuit (IC) for detecting a voltage device or the like has a partial resistor of a thin film resistor including a polysilicon, for example, in combination with a resistor and a resistor to output a desired characteristic. Circuit and adjust its resistor divider ratio. An interlayer insulating film and a final protective film are formed on the thin film resistor, but a problem is known in that the resistance of the voltage dividing resistor is proportional to the in-wafer in the wafer due to the immersion of diffused hydrogen during the formation thereof. Uneven, yield decline. A general semiconductor device is provided with a large-area metal wiring seamlessly on a thin film resistor to avoid the problem of hydrogen immersion.
其中，即便於以所述方式配置金屬配線的情況下，根據配線上的情況，將各電阻器的電極部彼此電性連接的金屬配線、即覆蓋電極部的金屬配線亦與覆蓋電極部以外的高電阻部的大面積的金屬配線分離。因此，於經分離的金屬配線間存在間隙，難以避免自所述間隙向電極部周邊的氫的浸入。向電極部周邊的氫的浸入的影響於搭載複雜的電路的多層配線結構的半導體裝置中變得顯著。In the case where the metal wiring is disposed as described above, the metal wiring electrically connecting the electrode portions of the respective resistors, that is, the metal wiring covering the electrode portion, and the cover electrode portion are not included in the wiring. The large-area metal wiring of the high-resistance portion is separated. Therefore, there is a gap between the separated metal wirings, and it is difficult to avoid the intrusion of hydrogen from the gap to the periphery of the electrode portion. The influence of the intrusion of hydrogen around the electrode portion on the semiconductor device having a multilayer wiring structure in which a complicated circuit is mounted becomes remarkable.
另一方面，於如所述般配置大面積的金屬配線的情況下，亦產生於構成分壓電阻電路的各電阻器單元，電阻值因不同的比例而調變的問題。其起因於：由電源電壓（Vdd 、Vss ）形成的各電阻器單元的電位根據離電源的距離而不同，與接地的金屬配線的電位差於各電阻器單元而不同。例如，處於低電位側（Vss ）的電阻器單元與金屬配線的電位差小，因此電阻值調變小，相對於此，處於高電位側（Vdd ）的電阻器單元與金屬配線的電位差大，因此電阻值調變大。各電阻器單元的電阻值調變的不均於使電源電壓變高的情況下變得顯著，要求一種所述情況下的對策。On the other hand, when a large-area metal wiring is disposed as described above, it also occurs in each resistor unit constituting the voltage dividing resistor circuit, and the resistance value is changed by a different ratio. This is because the potential of each resistor unit formed by the power supply voltages (V dd , V ss ) differs depending on the distance from the power source, and the potential difference from the grounded metal wiring differs from the respective resistor units. For example, the potential difference between the resistor unit and the metal wiring on the low potential side (V ss ) is small, so that the resistance value is small, and the potential difference between the resistor unit and the metal wiring on the high potential side (V dd ) is large. Therefore, the resistance value is adjusted to be large. The variation in the resistance value of each resistor unit becomes remarkable when the power supply voltage is increased, and a countermeasure in the above case is required.
作為電阻值調變的不均的對策之一，於專利文獻1中揭示有一種將金屬配線以與各電阻器單元相對應的方式分割，並將分割的金屬配線的各個與相對應的電阻器單元電性連接的構成。根據該構成，於電阻器單元與金屬配線之間未產生電位差，因此可避免電阻值調變的不均的問題。One of the countermeasures for unevenness in the change of the resistance value is disclosed in Patent Document 1 in which metal wiring is divided so as to correspond to each resistor unit, and each of the divided metal wirings and the corresponding resistor are provided. The composition of the unit electrical connection. According to this configuration, no potential difference is generated between the resistor unit and the metal wiring, so that the problem of unevenness in the adjustment of the resistance value can be avoided.
其中，該構成中，於經分割的金屬配線彼此之間產生間隙，因此有可能通過間隙的氫擾亂分壓電阻電路的電阻分壓比，存在進一步改善的餘地。 [現有技術文獻] [專利文獻]In this configuration, since a gap is formed between the divided metal wires, there is a possibility that the resistance division ratio of the voltage dividing resistor circuit is disturbed by the hydrogen in the gap, and there is room for further improvement. [Prior Art Document] [Patent Literature]
[專利文獻1]日本專利第3526701號[Patent Document 1] Japanese Patent No. 3562701
[發明所欲解決之課題] 本發明是鑒於所述情況而成者，其目的在於提供一種可防止向包含電極部的分壓電阻電路整體的氫的浸入，且可抑制構成分壓電阻電路的各電阻器單元的電阻值調變的不均的半導體裝置。 [解決課題之手段][Problems to be Solved by the Invention] The present invention has been made in view of the above circumstances, and it is an object of the invention to provide a method of preventing intrusion of hydrogen into the entire voltage dividing resistor circuit including an electrode portion, and suppressing formation of a voltage dividing resistor circuit. A semiconductor device in which the resistance values of the respective resistor units are modulated unevenly. [Means for solving the problem]
為了解決所述課題，本發明採用以下的手段。In order to solve the above problems, the present invention employs the following means.
（1）本發明的一實施方式的半導體裝置具有：基板；分壓電阻電路元件，形成於所述基板的其中一主面側，且包含多個多晶矽電阻器單元；第一金屬膜，以個別地覆蓋所述多個多晶矽電阻器單元的各個的方式分割為多個；一體的第二金屬膜，於所述第一金屬膜上覆蓋所述分壓電阻電路元件的整體；以及氮化矽膜，形成於所述第二金屬膜上；多個所述第一金屬膜的各個於所述多晶矽電阻器單元中包含覆蓋電極部的部分與覆蓋電極部以外的部分，覆蓋所述電極部以外的所述部分與各自覆蓋的所述多晶矽電阻器單元進行電性連接。 （2）如所述（1）所述的半導體裝置，較佳為自所述氮化矽膜側的俯視時，所述第2金屬膜的最外周較所述分壓電阻電路元件的最外周處於更外側。 （3）如所述（1）或（2）所述的半導體裝置，較佳為進而具有側壁部，所述側壁部立設於所述分壓電阻電路元件的周圍，並與所述第二金屬膜連接。 （4）如所述（1）至（3）中任一項所述的半導體裝置，較佳為具有將所述基板與所述第一金屬膜連結的第一連接孔、以及將所述第一金屬膜與所述第二金屬膜連結的第二連接孔，所述側壁部包括埋入至所述第一連接孔中的金屬膜、以及埋入至所述第二連接孔中的金屬膜。 （5）如所述（3）或（4）所述的半導體裝置，較佳為俯視時於形成有所述分壓電阻電路元件的區域與形成有所述側壁部的區域之間的區域具有多晶矽罩的構成。 [發明的效果](1) A semiconductor device according to an embodiment of the present invention includes: a substrate; a voltage dividing resistor circuit element formed on one of main faces of the substrate, and including a plurality of polysilicon resistor units; and a first metal film to be individually Dividing into a plurality of ways of covering each of the plurality of polysilicon resistor units; an integral second metal film covering the entirety of the voltage dividing resistor circuit component on the first metal film; and a tantalum nitride film Formed on the second metal film; each of the plurality of first metal films includes a portion covering the electrode portion and a portion other than the cover electrode portion in the polysilicon resistor unit, covering the electrode portion The portions are electrically connected to the respective polysilicon resistor units covered. (2) The semiconductor device according to (1), wherein the outermost circumference of the second metal film is smaller than the outermost circumference of the voltage dividing resistor circuit element in a plan view from the tantalum nitride film side. On the outside. (3) The semiconductor device according to (1) or (2), further comprising a side wall portion that is erected around the voltage dividing resistor circuit element and the second portion Metal film connection. (4) The semiconductor device according to any one of (1) to (3), further comprising: a first connection hole that connects the substrate to the first metal film, and the first a second connection hole connecting the metal film and the second metal film, the side wall portion including a metal film buried in the first connection hole, and a metal film buried in the second connection hole . (5) The semiconductor device according to the above (3) or (4), preferably having a region between a region where the voltage dividing resistor circuit element is formed and a region where the sidewall portion is formed in plan view The composition of the polycrystalline enamel cover. [Effects of the Invention]
所述半導體裝置中具有個別連接於多個多晶矽電阻器單元的各個的多個第一金屬膜，進而具有夾持第一金屬膜並覆蓋分壓電阻電路元件的整體的大面積的第二金屬膜。藉由具有第一金屬膜，多晶矽電阻器單元與第一金屬膜的電位差不論佈局如何均成為一定，因此可避免電阻值調變於各多晶矽電阻器單元不均的問題。The semiconductor device has a plurality of first metal films individually connected to each of the plurality of polysilicon resistor units, and further has a large area of the second metal film sandwiching the first metal film and covering the entire portion of the voltage dividing resistor circuit element . By having the first metal film, the potential difference between the polysilicon resistor unit and the first metal film is constant regardless of the layout, so that the problem that the resistance value is modulated by the unevenness of each polysilicon resistor unit can be avoided.
另外，藉由具有第二金屬膜，可避免於製造過程中氫浸入至分壓電阻電路元件中的問題。因此，所述半導體裝置中分壓電阻電路元件中所含有的氫的量較先前而明顯減少。In addition, by having the second metal film, the problem of hydrogen immersion into the voltage dividing resistor circuit element during the manufacturing process can be avoided. Therefore, the amount of hydrogen contained in the voltage dividing resistor circuit element in the semiconductor device is significantly reduced as compared with the prior art.
將第二金屬膜設於第一金屬膜的上層側，無需如第一金屬膜般按照相對應的多晶矽電阻器單元的電極部、高電阻部進行分割，可形成無間隙地覆蓋包含電極部周邊在內的分壓電阻電路整體的形狀。因此，所述半導體裝置中，不僅可遮蔽向多晶矽電阻器的中央部的氫浸入路徑，而且亦可遮蔽向設有電極部的多晶矽電阻器的端部的氫浸入路徑，從而可防止伴隨分壓電阻電路元件的電阻分壓比的紊亂的良率下降。The second metal film is provided on the upper layer side of the first metal film, and it is not necessary to divide the electrode portion and the high resistance portion of the corresponding polysilicon resistor unit as in the first metal film, and the periphery of the electrode portion can be formed without a gap. The overall shape of the voltage dividing resistor circuit. Therefore, in the semiconductor device, not only the hydrogen immersion path to the central portion of the polysilicon resistor but also the hydrogen immersion path to the end portion of the polysilicon resistor provided with the electrode portion can be shielded, thereby preventing the accompanying partial pressure. The turbulent yield of the resistance division ratio of the resistance circuit element is lowered.
以下，適當參照圖來對本發明進行詳細說明。對於以下的說明中所用的圖式，為了容易理解本發明的特徵，有時會為了方便而將成為特徵的部分放大表示，各構成要素的尺寸比率等有時與實際不同。另外，以下的說明中例示的材料、尺寸等為一例，本發明並不限定於該些，可在發揮本發明的效果的範圍內進行適當變更而實施。Hereinafter, the present invention will be described in detail with reference to the drawings. In the drawings used in the following description, in order to facilitate understanding of the features of the present invention, the features may be enlarged for convenience, and the dimensional ratios of the respective constituent elements may be different from actual ones. In addition, the material, the size, and the like exemplified in the following description are examples, and the present invention is not limited thereto, and can be appropriately modified and implemented within the scope of exerting the effects of the present invention.
＜第一實施形態＞ [半導體裝置的構成] 圖1是本發明的第一實施形態的半導體裝置100的平面圖。圖2（a）及圖2（b）分別是於圖1中沿A-A'線、B-B'線切斷半導體裝置100時的剖面圖。<First Embodiment> [Configuration of Semiconductor Device] Fig. 1 is a plan view showing a semiconductor device 100 according to a first embodiment of the present invention. 2(a) and 2(b) are cross-sectional views showing the semiconductor device 100 taken along line A-A' and line BB' in Fig. 1, respectively.
半導體裝置100具有基板（基材）101、形成於基板的其中一主面側的分壓電阻電路元件102、形成於分壓電阻電路元件102上的兩個金屬膜（第一金屬膜103、第二金屬膜104）、以及設於第二金屬膜104上的氮化矽膜105作為主要的構成要素。The semiconductor device 100 includes a substrate (substrate) 101, a voltage dividing resistor circuit element 102 formed on one of the main surface sides of the substrate, and two metal films (first metal film 103, first) formed on the voltage dividing resistor circuit element 102. The two metal film 104) and the tantalum nitride film 105 provided on the second metal film 104 are main constituent elements.
於基板101與分壓電阻電路元件102之間、分壓電阻電路元件102與第一金屬膜103之間、第一金屬膜103與第二金屬膜104之間分別形成有絕緣膜106、絕緣膜107、絕緣膜108。亦可於第二金屬膜104與氮化矽膜105之間形成有絕緣膜109。再者，圖1中為了使作為主要部分的分壓電阻電路元件102及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。An insulating film 106 and an insulating film are formed between the substrate 101 and the voltage dividing resistor circuit element 102, between the voltage dividing resistor circuit element 102 and the first metal film 103, and between the first metal film 103 and the second metal film 104, respectively. 107. An insulating film 108. An insulating film 109 may be formed between the second metal film 104 and the tantalum nitride film 105. In addition, in FIG. 1, in order to clarify the structure of the voltage-dividing resistor circuit element 102 as a main part and its surroundings, the illustration of a board|substrate, an insulating film, a tantalum nitride film, etc. is ab
圖2（a）及圖2（b）所示的半導體裝置100中是使用於一主面側設有p型阱101A的n型基板101，具有兩層配線結構。分壓電阻電路元件102是設於形成於p型阱101A的表面的絕緣膜（場絕緣膜）106上。In the semiconductor device 100 shown in FIGS. 2(a) and 2(b), the n-type substrate 101 provided with the p-type well 101A on one main surface side has a two-layer wiring structure. The voltage dividing resistor circuit element 102 is provided on an insulating film (field insulating film) 106 formed on the surface of the p type well 101A.
再者，半導體裝置100的構成並不限於圖2（a）及圖2（b）所示者，亦可根據用途而設有分壓電阻電路元件102以外的元件，亦可具有兩層以上的配線結構。另外，亦可自由地設定基板上所摻雜的雜質的導電型。In addition, the configuration of the semiconductor device 100 is not limited to those shown in FIGS. 2( a ) and 2 ( b ), and elements other than the voltage dividing resistor circuit element 102 may be provided depending on the application, and may have two or more layers. Wiring structure. Further, the conductivity type of the impurity doped on the substrate can be freely set.
分壓電阻電路元件102包含多個多晶矽電阻器單元10。多晶矽電阻器單元10包含摻雜有p型或n型的雜質、且顯示所需的電阻值的單體的多晶矽電阻器11、以顯示所需的電阻值的方式連接的多個多晶矽電阻器11中的一者或兩者。The voltage dividing resistor circuit component 102 includes a plurality of polysilicon resistor units 10. The polysilicon resistor unit 10 includes a polysilicon resistor 11 doped with a p-type or n-type impurity and exhibiting a desired resistance value, and a plurality of polysilicon resistors 11 connected in such a manner as to display a desired resistance value. One or both of them.
即，分壓電阻電路元件102可僅由包含單體的多晶矽電阻器11的多晶矽電阻器單元10A構成，亦可僅由包含多個多晶矽電阻器11的多晶矽電阻器單元10B構成，抑或可將多晶矽電阻器單元10A、多晶矽電阻器單元10B兩者組合而構成。圖1中例示將多晶矽電阻器單元10A、多晶矽電阻器單元10B兩者組合而構成的情況。That is, the voltage dividing resistor circuit element 102 may be composed only of the polysilicon resistor unit 10A including the polysilicon resistor 11 of a single body, or may be composed only of the polysilicon resistor unit 10B including a plurality of polysilicon resistors 11, or may be polycrystalline germanium. The resistor unit 10A and the polysilicon resistor unit 10B are combined and configured. FIG. 1 exemplifies a case where both the polysilicon resistor unit 10A and the polysilicon resistor unit 10B are combined.
作為第一金屬膜103，例如可使用Al-Si-Cu膜、Al-Cu膜等，其厚度較佳為大致3000 Å以上且5000 Å以下的範圍。As the first metal film 103, for example, an Al-Si-Cu film, an Al-Cu film, or the like can be used, and the thickness thereof is preferably in the range of approximately 3,000 Å or more and 5,000 Å or less.
第一金屬膜103是以個別地覆蓋多個多晶矽電阻器單元10的各個的方式分割為多個。即，於任一多晶矽電阻器單元10上亦設有各至少一片第一金屬膜103。於鄰接的多晶矽電阻器單元10上所設置的第一金屬膜103彼此相互隔開。The first metal film 103 is divided into a plurality of pieces so as to cover each of the plurality of polysilicon resistor units 10 individually. That is, at least one piece of the first metal film 103 is also provided on any of the polysilicon resistor units 10. The first metal films 103 provided on the adjacent polysilicon resistor unit 10 are spaced apart from each other.
多個第一金屬膜103的各個於多晶矽電阻器單元10中藉由覆蓋電極部11A的部分（電極引出層）103A、以及覆蓋電極部11A以外的高電阻部11B的部分（被覆層）103B而進一步分割。電極部11A位於各多晶矽電阻器11的端部，以較高電阻部11B更高的濃度摻雜有雜質。Each of the plurality of first metal films 103 is covered by a portion (electrode extraction layer) 103A covering the electrode portion 11A and a portion (cover layer) 103B covering the high resistance portion 11B other than the electrode portion 11A in the polysilicon resistor unit 10. Further segmentation. The electrode portion 11A is located at the end of each of the polysilicon resistors 11, and is doped with impurities at a higher concentration of the higher resistance portion 11B.
圖3是使半導體裝置100運作的分壓電阻電路102A及其周邊電路的圖。分壓電阻電路102A中串聯連接有多個多晶矽電阻器單元10，相對於特定的多晶矽電阻器單元10而並列連接有保險絲電路元件12。FIG. 3 is a diagram of a voltage dividing resistor circuit 102A that operates the semiconductor device 100 and its peripheral circuits. A plurality of polysilicon resistor units 10 are connected in series to the voltage dividing resistor circuit 102A, and the fuse circuit elements 12 are connected in parallel with respect to the specific polysilicon resistor unit 10.
被覆層103B與其各自覆蓋的多晶矽電阻器單元10經由金屬配線而連接。即，相對於一個多晶矽電阻器單元10而電性連接有覆蓋其的一個被覆層103B。因此，對串聯連接有多個多晶矽電阻器單元10的分壓電阻電路102A的一端側、另一端側分別施加不同的電源電壓Vdd 、Vss （Vdd ＞Vss ）並於兩者產生電位差的情況下，被覆層103B與多晶矽電阻器單元10亦成為等電位。The cladding layer 103B is connected to the polysilicon resistor unit 10 covered by the respective layers 103B via metal wiring. That is, one cladding layer 103B covering the polysilicon resistor unit 10 is electrically connected thereto. Therefore, different power supply voltages V dd , V ss (V dd > V ss ) are applied to one end side and the other end side of the voltage dividing resistor circuit 102A in which a plurality of polysilicon resistor units 10 are connected in series, and a potential difference is generated therebetween. In the case of the coating layer 103B and the polysilicon resistor unit 10, the potential is also equal.
將多晶矽電阻器單元10與被覆層103B連接的金屬配線的材料亦可為與第一金屬膜103相同者，亦可為高熔點金屬的鎢等。The material of the metal wiring connecting the polysilicon resistor unit 10 and the coating layer 103B may be the same as the first metal film 103, or may be tungsten of a high melting point metal or the like.
作為第二金屬膜104，例如可使用Al-Si-Cu膜、Al-Cu膜等，其厚度較佳為大致3000 Å以上且10000 Å以下的範圍。As the second metal film 104, for example, an Al-Si-Cu film, an Al-Cu film, or the like can be used, and the thickness thereof is preferably in the range of approximately 3,000 Å or more and 10,000 Å or less.
第二金屬膜104為夾持第一金屬膜103且無接縫地覆蓋包含電極部11A的分壓電阻電路元件102的整體的一體的大面積膜。第二金屬膜104的電位以Vss 接地。The second metal film 104 is an integrated large-area film that sandwiches the first metal film 103 and seamlessly covers the entire portion of the voltage dividing resistor circuit element 102 including the electrode portion 11A. The potential of the second metal film 104 is grounded at V ss .
本實施形態的半導體裝置100中具有個別連接於多個多晶矽電阻器單元10的各個的多個第一金屬膜103，進而具有夾持第一金屬膜103並覆蓋分壓電阻電路元件102的整體的大面積的第二金屬膜104。藉由具有第一金屬膜103，多晶矽電阻器單元10與第一金屬膜103的電位差不論佈局如何均成為一定，因此可避免電阻值調變於各多晶矽電阻器單元10不均的問題。The semiconductor device 100 of the present embodiment includes a plurality of first metal films 103 that are individually connected to each of the plurality of polysilicon resistor units 10, and further includes a first metal film 103 sandwiched therebetween and covering the entire voltage dividing resistor circuit element 102. A large area of the second metal film 104. By having the first metal film 103, the potential difference between the polysilicon resistor unit 10 and the first metal film 103 is constant irrespective of the layout, so that the problem that the resistance value is modulated by the unevenness of each polysilicon resistor unit 10 can be avoided.
另外，藉由具有第二金屬膜104，可避免於製造過程中氫浸入至分壓電阻電路元件102中的問題。因此，本實施形態的半導體裝置100中分壓電阻電路元件102中所含有的氫的量較先前而明顯減少。In addition, by having the second metal film 104, the problem of hydrogen immersion into the voltage dividing resistor circuit element 102 during the manufacturing process can be avoided. Therefore, in the semiconductor device 100 of the present embodiment, the amount of hydrogen contained in the voltage dividing resistor circuit element 102 is significantly reduced as compared with the prior art.
將第二金屬膜104設於第一金屬膜103的上層側，無需如第一金屬膜103般按照相對應的多晶矽電阻器單元10的電極部11A、高電阻部11B進行分割，可形成無間隙地覆蓋包含電極部11A周邊在內的分壓電阻電路元件102A整體的形狀。因此，本實施形態的半導體裝置100中，不僅可遮蔽向多晶矽電阻器11的高電阻部11B的氫浸入路徑，而且亦可遮蔽向多晶矽電阻器11的設有電極部11A的端部的氫浸入路徑，從而可防止伴隨分壓電阻電路元件102的電阻分壓比的紊亂的良率下降。The second metal film 104 is provided on the upper layer side of the first metal film 103, and it is not necessary to divide the electrode portion 11A and the high resistance portion 11B of the corresponding polysilicon resistor unit 10 as in the first metal film 103, and a gap can be formed. The shape of the entire voltage dividing resistor circuit element 102A including the periphery of the electrode portion 11A is covered. Therefore, in the semiconductor device 100 of the present embodiment, not only the hydrogen immersion path to the high resistance portion 11B of the polysilicon resistor 11 but also the hydrogen immersion of the end portion of the polysilicon resistor 11 where the electrode portion 11A is provided can be shielded. The path can prevent a decrease in the yield of the disturbance accompanying the voltage division ratio of the voltage dividing resistor circuit element 102.
較佳為自氮化矽膜105側的俯視時，第二金屬膜104的最外周較分壓電阻電路元件102的最外周處於更外側。該情況下，可於第二金屬膜104中阻止相對於分壓電阻電路元件102而欲自上層側垂直地浸入的氫、以及欲傾斜地浸入的氫的一部分，相對應地，可提高相對於氫的分壓電阻電路元件102的保護功能。It is preferable that the outermost circumference of the second metal film 104 is located further outward than the outermost circumference of the voltage dividing resistor circuit element 102 in a plan view from the side of the tantalum nitride film 105. In this case, in the second metal film 104, hydrogen which is to be vertically immersed from the upper layer side with respect to the voltage dividing resistor circuit element 102 and a part of hydrogen to be obliquely immersed can be prevented, and accordingly, relative to hydrogen can be improved. The protection function of the voltage dividing resistor circuit component 102.
先前的結構中，需要利用第一金屬膜確實地覆蓋高電阻部，因此第一金屬膜以不僅覆蓋高電阻部而且亦覆蓋低電阻部的一部分的方式大範圍地形成。即，先前結構中，於第一金屬膜存在與低電阻部的重疊（overlap）區域。In the prior art, it is necessary to surely cover the high-resistance portion by the first metal film, and therefore the first metal film is formed in a wide range so as not to cover not only the high-resistance portion but also a part of the low-resistance portion. That is, in the prior structure, there is an overlap region with the low resistance portion in the first metal film.
相對於此，本實施形態的半導體裝置100中，第二金屬膜104起到覆蓋高電阻部的作用，因此無需大範圍地形成第一金屬膜103，可削減第一金屬膜103與低電阻部的重疊區域，並可縮小半導體裝置整體的尺寸。On the other hand, in the semiconductor device 100 of the present embodiment, since the second metal film 104 functions to cover the high resistance portion, the first metal film 103 is not required to be formed in a wide range, and the first metal film 103 and the low resistance portion can be reduced. The overlapping area and the overall size of the semiconductor device can be reduced.
另外，於先前結構中，為了於分割的第一金屬膜彼此的間隙處，利用第一金屬膜確實地覆蓋高電阻部，配置有虛設的電阻器，但本實施形態中無需如此，進而可縮小半導體裝置整體的尺寸。Further, in the prior art, in order to cover the high-resistance portion with the first metal film in the gap between the divided first metal films, a dummy resistor is disposed, but this need not be the case in the embodiment, and thus can be reduced. The overall size of the semiconductor device.
[半導體裝置的製造方法] 以形成分壓電阻電路元件102及其周邊部分的步驟為中心來對半導體裝置100的製造方法進行說明。[Manufacturing Method of Semiconductor Device] A method of manufacturing the semiconductor device 100 will be described focusing on a step of forming the voltage dividing resistor circuit element 102 and its peripheral portion.
首先，於n型基板的其中一主面側摻雜p型雜質而形成p型阱。繼而，利用矽局部氧化（Local Oxidation of Silicon，LOCOS）法或淺溝槽隔離（Shallow Trench Isolation，STI）法來形成場絕緣膜。繼而，於p型阱內的規定位置形成p型雜質濃度相對高的區域（p+ 擴散層）。First, a p-type impurity is formed by doping a p-type impurity on one of the main surface sides of the n-type substrate. Then, a field insulating film is formed by a Local Oxidation of Silicon (LOCOS) method or a Shallow Trench Isolation (STI) method. Then, a region (p + diffusion layer) having a relatively high p-type impurity concentration is formed at a predetermined position in the p-type well.
其次，利用化學氣相沈積（Chemical Vapor Deposition，CVD）法等公知的方法，於場絕緣膜上進行構成分壓電阻電路的多晶矽（多矽）的膜形成，進而以成為所需的形狀、配置的方式進行圖案化，從而形成多個多晶矽電阻器。所形成的電阻器的厚度較佳為設為大致500 Å以上且5000 Å以下。Next, a polycrystalline silicon (multi-turn) film constituting a voltage dividing resistor circuit is formed on a field insulating film by a known method such as chemical vapor deposition (CVD), and further, a desired shape and arrangement are performed. The pattern is patterned to form a plurality of polysilicon resistors. The thickness of the formed resistor is preferably set to be approximately 500 Å or more and 5,000 Å or less.
其次，利用CVD法等公知的方法，於多晶矽電阻器上形成層間絕緣膜。繼而，於與包含單個或多個多晶矽電阻器的多晶矽電阻器單元的至少一部分重合的位置，在層間絕緣膜內形成接觸孔。繼而，將金屬膜埋入至接觸孔內。埋入的金屬膜的材料亦可為與第一金屬膜的材料相同者，亦可為高熔點金屬的鎢。Next, an interlayer insulating film is formed on the polysilicon resistor by a known method such as a CVD method. Then, a contact hole is formed in the interlayer insulating film at a position overlapping with at least a portion of the polysilicon resistor unit including the single or plurality of polysilicon resistors. Then, the metal film is buried in the contact hole. The material of the buried metal film may be the same as the material of the first metal film, or may be tungsten of a high melting point metal.
其次，利用濺鍍法等公知的方法，於形成有接觸孔的層間絕緣膜上形成第一金屬膜。而且，對於所形成的第一金屬膜而言，以1比1對應於各多晶矽電阻器單元的方式進行圖案化並加以分割。藉由該分割，針對各多晶矽電阻器單元而形成有相對應的第一金屬膜的被覆層。即，成為一個第一金屬膜被覆一個多晶矽電阻器單元的狀態。Next, a first metal film is formed on the interlayer insulating film on which the contact holes are formed by a known method such as sputtering. Further, the formed first metal film is patterned and divided so that 1 to 1 corresponds to each polysilicon resistor unit. By this division, a coating layer of the corresponding first metal film is formed for each polysilicon resistor unit. That is, a state in which one first metal film is coated with one polysilicon resistor unit is obtained.
作為第一金屬膜，例如可使用Al-Si-Cu膜、Al-Cu膜。第一金屬膜的厚度較佳為於大致3000 Å以上且5000 Å以下的範圍內設定。As the first metal film, for example, an Al—Si—Cu film or an Al—Cu film can be used. The thickness of the first metal film is preferably set in a range of approximately 3,000 Å or more and 5,000 Å or less.
其次，利用CVD法等公知的方法，於第一金屬膜上形成層間絕緣膜，並利用濺鍍法等公知的方法，於該層間絕緣膜上形成第二金屬膜。此時，成為至少覆蓋分壓電阻電路元件的整體的、一體的具有大面積的膜。Then, an interlayer insulating film is formed on the first metal film by a known method such as a CVD method, and a second metal film is formed on the interlayer insulating film by a known method such as sputtering. At this time, an integrated film having a large area covering at least the entire portion of the voltage dividing resistor circuit element is formed.
作為第二金屬膜，例如可使用Al-Si-Cu膜、Al-Cu膜。第二金屬膜的厚度較佳為於大致3000 Å以上且10000 Å以下的範圍內設定。As the second metal film, for example, an Al—Si—Cu film or an Al—Cu film can be used. The thickness of the second metal film is preferably set in a range of approximately 3,000 Å or more and 10,000 Å or less.
最後，利用電漿CVD法，直接或經由氧化膜而於第二金屬膜上形成氮化矽膜，藉此可獲得本實施形態的半導體裝置100。Finally, the semiconductor device 100 of the present embodiment can be obtained by forming a tantalum nitride film on the second metal film directly or via an oxide film by a plasma CVD method.
＜第二實施形態＞ [半導體裝置的構成] 圖4是本發明的第二實施形態的半導體裝置200的平面圖。圖5是於圖4中沿C-C'線切斷半導體裝置200時的剖面圖。再者，圖4中為了使作為主要部分的分壓電阻電路元件及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。<Second Embodiment> [Configuration of Semiconductor Device] Fig. 4 is a plan view showing a semiconductor device 200 according to a second embodiment of the present invention. FIG. 5 is a cross-sectional view of the semiconductor device 200 taken along line CC' in FIG. In addition, in FIG. 4, in order to clarify the structure of the voltage-dividing resistor circuit element as a main part and its surroundings, the illustration of a board|substrate, an insulating film, a tantalum nitride film, etc. is ab
半導體裝置200具有立設於分壓電阻電路元件202的周圍（最外周），頂部與第二金屬膜204連接且底部與基板201連接的側壁部211。於基板201的表面中連接有側壁部211的部分設有p型高濃度擴散層（p+ 擴散層）210。半導體裝置200的側壁部211以外的構成與第一實施形態的半導體裝置100的構成相同，可獲得與半導體裝置100同等的效果。The semiconductor device 200 has a side wall portion 211 which is disposed around the periphery (outermost circumference) of the voltage dividing resistor circuit element 202, and has a top portion connected to the second metal film 204 and a bottom portion connected to the substrate 201. A p-type high concentration diffusion layer (p + diffusion layer) 210 is provided in a portion of the surface of the substrate 201 to which the side wall portion 211 is connected. The configuration other than the side wall portion 211 of the semiconductor device 200 is the same as that of the semiconductor device 100 of the first embodiment, and an effect equivalent to that of the semiconductor device 100 can be obtained.
側壁部211藉由第一金屬膜203C、分別埋入至第一金屬膜203C的下層側及上層側的絕緣膜207、絕緣膜208中所設置的接觸孔（第一連接孔207A、第二連接孔208A）中的金屬膜207B、金屬膜208B、以及第一連接孔207A之下的p型阱201A內所設置的p型高濃度擴散層（p+ 擴散層）210而構成為堆疊狀。第一連接孔207A將基板201與第一金屬膜203C連結，第二連接孔208A將第一金屬膜203C與第二金屬膜204連結。p型高濃度擴散層210於自半導體裝置200的最表面側的俯視時，包圍分壓電阻電路元件202的周圍。The side wall portion 211 is buried in the insulating film 207 on the lower layer side and the upper layer side of the first metal film 203C and the contact hole provided in the insulating film 208 by the first metal film 203C (first connection hole 207A, second connection) The metal film 207B in the hole 208A), the metal film 208B, and the p-type high concentration diffusion layer (p + diffusion layer) 210 provided in the p-type well 201A under the first connection hole 207A are formed in a stacked shape. The first connection hole 207A connects the substrate 201 to the first metal film 203C, and the second connection hole 208A connects the first metal film 203C and the second metal film 204. The p-type high concentration diffusion layer 210 surrounds the periphery of the voltage dividing resistor circuit element 202 in a plan view from the outermost surface side of the semiconductor device 200.
較佳為自氮化矽膜205側的俯視時，側壁部211以短間隔並排，若無接縫地包圍分壓電阻電路元件202，則更佳。It is preferable that the side wall portions 211 are arranged side by side at a short interval in a plan view from the side of the tantalum nitride film 205, and it is more preferable to surround the voltage dividing resistor circuit element 202 without seams.
藉由半導體裝置200中存在側壁部211，不僅可阻止自上方呈直線浸入至分壓電阻電路元件202中的氫，而且亦可阻止自側方迂回而浸入的氫，從而可更有力地保護分壓電阻電路元件202。By the presence of the side wall portion 211 in the semiconductor device 200, not only the hydrogen which is linearly immersed into the voltage dividing resistor circuit element 202 from above but also the hydrogen immersed from the side can be prevented, so that the branch can be more effectively protected. Piezoresistive circuit component 202.
另外，側壁部211遮蔽自側方的氫浸入，因此第二金屬膜204只要僅遮蔽自上方呈直線向分壓電阻電路元件202浸入的氫即可。因此，第二金屬膜204的面積可設為與分壓電阻電路元件202相同程度的面積，與無側壁部211的情況相比，可縮小半導體裝置整體的尺寸。Further, since the side wall portion 211 shields the hydrogen intrusion from the side, the second metal film 204 only needs to shield the hydrogen which is linearly infiltrated into the voltage dividing resistor circuit element 202 from above. Therefore, the area of the second metal film 204 can be set to be the same as that of the voltage dividing resistor circuit element 202, and the size of the entire semiconductor device can be reduced as compared with the case where the side wall portion 211 is not provided.
＜第三實施形態＞ [半導體裝置的構成] 圖6是本發明的第三實施形態的半導體裝置300的平面圖。圖7（a）及圖7（b）分別是於圖6中沿D-D'線、E-E'線切斷半導體裝置300時的剖面圖。再者，圖6中為了使作為主要部分的分壓電阻電路元件及其周邊的構成明瞭化，省略基板、絕緣膜、氮化矽膜等的圖示。<Third Embodiment> [Configuration of Semiconductor Device] Fig. 6 is a plan view showing a semiconductor device 300 according to a third embodiment of the present invention. 7(a) and 7(b) are cross-sectional views showing the semiconductor device 300 taken along line DD' and line E-E' in Fig. 6, respectively. In addition, in FIG. 6, in order to clarify the structure of the voltage-dividing resistor circuit element which is a main part and its surroundings, illustration of a board|substrate, an insulating film, a
與第二實施形態同樣地，半導體裝置300具有立設於分壓電阻電路元件302的周圍（最外周），頂部與第二金屬膜304連接且底部與基板301連接的側壁部311。另外，關於半導體裝置300的形成有側壁部311的區域的內側的分壓電阻電路元件302的構成，與第一實施形態的半導體裝置100的構成相同。Similarly to the second embodiment, the semiconductor device 300 has a side wall portion 311 which is provided on the periphery (outermost circumference) of the voltage dividing resistor circuit element 302, and has a top portion connected to the second metal film 304 and a bottom portion connected to the substrate 301. In addition, the configuration of the voltage dividing resistor circuit element 302 on the inner side of the region in which the side wall portion 311 of the semiconductor device 300 is formed is the same as that of the semiconductor device 100 of the first embodiment.
如圖7（a）所示，亦與第二實施形態相同的是：側壁部311藉由第一金屬膜303C、分別埋入至第一金屬膜303C的下層側及上層側的絕緣膜307、絕緣膜308中所設置的接觸孔（第一連接孔307A、第二連接孔308A）中的金屬膜307B、金屬膜308B、以及第一連接孔307A之下的p型阱301A內所設置的p型高濃度擴散層（p+ 擴散層）310而構成為堆疊狀。而且，第一連接孔307A將基板301與第一金屬膜303C連結，第二連接孔308A將第一金屬膜303C與第二金屬膜304連結。p型高濃度擴散層310於自半導體裝置300的最表面側的俯視時，包圍分壓電阻電路元件302的周圍。即，可藉由該些構成來獲得與第一實施形態及第二實施形態同等的效果。As shown in Fig. 7 (a), the side wall portion 311 is embedded in the lower surface side and the upper layer side insulating film 307 of the first metal film 303C by the first metal film 303C, respectively. The metal film 307B, the metal film 308B, and the p provided in the p-type well 301A under the first connection hole 307A in the contact hole (the first connection hole 307A, the second connection hole 308A) provided in the insulating film 308 The high-concentration diffusion layer (p + diffusion layer) 310 is formed in a stacked shape. Further, the first connection hole 307A connects the substrate 301 to the first metal film 303C, and the second connection hole 308A connects the first metal film 303C and the second metal film 304. The p-type high concentration diffusion layer 310 surrounds the periphery of the voltage dividing resistor circuit element 302 in a plan view from the outermost surface side of the semiconductor device 300. That is, the same effects as those of the first embodiment and the second embodiment can be obtained by these configurations.
圖6的E-E'線的附近，為了使連接於電極部31A的電極引出層303A與未圖示的其他電路元件部分連接，於電極引出層303A朝分壓電阻電路元件302的外側延伸設置的部分，側壁部311具有接縫。In the vicinity of the line EE' in FIG. 6, the electrode lead-out layer 303A connected to the electrode portion 31A is connected to another circuit element portion (not shown), and is extended to the outside of the voltage-dividing resistor circuit element 302 in the electrode lead-out layer 303A. The portion of the side wall portion 311 has a seam.
因此，第三實施形態中，半導體裝置300進而於形成有分壓電阻電路元件302的區域、與形成有側壁部311的區域之間的區域具有多晶矽罩32。將多晶矽罩32以於在側壁部311存在接縫的部分，俯視時填補所述側壁部311的接縫的方式，配置於分壓電阻電路元件302的外側的區域。圖6中，多晶矽罩32於分壓電阻電路元件302的外側的區域中，相對於配置有電極部31A的右側與左側的邊而平行且呈直線地設置。Therefore, in the third embodiment, the semiconductor device 300 further has a polysilicon mask 32 in a region between the region where the voltage dividing resistor circuit element 302 is formed and the region where the sidewall portion 311 is formed. The polysilicon dome cover 32 is disposed in a region outside the voltage dividing resistor circuit element 302 so as to fill the seam of the side wall portion 311 in a portion where the side wall portion 311 has a seam. In FIG. 6, the polysilicon mask 32 is disposed in a line on the outer side of the voltage dividing resistor circuit element 302 in parallel with the right side and the left side where the electrode portion 31A is disposed.
如圖7（b）的剖面圖所示，多晶矽罩32是於多晶矽電阻器31的兩側的場絕緣膜306上，由與多晶矽電阻器31相同的多晶矽層形成。於多晶矽罩32上，將電極引出層303A較形成有第二金屬膜304的區域而更進一步朝外側延伸設置，無法於此處形成側壁部311。因此，氫有可能通過該側壁部311的接縫而侵入至多晶矽電阻器31。多晶矽罩32可吸收通過側壁部311的接縫而朝多晶矽電阻器31侵入的氫，從而減少到達多晶矽電阻器31的氫。As shown in the cross-sectional view of Fig. 7(b), the polysilicon mask 32 is formed on the field insulating film 306 on both sides of the polysilicon resistor 31, and is formed of the same polysilicon layer as the polysilicon resistor 31. On the polysilicon cap 32, the electrode lead-out layer 303A is extended further outward than the region in which the second metal film 304 is formed, and the side wall portion 311 cannot be formed there. Therefore, hydrogen may intrude into the polysilicon resistor 31 through the joint of the side wall portion 311. The polysilicon cap 32 absorbs hydrogen that has entered the polysilicon resistor 31 through the seam of the side wall portion 311, thereby reducing hydrogen reaching the polysilicon resistor 31.
一般而言，多晶矽與單晶矽不同，包括矽原子有規律地鍵結而成的結晶性高的晶粒（grain）部分、以及作為其邊界部分且矽原子的排列不規則的結晶性低的晶粒邊界部分。於晶粒邊界部分存在大量的具有未結合鍵的原子。原子的未結合鍵中容易鍵結有氫，因此根據其鍵結不均而多晶矽電阻器的電阻值不均。圖6中的多晶矽罩32利用該性質，配置於分壓電阻電路元件302的外側的區域，由此吸收自多晶矽罩32的外側浸入的氫，抑制向較形成有多晶矽罩32的區域更靠內側的區域的氫的侵入。In general, polycrystalline germanium differs from single crystal germanium in that it includes a grain portion having a high crystallinity in which germanium atoms are regularly bonded, and a crystal having low irregularity in arrangement of germanium atoms as a boundary portion thereof. Grain boundary portion. There are a large number of atoms with unbound bonds at the grain boundary portion. Hydrogen is easily bonded to the unbonded bond of the atom, and therefore the resistance value of the polysilicon resistor is not uniform depending on the bonding unevenness. The polysilicon cap 32 of FIG. 6 is disposed in a region outside the voltage dividing resistor circuit element 302 by this property, thereby absorbing hydrogen immersed from the outside of the polysilicon cap 32, and suppressing the inner side of the region in which the polysilicon cap 32 is formed. The intrusion of hydrogen into the area.
半導體裝置300除第二金屬膜304與側壁部311以外，於側壁部311的接縫附近具備多晶矽罩32，藉此可抑制自外部的氫的浸入，可較第二實施形態更有力地保護分壓電阻電路元件302。In addition to the second metal film 304 and the side wall portion 311, the semiconductor device 300 includes the polysilicon cover 32 in the vicinity of the joint of the side wall portion 311, whereby the intrusion of hydrogen from the outside can be suppressed, and the protective portion can be more strongly protected than the second embodiment. Piezoresistive circuit component 302.
圖6中，多晶矽罩32於分壓電阻電路元件302的外側的區域中，相對於配置有電極部31A的右側與左側的所有邊而平行且呈直線地設置，但並不限於該構成。即，亦可將多晶矽罩32局部配置於側壁部311的接縫的附近。另外，若俯視時於分壓電阻電路元件302的外側的區域的沿未配置有電極部31A的上側與下側的邊的部分存在側壁部311的接縫，則於該部分配置多晶矽罩32。另一方面，亦可以包圍分壓電阻電路元件302的整個周圍的方式無接縫地配置多晶矽罩32。藉此，可抑制來自任一方向的意外的氫的浸入，從而抑制多晶矽電阻器31的電阻值不均。In the region of the outer side of the voltage dividing resistor circuit element 302, the polysilicon buffer cover 32 is provided in parallel with the right side and the left side of the electrode portion 31A in a straight line, but is not limited to this configuration. That is, the polysilicon dome cover 32 may be partially disposed in the vicinity of the joint of the side wall portion 311. When the seam of the side wall portion 311 exists in a portion of the region outside the voltage dividing resistor circuit element 302 that is not disposed on the upper side and the lower side of the electrode portion 31A in plan view, the polysilicon dome cover 32 is disposed in this portion. On the other hand, the polysilicon mask 32 may be disposed without seams so as to surround the entire circumference of the voltage dividing resistor circuit element 302. Thereby, accidental hydrogen intrusion from any direction can be suppressed, and the resistance value unevenness of the polysilicon resistor 31 can be suppressed.
另外，多晶矽罩32的厚度較多晶矽電阻器31更厚時可減少氫浸入方向，因此遮蔽氫的效果高。圖7（a）及圖7（b）中，由相同的多晶矽層形成多晶矽電阻器31與多晶矽罩32。因此，無法使兩者的厚度不同，但可藉由以與多晶矽電阻器31不同的多晶矽層形成多晶矽罩32來實現厚度的不同。若多晶矽罩32為與多晶矽電阻器31不同的多晶矽層，厚度較多晶矽電阻器31更厚，則例如亦可利用場效型電晶體的閘極電極中所使用的多晶矽層、或調整電阻值的保險絲中所使用的多晶矽層（未圖示）。Further, when the thickness of the polysilicon mask 32 is larger than that of the wafer resistor 31, the hydrogen immersion direction can be reduced, so that the effect of shielding hydrogen is high. In FIGS. 7(a) and 7(b), the polysilicon resistor 31 and the polysilicon mask 32 are formed of the same polysilicon layer. Therefore, the thicknesses of the two cannot be made different, but the difference in thickness can be achieved by forming the polysilicon cap 32 with a polysilicon layer different from the polysilicon resistor 31. If the polysilicon mask 32 is a polysilicon layer different from the polysilicon resistor 31, and the thickness of the wafer resistor 31 is thicker, for example, a polysilicon layer used in a gate electrode of a field effect transistor or a resistance value may be used. A polysilicon layer (not shown) used in the fuse.
10、10A、10B‧‧‧多晶矽電阻器單元10, 10A, 10B‧‧‧ polysilicon resistor unit
11、21、31‧‧‧多晶矽電阻器11, 21, 31‧‧‧ Polysilicon resistors
11A、21A、31A‧‧‧電極部11A, 21A, 31A‧‧‧ electrode parts
11B、21B、31B‧‧‧高電阻部11B, 21B, 31B‧‧‧ High Resistance Section
12‧‧‧保險絲電路元件12‧‧‧Fuse circuit components
32‧‧‧多晶矽罩32‧‧‧ Polycrystalline hood
100、200、300‧‧‧半導體裝置100, 200, 300‧‧‧ semiconductor devices
101‧‧‧基板（n型基板）（基材）101‧‧‧Substrate (n-type substrate) (substrate)
101A、201A、301A‧‧‧p型阱101A, 201A, 301A‧‧‧p-type well
102、202、302‧‧‧分壓電阻電路元件102, 202, 302‧‧‧voltage resistor circuit components
102A‧‧‧分壓電阻電路102A‧‧‧voltage resistor circuit
103、203、203C、303、303C‧‧‧第一金屬膜103, 203, 203C, 303, 303C‧‧‧ first metal film
103A、203A、303A‧‧‧電極引出層103A, 203A, 303A‧‧‧ electrode extraction layer
103B、203B、303B‧‧‧被覆層103B, 203B, 303B‧‧‧ coating
104、204、304‧‧‧第二金屬膜104, 204, 304‧‧‧ second metal film
105、205、305‧‧‧氮化矽膜105, 205, 305‧‧‧ nitride film
106、206、306‧‧‧絕緣膜（場絕緣膜）106, 206, 306‧‧ ‧ insulating film (field insulating film)
107、207、307‧‧‧絕緣膜107, 207, 307‧‧ ‧ insulating film
108、208、308‧‧‧絕緣膜108, 208, 308‧‧ ‧ insulating film
109、209、309‧‧‧絕緣膜109, 209, 309‧‧ ‧ insulating film
201、301‧‧‧基板（n型基板）201, 301‧‧‧ substrate (n-type substrate)
207A、307A‧‧‧第一連接孔207A, 307A‧‧‧ first connection hole
207B、307B‧‧‧金屬膜207B, 307B‧‧‧ metal film
208A、308A‧‧‧第二連接孔208A, 308A‧‧‧ second connection hole
208B、308B‧‧‧金屬膜208B, 308B‧‧‧ metal film
210、310‧‧‧p型高濃度擴散層（p+擴散層）210, 310‧‧‧p type high concentration diffusion layer (p + diffusion layer)
211、311‧‧‧側壁部211, 311‧‧‧ side wall
Vdd、Vss‧‧‧電源電壓V dd , V ss ‧‧‧ power supply voltage
Vout‧‧‧輸出電壓Vout‧‧‧ output voltage
圖1是本發明的第一實施形態的半導體裝置的平面圖。 圖2（a）及圖2（b）是圖1的半導體裝置的剖面圖。 圖3是構成圖1、圖2（a）及圖2（b）的半導體裝置的分壓電阻電路的圖。 圖4是本發明的第二實施形態的半導體裝置的平面圖。 圖5是圖4的半導體裝置的剖面圖。 圖6是本發明的第三實施形態的半導體裝置的平面圖。 圖7（a）及圖7（b）是圖6的半導體裝置的剖面圖。Fig. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. 2(a) and 2(b) are cross-sectional views of the semiconductor device of Fig. 1. 3 is a view showing a voltage dividing resistor circuit constituting the semiconductor device of FIGS. 1, 2(a) and 2(b). Fig. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention. Figure 5 is a cross-sectional view of the semiconductor device of Figure 4 . Fig. 6 is a plan view showing a semiconductor device according to a third embodiment of the present invention. 7(a) and 7(b) are cross-sectional views of the semiconductor device of Fig. 6.
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