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TW201815240A - Element-embedded circuit board structures and methods for forming the same - Google Patents

Element-embedded circuit board structures and methods for forming the same Download PDF

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Publication number
TW201815240A
TW201815240A TW105132511A TW105132511A TW201815240A TW 201815240 A TW201815240 A TW 201815240A TW 105132511 A TW105132511 A TW 105132511A TW 105132511 A TW105132511 A TW 105132511A TW 201815240 A TW201815240 A TW 201815240A
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Taiwan
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component
board
heat dissipation
wire
circuit board
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TW105132511A
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Chinese (zh)
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張騰宇
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南亞電路板股份有限公司
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Priority to TW105132511A priority Critical patent/TW201815240A/en
Priority to CN201610948199.XA priority patent/CN107919334A/en
Publication of TW201815240A publication Critical patent/TW201815240A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

A element-embedded circuit board structure is provided. The includes a first core substrate having a first side and a second side opposite to the first side and an opening. A semiconductor element is disposed in the opening of the first core substrate, and there is a first gap between the semiconductor element and the first core substrate. A thermal-conductive glue fills the first gap, and a first wiring additional layered structure is disposed on the first side and covers the first core substrate, the semiconductor element and the thermal-conductive glue having a first blind hole located on the first core substrate, and having a first heat dissipation line is disposed in the first blind hole. A method for forming the element-embedded circuit board structure is also provided.

Description

元件埋入式電路板結構及其製造方法  Component embedded circuit board structure and manufacturing method thereof  

本發明係有關於埋入式元件的封裝技術,特別有關於具有散熱結構之元件埋入式電路板結構及其製造方法。 The present invention relates to a packaging technology for a buried component, and more particularly to a component buried circuit board structure having a heat dissipation structure and a method of fabricating the same.

在習知的封裝技術中,利用覆晶(flip chip,FC)方式或打線接合(WB,Wire Bonding)方式將主動元件與載板形成一封裝結構體(package),並將一個以上的封裝結構體進行堆疊或安裝於同一載板表面上。考量各元件間須互相透過線路連接及載板因產品限制而縮小其面積和體積等要求,使得佈線難度愈來愈高,故業界開始研發將主動或被動元件埋入載板內之技術。 In a conventional packaging technology, a flip chip (FC) method or a wire bonding (WB) method is used to form an active component and a carrier into a package structure, and more than one package structure is used. The bodies are stacked or mounted on the same carrier surface. Considering the requirement that each component must be connected to each other through the line and the carrier board is reduced in size and volume due to product limitations, the wiring is becoming more and more difficult. Therefore, the industry has begun to develop technology for embedding active or passive components in the carrier.

元件埋入式電路板結構中,基板會因不同材料結合,在不同生產環境及溫度下,產生不同應力變化,進而使基板產生形變彎曲或伸縮等變化,導致生產困難,對位不易,良率降低及信賴性表現不佳等影響。 In the embedded circuit board structure, the substrate will be combined with different materials, and different stress changes will occur in different production environments and temperatures, which will cause deformation or bending deformation of the substrate, resulting in production difficulties, misalignment, and yield. Reduced and affected by poor performance.

隨著電子產品之操作頻率愈來愈高且愈來愈多元件需安裝於同一載板上,主動元件與被動元件所產生之熱能持續增加,故對元件埋入式電路板結構而言,散熱能力與設計具 有其重要性。 As the operating frequency of electronic products is getting higher and higher and more and more components need to be mounted on the same carrier board, the thermal energy generated by the active components and the passive components continues to increase, so the heat dissipation of the component embedded circuit board structure Ability and design are important.

本發明的一些實施例提供元件埋入式電路板結構,包括:第一核心板,具有第一側和相對於第一側的第二側,且具有開口;半導體元件,設置於第一核心板的開口中,且半導體元件與第一核心板之間具有第一間隙;導熱膠,填滿第一間隙;第一線路增層結構,設置於第一側上並覆蓋第一核心板、半導體元件和導熱膠,具有第一盲孔位於第一核心板上,且具有第一散熱導線設置於第一盲孔中。 Some embodiments of the present invention provide an element buried circuit board structure including: a first core board having a first side and a second side opposite to the first side, and having an opening; and a semiconductor component disposed on the first core board And a first gap between the semiconductor element and the first core plate; a thermal conductive adhesive filling the first gap; and a first circuit build-up structure disposed on the first side and covering the first core plate and the semiconductor component And the thermal paste, the first blind hole is located on the first core plate, and the first heat dissipation wire is disposed in the first blind hole.

本發明的一些實施例提供元件埋入式電路板結構的製造方法,包括:提供載板;形成核心板於載板上,核心板具有第一側和相對於第一側的第二側,且具有開口;將半導體元件埋置於開口中,其中半導體元件與核心板之間具有間隙;將導熱膠填滿間隙;移除載板;形成線路增層結構於第一側上,覆蓋核心板、半導體元件和導熱膠,並在線路增層結構中形成盲孔於核心板上,其中線路增層結構具有散熱導線形成於盲孔中。 Some embodiments of the present invention provide a method of fabricating an element buried circuit board structure, comprising: providing a carrier board; forming a core board on the carrier board, the core board having a first side and a second side opposite to the first side, and Having an opening; embedding a semiconductor component in the opening, wherein the semiconductor component has a gap with the core plate; filling the gap with the thermal conductive adhesive; removing the carrier; forming a line build-up structure on the first side, covering the core plate, The semiconductor component and the thermal conductive paste form a blind via in the line build-up structure on the core board, wherein the line build-up structure has a heat dissipation lead formed in the blind via.

100、200、300、400、500、600‧‧‧元件埋入式電路板結構 100, 200, 300, 400, 500, 600‧‧‧ component embedded circuit board structure

101‧‧‧第一核心板 101‧‧‧First core board

101a‧‧‧第一側 101a‧‧‧ first side

101b‧‧‧第二側 101b‧‧‧ second side

101c、201a、301a‧‧‧開口 101c, 201a, 301a‧‧

102‧‧‧半導體元件 102‧‧‧Semiconductor components

103‧‧‧接觸墊 103‧‧‧Contact pads

104‧‧‧導熱膠 104‧‧‧thermal adhesive

105‧‧‧第一線路增層結構 105‧‧‧First line build-up structure

105a‧‧‧第一盲孔 105a‧‧‧First blind hole

105b‧‧‧第二盲孔 105b‧‧‧second blind hole

106‧‧‧第一散熱導線 106‧‧‧First heat sink

107‧‧‧電性連接結構 107‧‧‧Electrical connection structure

108‧‧‧第二線路增層結構 108‧‧‧Second line build-up structure

105c、108a‧‧‧第三盲孔 105c, 108a‧‧‧ third blind hole

108b、108a’‧‧‧第四盲孔 108b, 108a’‧‧‧4th blind hole

108b’‧‧‧第五盲孔 108b’‧‧‧ fifth blind hole

108c’‧‧‧第六盲孔 108c’‧‧‧6th blind hole

109、309‧‧‧第二散熱導線 109, 309‧‧‧second heat-dissipating wire

110、304‧‧‧第三散熱導線 110, 304‧‧‧ third cooling wire

111‧‧‧第一抗焊絕緣層 111‧‧‧First solder resist insulation

111a‧‧‧第一開孔 111a‧‧‧First opening

111b‧‧‧第二開孔 111b‧‧‧Second opening

111c、112a‧‧‧第三開孔 111c, 112a‧‧‧ third opening

112‧‧‧第二抗焊絕緣層 112‧‧‧Second solder resist insulation

112b、112a’‧‧‧第四開孔 112b, 112a’‧‧‧ fourth opening

112b’‧‧‧第五開孔 112b’‧‧‧ fifth opening

112c'‧‧‧第六開孔 112c'‧‧‧ sixth opening

120、220‧‧‧載板 120, 220‧‧‧ carrier board

201‧‧‧第二核心板 201‧‧‧Second core board

202‧‧‧單元 202‧‧‧ unit

203、305‧‧‧間隙 203, 305 ‧ ‧ gap

301‧‧‧無核心板 301‧‧‧No core board

302‧‧‧介電層 302‧‧‧Dielectric layer

303、502、503‧‧‧線路層 303, 502, 503‧‧‧ circuit layer

306‧‧‧第四散熱導線 306‧‧‧4th heat sink

307‧‧‧第五散熱導線 307‧‧‧Firmary heat sink

401、402、501、601‧‧‧散熱框 401, 402, 501, 601‧‧‧ heat dissipation frame

SC‧‧‧切割道 SC‧‧‧Cut Road

第1A-1E圖顯示依據本發明的一實施例之形成元件埋入式電路板結構的製造方法在各階段的剖面示意圖。 1A-1E is a cross-sectional view showing the manufacturing method of the device-embedded circuit board structure in accordance with an embodiment of the present invention at various stages.

第2圖顯示依據本發明的一實施例之第1A圖的上視圖。 Fig. 2 is a top view showing a first embodiment of Fig. 1A according to an embodiment of the present invention.

第3A-3F圖顯示依據本發明的另一實施例之形成元件埋入式電路板結構的製造方法在各階段的剖面示意圖。 3A-3F are cross-sectional views showing various stages of a method of fabricating an element buried circuit board structure in accordance with another embodiment of the present invention.

第4A-4F圖顯示依據本發明的又另一實施例之形成元件埋入式電路板結構的製造方法在各階段的剖面示意圖。 4A-4F are cross-sectional views showing the manufacturing method of the component-embedded circuit board structure in accordance with still another embodiment of the present invention at various stages.

第5圖顯示依據本發明的一實施例之元件埋入式電路板結構的剖面示意圖。 Figure 5 is a cross-sectional view showing the structure of an element buried circuit board in accordance with an embodiment of the present invention.

第6圖顯示依據本發明的另一實施例之元件埋入式電路板結構的剖面示意圖。 Figure 6 is a cross-sectional view showing the structure of an element buried circuit board in accordance with another embodiment of the present invention.

第7圖顯示依據本發明的又另一實施例之元件埋入式電路板結構的剖面示意圖。 Figure 7 is a cross-sectional view showing the structure of an element buried circuit board in accordance with still another embodiment of the present invention.

以下說明本發明實施例之元件埋入式電路板結構及元件埋入式電路板結構的製造方法。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。再者,在本發明實施例之圖式及說明內容中係使用相同的標號來表示相同或相似的部件。 Hereinafter, a component-embedded circuit board structure and a method of manufacturing a component-embedded circuit board structure according to an embodiment of the present invention will be described. However, it will be readily understood that the embodiments of the present invention are susceptible to many specific embodiments of the invention and can The specific embodiments disclosed are merely illustrative of the invention, and are not intended to limit the scope of the invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.

請先參照第1E圖,其顯示出依據本發明的一實施例之元件埋入式電路板結構100的剖面示意圖。電路板結構100包含第一核心板101,第一核心板101具有第一側101a和相對於第一側101a的第二側101b,且具有至少一開口101c貫穿第一核心板101(如第1A圖所示)。在本實施例中,第一核心板101可為剛性較佳、硬度較高且導熱的金屬材料。在一些實施例中,第一核心板101的金屬材料包含鋁、鉻、鎢、鈦、釩、銥或鍺等 硬度較高的金屬或合金。 Referring first to FIG. 1E, a cross-sectional view of a component buried circuit board structure 100 in accordance with an embodiment of the present invention is shown. The circuit board structure 100 includes a first core board 101 having a first side 101a and a second side 101b opposite to the first side 101a, and having at least one opening 101c extending through the first core board 101 (eg, 1A) Figure shows). In this embodiment, the first core plate 101 may be a metal material having better rigidity, higher hardness, and thermal conductivity. In some embodiments, the metal material of the first core plate 101 comprises a relatively hard metal or alloy such as aluminum, chromium, tungsten, titanium, vanadium, niobium or tantalum.

透過採用剛性較佳且導熱的金屬材料作為第一核心板101,第一核心板101較能夠承受在製造元件埋入式電路板結構100的過程中的應力變化,因此第一核心板101可改善元件埋入式電路板結構100變形的情況且具有快速散熱的功效。 By using a metal material having a relatively good rigidity and heat conductivity as the first core board 101, the first core board 101 can withstand the stress variation in the process of manufacturing the component buried circuit board structure 100, and thus the first core board 101 can be improved. The component buried circuit board structure 100 is deformed and has the effect of rapid heat dissipation.

元件埋入式電路板結構100包含半導體元件102,至少一半導體元件102設置於第一核心板101的開口101c中,且半導體元件102與第一核心板101之間相隔一距離而產生間隙。在一些實施例中,半導體元件102可包含例如電晶體或二極體之主動元件或例如電阻、電容或電感之被動元件。半導體元件102上方具有接觸墊103,接觸墊103用以電性連接半導體元件102與外部線路。另外,半導體元件102下方可具有導熱金屬層(未顯示)。在一些實施例中,導熱金屬層可包含鎳、金、錫、鉛、銅、鋁、銀、鉻、鎢、矽或其組合或上述之合金或其他合適的金屬材料。 The component embedded circuit board structure 100 includes a semiconductor component 102. The at least one semiconductor component 102 is disposed in the opening 101c of the first core board 101, and the semiconductor component 102 is spaced apart from the first core board 101 to create a gap. In some embodiments, semiconductor component 102 can comprise an active component such as a transistor or a diode or a passive component such as a resistor, capacitor, or inductor. Above the semiconductor component 102 is a contact pad 103 for electrically connecting the semiconductor component 102 to an external line. Additionally, a thermally conductive metal layer (not shown) may be beneath the semiconductor component 102. In some embodiments, the thermally conductive metal layer can comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, tantalum, or combinations thereof, or alloys of the foregoing or other suitable metallic materials.

導熱膠104填滿半導體元件102與第一核心板101之間的間隙,使半導體元件102固定至第一核心板101的開口101c中,且導熱膠104具有導熱的功能,可將半導體元件102產生的熱能傳導至第一核心板101。在一些實施例中,導熱膠104可包含矽及環氧樹脂,並添加鈹、鋁、銅等金屬或其氧化物,且會因應使用狀況不同加入玻璃纖維等強化材料。 The thermal conductive adhesive 104 fills the gap between the semiconductor component 102 and the first core board 101 to fix the semiconductor component 102 to the opening 101c of the first core board 101, and the thermal conductive adhesive 104 has a heat conducting function, and the semiconductor component 102 can be generated. The thermal energy is conducted to the first core board 101. In some embodiments, the thermal conductive adhesive 104 may comprise ruthenium and epoxy resin, and a metal such as ruthenium, aluminum, copper or the like or an oxide thereof may be added, and a reinforcing material such as glass fiber may be added depending on the use condition.

在本實施例中,元件埋入式電路板結構100包含第一線路增層結構105。第一線路增層結構105設置於第一核心板101的第一側101a上並覆蓋第一核心板101、半導體元件102和 導熱膠104,且第一線路增層結構105具有第一盲孔105a位於第一核心板101上和第二盲孔105b位於半導體元件102上的接觸墊103上。在一些實施例中,第一線路增層結構105可包含複數個垂直堆疊的絕緣層、形成於絕緣層之間的線路層和貫穿絕緣層且用以電性連接不同層之線路層的導通孔。為了圖式簡潔之目的,上述絕緣層、線路層和導通孔並未繪示於第一線路增層結構105中。 In the present embodiment, the component-embedded circuit board structure 100 includes a first line build-up structure 105. The first line build-up structure 105 is disposed on the first side 101a of the first core board 101 and covers the first core board 101, the semiconductor component 102 and the thermal paste 104, and the first line build-up structure 105 has a first blind via 105a. Located on the first core board 101 and the second blind via 105b are located on the contact pads 103 on the semiconductor component 102. In some embodiments, the first line build-up structure 105 may include a plurality of vertically stacked insulating layers, a circuit layer formed between the insulating layers, and a via hole penetrating the insulating layer and electrically connecting the circuit layers of the different layers. . The insulating layer, the wiring layer and the via holes are not shown in the first line build-up structure 105 for the sake of simplicity of the drawing.

在本實施例中,第一線路增層結構105具有第一散熱導線106設置於第一盲孔105a中,如此一來,半導體元件102產生的熱能傳導至第一核心板101之後,可透過第一散熱導線106將熱能向上傳導至元件埋入式電路板結構100的外部。在本實施例中,第一線路增層結構105具有電性連接結構107設置於第二盲孔105b中以電性連接半導體元件102與外部線路。在一些實施例中,第一散熱導線106和電性連接結構107可包含鎳、金、錫、鉛、銅、鋁、銀、鉻、鎢、矽或其組合或上述之合金或其他合適的金屬材料。 In this embodiment, the first line build-up structure 105 has the first heat-dissipating wire 106 disposed in the first blind hole 105a. Thus, after the heat energy generated by the semiconductor component 102 is transmitted to the first core plate 101, the first A heat sink wire 106 conducts thermal energy up to the exterior of the component buried circuit board structure 100. In this embodiment, the first line build-up structure 105 has an electrical connection structure 107 disposed in the second blind via 105b to electrically connect the semiconductor component 102 to the external line. In some embodiments, the first heat dissipation wire 106 and the electrical connection structure 107 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, tantalum or combinations thereof or alloys thereof or other suitable metals. material.

在一些實施例中,元件埋入式電路板結構100更包含第二線路增層結構108。第二線路增層結構108設置於第一核心板101的第二側101b上並位於第一核心板101、半導體元件102和導熱膠104下方,且第二線路增層結構108具有第三盲孔108a位於第一核心板101下方和第四盲孔108b位於半導體元件102下方。在一些實施例中,第二線路增層結構108與第一線路增層結構105的組成可相同,即第二線路增層結構108可包含複數個垂直堆疊的絕緣層、形成於絕緣層之間的線路層和貫穿絕 緣層且用以電性連接不同層之線路層的導通孔。 In some embodiments, the component buried circuit board structure 100 further includes a second line build structure 108. The second line build-up structure 108 is disposed on the second side 101b of the first core board 101 and under the first core board 101, the semiconductor component 102 and the thermal paste 104, and the second line build-up structure 108 has a third blind via 108a is located below the first core board 101 and the fourth blind via 108b is located below the semiconductor component 102. In some embodiments, the second line build-up structure 108 and the first line build-up structure 105 may have the same composition, that is, the second line build-up structure 108 may include a plurality of vertically stacked insulating layers formed between the insulating layers. a wiring layer and a via hole penetrating the insulating layer and electrically connecting the circuit layers of the different layers.

在本實施例中,第二線路增層結構108具有第二散熱導線109設置於第三盲孔108a中,如此一來,半導體元件102產生的熱能傳導至第一核心板101之後,可透過第二散熱導線109將熱能向下傳導至元件埋入式電路板結構100的外部。在本實施例中,第二線路增層結構108具有第三散熱導線110設置於第四盲孔108b中,如此一來,半導體元件102產生的熱能傳導至下方的導熱金屬層(未顯示)之後,可透過第三散熱導線110將熱能向下傳導至元件埋入式電路板結構100的外部。在一些實施例中,第二散熱導線109和第三散熱導線110可包含鎳、金、錫、鉛、銅、鋁、銀、鉻、鎢、矽或其組合或上述之合金或其他合適的金屬材料。 In this embodiment, the second line build-up structure 108 has the second heat-dissipating wire 109 disposed in the third blind hole 108a. Thus, after the heat energy generated by the semiconductor component 102 is transmitted to the first core board 101, the The two heat dissipating wires 109 conduct thermal energy downward to the outside of the component buried circuit board structure 100. In this embodiment, the second line build-up structure 108 has a third heat-dissipating wire 110 disposed in the fourth blind via 108b, such that the thermal energy generated by the semiconductor component 102 is conducted to the underlying thermally conductive metal layer (not shown). The thermal energy can be conducted downward through the third heat dissipation wire 110 to the outside of the component buried circuit board structure 100. In some embodiments, the second heat dissipating wire 109 and the third heat dissipating wire 110 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, tantalum or combinations thereof or alloys thereof or other suitable metals. material.

由於第一散熱導線106設置於第一線路增層結構105的第一盲孔105a中,第二散熱導線109設置於第二線路增層結構108的第三盲孔108a中,第三散熱導線110設置於第二線路增層結構108的第四盲孔108b中,半導體元件102產生的熱能可從多個方向傳導出去,且可有效增加半導體元件102的散熱導線的佈線位置和面積。此外,由於第一散熱導線106和第二散熱導線109設置於第一核心板101上而並非設置於半導體元件102上,第一散熱導線106和第二散熱導線109的配置可不受限且不佔用半導體元件102上的線路佈局。 The first heat dissipation wire 106 is disposed in the first blind hole 105a of the first circuit build-up structure 105, and the second heat dissipation wire 109 is disposed in the third blind hole 108a of the second circuit build-up structure 108. The third heat dissipation wire 110 is disposed. In the fourth blind via 108b of the second line build-up structure 108, the thermal energy generated by the semiconductor component 102 can be conducted out from a plurality of directions, and the wiring position and area of the heat-dissipating wires of the semiconductor component 102 can be effectively increased. In addition, since the first heat dissipation wires 106 and the second heat dissipation wires 109 are disposed on the first core plate 101 instead of being disposed on the semiconductor component 102, the configurations of the first heat dissipation wires 106 and the second heat dissipation wires 109 are not limited and are not occupied. The layout of the lines on the semiconductor component 102.

在一些實施例中,元件埋入式電路板結構100更包含第一抗焊絕緣層111和第二抗焊絕緣層112。第一抗焊絕緣層111和第二抗焊絕緣層112分別設置於第一線路增層結構105上 和第二線路增層結構108下方,第一抗焊絕緣層111具有第一開孔111a暴露出第一散熱導線106和第二開孔111b暴露出電性連接結構107,第二抗焊絕緣層112具有第三開孔112a暴露出第二散熱導線109和第四開孔112b暴露出第三散熱導線110。在一些實施例中,第一抗焊絕緣層111和第二抗焊絕緣層112可包含防焊材料(或稱綠漆),或可為包含聚亞醯胺(polyimide)、ABF膜(ajinomoto build-up film)或聚丙烯(polypropylene,PP)之絕緣材料,其可保護第一散熱導線106、電性連接結構107、第二散熱導線109和第三散熱導線110不被氧化或彼此短路。 In some embodiments, the component buried circuit board structure 100 further includes a first solder resist insulating layer 111 and a second solder resist insulating layer 112. The first solder resist insulating layer 111 and the second solder resist insulating layer 112 are respectively disposed on the first line build-up structure 105 and the second line build-up structure 108, and the first solder resist layer 111 has the first opening 111a exposed. The first heat dissipation wire 106 and the second opening 111b expose the electrical connection structure 107, and the second solder resist layer 112 has a third opening 112a exposing the second heat dissipation wire 109 and the fourth opening 112b exposing the third Heat sink wire 110. In some embodiments, the first solder resist insulating layer 111 and the second solder resist insulating layer 112 may comprise a solder resist material (or green paint), or may comprise a polyimide, an ABF film (ajinomoto build) An insulating material of polypropylene (PP), which protects the first heat dissipating wire 106, the electrical connection structure 107, the second heat dissipating wire 109, and the third heat dissipating wire 110 from being oxidized or shorted to each other.

請參照第1A-1E圖,其顯示依據本發明的一實施例之形成元件埋入式電路板結構100的製造方法在各階段的剖面示意圖。 Referring to FIGS. 1A-1E, there is shown a cross-sectional view of a method of fabricating a component-embedded circuit board structure 100 in various stages in accordance with an embodiment of the present invention.

如第1A圖所示,提供載板120,載板120表面具有黏著性。接著,利用載板120的表面黏著性將形成的第一核心板101貼附於載板120上,第一核心板101具有第一側101a和相對於第一側101a的第二側101b,第一核心板101的第二側101b黏著於載板120上。在將第一核心板101貼附於載板120之前,透過物理或化學方式形成至少一開口101c於第一核心板101中,開口101c的形狀則視埋入式元件之外型調整,任意形狀皆可。 As shown in FIG. 1A, a carrier 120 is provided, and the surface of the carrier 120 has adhesiveness. Next, the first core plate 101 formed by attaching the surface of the carrier 120 to the carrier 120 is attached. The first core plate 101 has a first side 101a and a second side 101b opposite to the first side 101a. The second side 101b of a core board 101 is adhered to the carrier board 120. Before attaching the first core board 101 to the carrier board 120, at least one opening 101c is physically or chemically formed in the first core board 101, and the shape of the opening 101c is adjusted according to the shape of the embedded component, any shape Can be.

第2圖顯示依據本發明的一實施例,第1A圖之第一核心板101和載板120的上視圖,在本實施例中,第一核心板101具有複數個開口101c,複數個開口101c可以任意的形式排列。 2 is a top view of the first core board 101 and the carrier board 120 of FIG. 1A according to an embodiment of the present invention. In this embodiment, the first core board 101 has a plurality of openings 101c, and a plurality of openings 101c. Can be arranged in any form.

在第1B圖中,將至少一半導體元件102埋置於第一 核心板101的開口101c中並位於載板120上,半導體元件102上方具有接觸墊103。半導體元件102與第一核心板101之間相隔一距離D而產生間隙,並將導熱膠104填滿此間隙。導熱膠104將第一核心板101和半導體元件102固定在一起,如此一來,如第1C圖所示,在填充導熱膠104之後,可移除載板120。 In Fig. 1B, at least one semiconductor element 102 is buried in the opening 101c of the first core board 101 and on the carrier board 120, and the semiconductor element 102 has a contact pad 103 thereon. The semiconductor element 102 is separated from the first core plate 101 by a distance D to create a gap, and the thermal conductive adhesive 104 fills the gap. The thermal paste 104 secures the first core board 101 and the semiconductor component 102 together, such that, as shown in FIG. 1C, after the thermal paste 104 is filled, the carrier 120 can be removed.

在第1D圖中,形成第一線路增層結構105於第一核心板101的第一側101a上並覆蓋第一核心板101、半導體元件102和導熱膠104,並形成第二線路增層結構108於第一核心板101的第二側101b上,且位於第一核心板101、半導體元件102和導熱膠104下方。接著,透過雷射鑽孔(laser drilling)或影像轉移等開孔製程,在第一線路增層結構105中形成第一盲孔105a於第一核心板101上和第二盲孔105b於半導體元件102上的接觸墊103上,並同時在第二線路增層結構108中形成第三盲孔108a於第一核心板101下方和第四盲孔108b於半導體元件102下方。接著,透過電鍍製程形成第一線路增層結構105的第一散熱導線106於第一盲孔105a中和第一線路增層結構105的電性連接結構107於第二盲孔105b中,並同時形成第二線路增層結構108的第二散熱導線109於第三盲孔108a中和第二線路增層結構108的第三散熱導線110於第四盲孔108b中。在一些實施例中,可重複形成其他線路增層結構(未顯示)於第一線路增層結構105上方或第二線路增層結構108下方,並同樣對其他線路增層結構實施開孔製程和電鍍製程,以形成多層結構。 In FIG. 1D, a first line build-up structure 105 is formed on the first side 101a of the first core board 101 and covers the first core board 101, the semiconductor component 102, and the thermal paste 104, and forms a second line build-up structure. 108 is on the second side 101b of the first core board 101 and is located below the first core board 101, the semiconductor component 102, and the thermal paste 104. Then, through the hole drilling process such as laser drilling or image transfer, the first blind via 105a is formed on the first core plate 101 and the second blind via 105b in the first line build-up structure 105. On the contact pad 103 on 102, and at the same time, a third blind via 108a is formed in the second line build-up structure 108 below the first core plate 101 and below the fourth blind via 108b under the semiconductor component 102. Then, the first heat dissipation wire 106 of the first line build-up structure 105 is formed in the first blind via 105a and the electrical connection structure 107 of the first line build-up structure 105 in the second blind via 105b through the electroplating process, and simultaneously The second heat dissipation wire 109 forming the second line build-up structure 108 is in the third blind hole 108a and the third heat dissipation wire 110 of the second line build-up structure 108 is in the fourth blind hole 108b. In some embodiments, other line build-up structures (not shown) may be repeatedly formed over the first line build-up structure 105 or under the second line build-up structure 108, and the opening process is also performed on other line build-up structures. An electroplating process to form a multilayer structure.

如第1E圖所示,以塗佈或貼附、壓附等物理方式形成第一抗焊絕緣層111於第一線路增層結構105上,以及形成 第二抗焊絕緣層112於第二線路增層結構108下方。接著,透過雷射鑽孔或影像轉移等開孔製程,在第一抗焊絕緣層111中形成第一開孔111a暴露出第一散熱導線106和第二開孔111b暴露出電性連接結構107,並透過雷射鑽孔或影像轉移等開孔製程,在第二抗焊絕緣層112中形成第三開孔112a暴露出第二散熱導線109和第四開孔112b暴露出第三散熱導線110,完成元件埋入式電路板結構100的製作。 As shown in FIG. 1E, the first solder resist layer 111 is formed on the first line build-up structure 105 by physical means such as coating or attaching, pressing, and the like, and the second solder resist layer 112 is formed on the second line. Below the buildup structure 108. Then, a first opening 111a is formed in the first solder resist insulating layer 111 by a hole drilling process such as laser drilling or image transfer, and the first heat dissipating wire 106 and the second opening 111b are exposed to expose the electrical connection structure 107. And forming a third opening 112a in the second solder resist insulating layer 112 to expose the second heat dissipating wire 109 and the fourth opening 112b to expose the third heat dissipating wire 110 through a hole drilling process such as laser drilling or image transfer. The fabrication of the component buried circuit board structure 100 is completed.

再者,請參照第3F圖,其顯示出依據本發明的一實施例之元件埋入式電路板結構200的剖面示意圖,其中相同於第1E圖中的部件係使用相同的標號並省略其說明。 Furthermore, please refer to FIG. 3F, which shows a cross-sectional view of the component-embedded circuit board structure 200 according to an embodiment of the present invention, wherein the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. .

第3F圖中的元件埋入式電路板結構200類似於第1E圖中的元件埋入式電路板結構100,差異處在於第3F圖的實施例中,第一核心板101、半導體元件102和導熱膠104組成一單元202,至少一單元202設置於第二核心板201的開口201a中,且單元202與第二核心板201之間相隔一距離而產生間隙203。再者,第一線路增層結構105更覆蓋第二核心板201並填滿單元202與第二核心板201之間的間隙203,第二線路增層結構108設置於單元202和第二核心板201下方。在本實施例中,第二核心板201的材料可為包含紙質酚醛樹脂(paper phenolic resin)、複合環氧樹脂(composite epoxy)、聚亞醯胺樹脂(polyimide resin)的樹脂材料。 The component buried circuit board structure 200 in FIG. 3F is similar to the component buried circuit board structure 100 in FIG. 1E except that in the embodiment of FIG. 3F, the first core board 101, the semiconductor element 102, and The thermal conductive adhesive 104 constitutes a unit 202. At least one unit 202 is disposed in the opening 201a of the second core board 201, and the unit 202 and the second core board 201 are separated by a distance to generate a gap 203. Furthermore, the first line build-up structure 105 further covers the second core board 201 and fills the gap 203 between the unit 202 and the second core board 201. The second line build-up structure 108 is disposed on the unit 202 and the second core board. Below 201. In this embodiment, the material of the second core plate 201 may be a resin material including a paper phenolic resin, a composite epoxy, and a polyimide resin.

透過採用剛性較佳且導熱的金屬材料作為第一核心板101,第一核心板101較能夠承受製造元件埋入式電路板結構200的過程中的應力變化,可藉由第一核心板101改善第二核 心板201之變形的情況。 By using the metal material with better rigidity and heat conduction as the first core board 101, the first core board 101 can withstand the stress variation in the process of manufacturing the component buried circuit board structure 200, and can be improved by the first core board 101. The case of deformation of the second core board 201.

請參照第3A-3F圖,其顯示依據本發明的一實施例之形成元件埋入式電路板結構200的製造方法在各階段的剖面示意圖,其中相同於第1A-1E圖中的部件係使用相同的標號並省略其說明。 Please refer to FIGS. 3A-3F, which are schematic cross-sectional views showing the manufacturing method of the component-embedded circuit board structure 200 according to an embodiment of the present invention, in which the components in the same manner as in the first A-1E diagram are used. The same reference numerals are used and the description thereof is omitted.

第3A-3F圖中的元件埋入式電路板結構200的製造方法在各階段的剖面示意圖類似於第1A-1E圖中的元件埋入式電路板結構100的製造方法在各階段的剖面示意圖,差異處在於第3C圖中,於第一核心板101的切割道SC處進行切割,以形成由第一核心板101、半導體元件102和導熱膠104組成的單元202。 The manufacturing method of the component-embedded circuit board structure 200 in the 3A-3F diagram is similar to the cross-sectional schematic diagram of the manufacturing method of the component-embedded circuit board structure 100 in FIG. 1A-1E at each stage. The difference is that in FIG. 3C, the cutting is performed at the scribe line SC of the first core board 101 to form the unit 202 composed of the first core board 101, the semiconductor element 102, and the thermal paste 104.

在第3D圖中,提供載板220,載板220表面具有黏著性。接著,利用載板220的表面黏著性將第二核心板201貼附於載板220上。在將第二核心板201貼附於載板220之前,透過物理或化學方法形成至少一開口201a於第二核心板201中。在一些實施例中,第二核心板201具有開口201a的上視圖可類似於第2圖顯示之第一核心板101具有開口101c的上視圖。 In the 3D drawing, the carrier 220 is provided, and the surface of the carrier 220 has adhesiveness. Next, the second core plate 201 is attached to the carrier 220 by the surface adhesion of the carrier 220. At least one opening 201a is formed in the second core plate 201 by physical or chemical means before the second core plate 201 is attached to the carrier 220. In some embodiments, the upper view of the second core panel 201 having the opening 201a can be similar to the top view of the first core panel 101 having the opening 101c as shown in FIG.

在形成具有開口201a的第二核心板201於載板220上之後,將至少一單元202放置於開口201a中並形成於載板220上,單元202與第二核心板201之間具有間隙203。 After the second core plate 201 having the opening 201a is formed on the carrier 220, at least one unit 202 is placed in the opening 201a and formed on the carrier 220, and a gap 203 is formed between the unit 202 and the second core plate 201.

在第3E圖中,形成第一線路增層結構105於第一核心板101的第一側101a上並覆蓋第二核心板201和單元202,且第一線路增層結構105填滿單元202與第二核心板201之間的間隙203。接著,由於第一線路增層結構105將第二核心板201和 單元202固定在一起,因此可移除載板220。接著,形成第二線路增層結構108於第一核心板101的第二側101b上,並位於單元202和第二核心板201下方。 In FIG. 3E, a first line build-up structure 105 is formed on the first side 101a of the first core board 101 and covers the second core board 201 and the unit 202, and the first line build-up structure 105 fills the unit 202 and A gap 203 between the second core plates 201. Next, since the first line build-up structure 105 secures the second core board 201 and the unit 202 together, the carrier board 220 can be removed. Next, a second line build-up structure 108 is formed on the second side 101b of the first core board 101 and below the unit 202 and the second core board 201.

接著,透過雷射鑽孔或影像轉移等開孔製程,在第一線路增層結構105中形成第一盲孔105a於第一核心板101上和第二盲孔105b於半導體元件102的接觸墊103上,並同時在第二線路增層結構108中形成第三盲孔108a於第一核心板101下方和第四盲孔108b於半導體元件102下方。接著,透過電鍍製程形成第一線路增層結構105的第一散熱導線106於第一盲孔105a中和第一線路增層結構105的電性連接結構107於第二盲孔105b中,並同時形成第二線路增層結構108的第二散熱導線109於第三盲孔108a中和第二線路增層結構108的第三散熱導線110於第四盲孔108b中。在一些實施例中,可重複形成其他線路增層結構(未顯示)於第一線路增層結構105上方或第二線路增層結構108下方,並同樣對其他線路增層結構實施開孔製程和電鍍製程,以形成多層結構。 Then, a contact pad of the first blind via 105a on the first core board 101 and the second blind via 105b on the semiconductor component 102 is formed in the first line build-up structure 105 by a hole drilling process such as laser drilling or image transfer. 103, and at the same time forming a third blind via 108a in the second line build-up structure 108 below the first core board 101 and the fourth blind via 108b below the semiconductor component 102. Then, the first heat dissipation wire 106 of the first line build-up structure 105 is formed in the first blind via 105a and the electrical connection structure 107 of the first line build-up structure 105 in the second blind via 105b through the electroplating process, and simultaneously The second heat dissipation wire 109 forming the second line build-up structure 108 is in the third blind hole 108a and the third heat dissipation wire 110 of the second line build-up structure 108 is in the fourth blind hole 108b. In some embodiments, other line build-up structures (not shown) may be repeatedly formed over the first line build-up structure 105 or under the second line build-up structure 108, and the opening process is also performed on other line build-up structures. An electroplating process to form a multilayer structure.

如第3F圖所示,以塗佈或貼附、壓附等物理方式形成第一抗焊絕緣層111於第一線路增層結構105上,並形成第二抗焊絕緣層112於第二線路增層結構108下方。接著,透過雷射鑽孔或影像轉移等開孔製程,在第一抗焊絕緣層111中形成第一開孔111a暴露出第一散熱導線106和第二開孔111b暴露出電性連接結構107,並透過雷射鑽孔或影像轉移等開孔製程,在第二抗焊絕緣層112中形成第三開孔112a暴露出第二散熱導線109和第四開孔112b暴露出第三散熱導線110,完成元件埋入 式電路板結構200的製作。 As shown in FIG. 3F, the first solder resist layer 111 is formed on the first line build-up structure 105 by physical means such as coating or attaching, pressing, etc., and the second solder resist layer 112 is formed on the second line. Below the buildup structure 108. Then, a first opening 111a is formed in the first solder resist insulating layer 111 by a hole drilling process such as laser drilling or image transfer, and the first heat dissipating wire 106 and the second opening 111b are exposed to expose the electrical connection structure 107. And forming a third opening 112a in the second solder resist insulating layer 112 to expose the second heat dissipating wire 109 and the fourth opening 112b to expose the third heat dissipating wire 110 through a hole drilling process such as laser drilling or image transfer. The fabrication of the component buried circuit board structure 200 is completed.

再者,請先參照第4F圖,其顯示出依據本發明的一實施例之元件埋入式電路板結構300的剖面示意圖,其中相同於第3F圖中的部件係使用相同的標號並省略其說明。 Furthermore, please refer to FIG. 4F, which shows a cross-sectional view of a component-embedded circuit board structure 300 according to an embodiment of the present invention, wherein components in the same manner as in FIG. 3F are given the same reference numerals and are omitted. Description.

第4F圖中的元件埋入式電路板結構300類似於第3F圖中的元件埋入式電路板結構200,差異處在於第4F圖中以無核心板301取代第二核心板201,即至少一單元202設置於無核心板301的開口301a中,且單元202與無核心板301之間具有間隙305。在一些實施例中,無核心板301中包含介電層302及設置於介電層302中的線路層303,亦即無核心板301不含有例如第一核心板101和第二核心板201的核心板材料,且無核心板301的厚度可小於第一核心板101和第二核心板201。 The component-embedded circuit board structure 300 in FIG. 4F is similar to the component-embedded circuit board structure 200 in FIG. 3F, except that the second core board 201 is replaced by the coreless board 301 in FIG. 4F, that is, at least A unit 202 is disposed in the opening 301a of the coreless board 301, and has a gap 305 between the unit 202 and the coreless board 301. In some embodiments, the coreless board 301 includes a dielectric layer 302 and a circuit layer 303 disposed in the dielectric layer 302, that is, the coreless board 301 does not include, for example, the first core board 101 and the second core board 201. The core board material, and the coreless board 301 may have a smaller thickness than the first core board 101 and the second core board 201.

透過採用剛性較佳且導熱的金屬材料作為第一核心板101,第一核心板101較能夠在製造承受元件埋入式電路板結構300的過程中的應力變化,並且可藉由第一核心板101改善無核心板301之變形的情況。 By using a rigid and thermally conductive metal material as the first core plate 101, the first core plate 101 is more capable of undergoing stress changes during the process of receiving the component buried circuit board structure 300, and can be utilized by the first core board. 101 improves the deformation of the coreless board 301.

在第4F圖中,第一線路增層結構105更覆蓋無核心板301並填滿單元202與無核心板301之間的間隙305,且第一線路增層結構105具有第三盲孔105c暴露出無核心板301的線路層303,且第一線路增層結構105具有第二散熱導線309設置於第三盲孔105c中。再者,第一散熱導線106和第二散熱導線309相互連接,無核心板301的線路層303透過第一線路增層結構105的第一散熱導線106及第二散熱導線309連接第一核心板101。 In FIG. 4F, the first line build-up structure 105 further covers the coreless board 301 and fills the gap 305 between the unit 202 and the coreless board 301, and the first line build-up structure 105 has the third blind hole 105c exposed. The circuit layer 303 of the core board 301 is absent, and the first line build-up structure 105 has a second heat dissipation wire 309 disposed in the third blind hole 105c. Furthermore, the first heat dissipation wire 106 and the second heat dissipation wire 309 are connected to each other, and the circuit layer 303 of the coreless board 301 is connected to the first core board through the first heat dissipation wire 106 and the second heat dissipation wire 309 of the first line build-up structure 105. 101.

在本實施例中,第二線路增層結構108設置於單元202和無核心板301下方,且具有第四盲孔108a’位於第一核心板101下方、第五盲孔108b’位於無核心板301下方和第六盲孔108c’位於半導體元件102下方,且第二線路增層結構108具有第三散熱導線304設置於第四盲孔108a’中、第四散熱導線306設置於第五盲孔108b’中和第五散熱導線307設置於第六盲孔108c’中。在本實施例中,第三散熱導線304和第四散熱導線306相互連接。 In this embodiment, the second line build-up structure 108 is disposed under the unit 202 and the coreless board 301, and has a fourth blind hole 108a' located below the first core board 101, and a fifth blind hole 108b' located on the coreless board. The lower and third blind holes 108c' are located below the semiconductor component 102, and the second circuit build-up structure 108 has a third heat-dissipating wire 304 disposed in the fourth blind hole 108a', and the fourth heat-dissipating wire 306 is disposed in the fifth blind hole. The 108b' neutralizing fifth heat dissipating wire 307 is disposed in the sixth blind hole 108c'. In the embodiment, the third heat dissipation wire 304 and the fourth heat dissipation wire 306 are connected to each other.

在本實施例中,第一抗焊絕緣層111和第二抗焊絕緣層112分別設置於第一線路增層結構105上以及第二線路增層結構108下方。第一抗焊絕緣層111具有第一開孔111a暴露出第一散熱導線106、第二開孔111b暴露出電性連接結構107和第三開孔111c暴露出第二散熱導線309,第二抗焊絕緣層112具有第四開孔112a’暴露出第三散熱導線304、第五開孔112b’暴露出第四散熱導線306和第六開孔112c’暴露出第五散熱導線307。 In the present embodiment, the first solder resist insulating layer 111 and the second solder resist insulating layer 112 are respectively disposed on the first line build-up structure 105 and below the second line build-up structure 108. The first solder resist insulating layer 111 has a first opening 111a exposing the first heat dissipating wire 106, the second opening 111b exposing the electrical connecting structure 107, and the third opening 111c exposing the second heat dissipating wire 309, the second anti-resistance The soldering insulating layer 112 has a fourth opening 112a' exposing the third heat dissipating wire 304, and the fifth opening 112b' exposing the fourth heat dissipating wire 306 and the sixth opening 112c' exposing the fifth heat dissipating wire 307.

透過上述配置,半導體元件102產生的熱能可依序透過導熱膠104、第一核心板101、第一線路增層結構105的第一散熱導線106和第二散熱導線309向上傳導至元件埋入式電路板結構300的外部,且半導體元件102產生的熱能也可依序透過導熱膠104、第一核心板101、第二線路增層結構108的第三散熱導線304和第四散熱導線306向下傳導至元件埋入式電路板結構300的外部,另外半導體元件102產生的熱能更可從第五散熱導線307直接向下傳導至元件埋入式電路板結構300的外部,因此半導體元件102產生的熱能可從更多個方向傳導出 去,且可有效增加半導體元件102的散熱導線的佈線位置和面積。此外,由於第一散熱導線106和第三散熱導線304設置於第一核心板101上,第二散熱導線309和第四散熱導線306設置於無核心板301上,上述元件並非設置於半導體元件102上,因此第一散熱導線106、第二散熱導線309、第三散熱導線304和第四散熱導線306的配置可不受限於且不佔用半導體元件102上的線路佈局。 Through the above configuration, the thermal energy generated by the semiconductor component 102 can be sequentially transmitted through the thermal conductive adhesive 104, the first core board 101, the first heat dissipation lead 106 of the first line build-up structure 105, and the second heat dissipation lead 309 to the component embedded type. The heat generated by the semiconductor device 102 can also pass through the thermal adhesive 104, the first core plate 101, the third heat dissipation wire 304 of the second line buildup structure 108, and the fourth heat dissipation wire 306. Conducted to the outside of the component buried circuit board structure 300, and the thermal energy generated by the semiconductor component 102 is further directly conducted from the fifth heat dissipation wire 307 to the outside of the component buried circuit board structure 300, and thus the semiconductor component 102 generates Thermal energy can be conducted out from more directions, and the wiring position and area of the heat dissipation wires of the semiconductor element 102 can be effectively increased. In addition, since the first heat dissipation wires 106 and the third heat dissipation wires 304 are disposed on the first core plate 101, the second heat dissipation wires 309 and the fourth heat dissipation wires 306 are disposed on the coreless plate 301, and the components are not disposed on the semiconductor component 102. Therefore, the configuration of the first heat dissipation wire 106, the second heat dissipation wire 309, the third heat dissipation wire 304, and the fourth heat dissipation wire 306 may not be limited and does not occupy the line layout on the semiconductor component 102.

第4A-4F圖中的元件埋入式電路板結構300的製造方法在各階段的剖面示意圖類似於第3A-3F圖中的元件埋入式電路板結構200的製造方法在各階段的剖面示意圖,差異處在於第4D圖中,利用載板220的表面黏著性將形成的無核心板301貼附於載板220上。在將無核心板301黏著於載板220之前,透過影像轉移製程形成至少一開口301a於無核心板301中。在一些實施例中,無核心板301具有開口301a的上視圖可類似於第2圖顯示之第一核心板101具有開口101c的上視圖。 The manufacturing method of the component-embedded circuit board structure 300 in the 4A-4F diagram is similar to the cross-sectional schematic diagram of the manufacturing method of the component-embedded circuit board structure 200 in the 3A-3F diagram at each stage. The difference is that in the 4D drawing, the coreless board 301 formed by the surface adhesion of the carrier 220 is attached to the carrier 220. Before the coreless board 301 is adhered to the carrier 220, at least one opening 301a is formed in the coreless board 301 through the image transfer process. In some embodiments, the top view of the coreless board 301 having the opening 301a may be similar to the top view of the first core board 101 having the opening 101c as shown in FIG.

在形成無核心板301於載板220上之後,將至少一單元202放置於開口301a中並位於載板220上,單元202與無核心板301之間具有間隙305。 After forming the coreless board 301 on the carrier board 220, at least one unit 202 is placed in the opening 301a and on the carrier board 220, and there is a gap 305 between the unit 202 and the coreless board 301.

在第4E圖中,形成第一線路增層結構105於第一核心板101的第一側101a上並覆蓋無核心板301和單元202,且第一線路增層結構105填滿單元202與無核心板301之間的間隙305。接著,由於第一線路增層結構105將無核心板301和單元202固定在一起,因此可移除載板220。接著,形成第二線路增層結構108於第一核心板的第二側101b上,並位於單元202和無 核心板301下方。 In FIG. 4E, a first line build-up structure 105 is formed on the first side 101a of the first core board 101 and covers the coreless board 301 and the unit 202, and the first line build-up structure 105 fills the unit 202 and A gap 305 between the core plates 301. Next, since the first line build-up structure 105 secures the coreless board 301 and the unit 202 together, the carrier board 220 can be removed. Next, a second line build-up structure 108 is formed on the second side 101b of the first core board and below the unit 202 and the coreless board 301.

接著,透過雷射鑽孔或影像轉移等開孔製程,在第一線路增層結構105中形成第一盲孔105a於第一核心板101上、第二盲孔105b於半導體元件102上的接觸墊103上和第三盲孔105c暴露出無核心板301的線路層303,並同時在第二線路增層結構108中形成第四盲孔108a’於第一核心板101下方、第五盲孔108b’於無核心板301下方並暴露出無核心板301的線路層303和第六盲孔108c’於半導體元件102下方。接著,透過電鍍製程形成第一散熱導線106於第一盲孔105a中、電性連接結構107於第二盲孔105b中和第二散熱導線309於第三盲孔105c中,其中,第一散熱導線106與第二散熱導線309相互連接,並同時形成第三散熱導線304於第四盲孔108a’中、第四散熱導線306於第五盲孔108b’中和第五散熱導線307於第六盲孔108c’中。在一些實施例中,可重複形成其他線路增層結構(未顯示)於第一線路增層結構105上方或第二線路增層結構108下方,並同樣對其他線路增層結構實施開孔製程和電鍍製程,以形成多層結構。 Then, through the hole drilling process such as laser drilling or image transfer, the first blind via 105a is formed on the first core plate 101 and the second blind via 105b is on the semiconductor device 102. The pad layer 103 and the third blind hole 105c expose the circuit layer 303 without the core plate 301, and at the same time, the fourth blind hole 108a' is formed in the second circuit build-up structure 108 below the first core plate 101, and the fifth blind hole 108b' is below the coreless board 301 and exposes the circuit layer 303 and the sixth blind via 108c' of the coreless board 301 below the semiconductor component 102. Then, the first heat dissipation wire 106 is formed in the first blind hole 105a through the electroplating process, the electrical connection structure 107 is in the second blind hole 105b, and the second heat dissipation wire 309 is in the third blind hole 105c, wherein the first heat dissipation The wire 106 and the second heat-dissipating wire 309 are connected to each other, and at the same time, the third heat-dissipating wire 304 is formed in the fourth blind hole 108a', the fourth heat-dissipating wire 306 is in the fifth blind hole 108b', and the fifth heat-dissipating wire 307 is in the sixth In the blind hole 108c'. In some embodiments, other line build-up structures (not shown) may be repeatedly formed over the first line build-up structure 105 or under the second line build-up structure 108, and the opening process is also performed on other line build-up structures. An electroplating process to form a multilayer structure.

如第4F圖所示,以塗佈或貼附、壓附等物理方式形成第一抗焊絕緣層111於第一線路增層結構105上,以及形成第二抗焊絕緣層112於第二線路增層結構108下方。接著,透過雷射鑽孔或影像轉移等開孔製程,在第一抗焊絕緣層111中形成第一開孔111a暴露出第一散熱導線106、第二開孔111b暴露出電性連接結構107和第三開孔111c暴露出第二散熱導線309,並透過雷射鑽孔或影像轉移等開孔製程,在第二抗焊絕 緣層112中形成第四開孔112a’暴露出第三散熱導線304、形成第五開孔112b’暴露出第四散熱導線306和形成第六開孔112c’暴露出第五散熱導線307,完成元件埋入式電路板結構300的製作。 As shown in FIG. 4F, the first solder resist insulating layer 111 is formed on the first line build-up structure 105 by a coating or attaching, pressing, or the like, and the second solder resist layer 112 is formed on the second line. Below the buildup structure 108. Then, through the hole drilling process such as laser drilling or image transfer, the first opening 111a is formed in the first solder resist insulating layer 111 to expose the first heat dissipating wire 106, and the second opening 111b exposes the electrical connection structure 107. And the third opening 111c exposes the second heat-dissipating wire 309, and through the hole drilling process such as laser drilling or image transfer, forming a fourth opening 112a' in the second solder resist insulating layer 112 to expose the third heat-dissipating wire 304, forming a fifth opening 112b' exposing the fourth heat-dissipating wire 306 and forming a sixth opening 112c' exposing the fifth heat-dissipating wire 307, completing the fabrication of the component-embedded circuit board structure 300.

再者,請參照第5圖,其顯示出依據本發明的一實施例之元件埋入式電路板結構400的剖面示意圖,其中相同於第1E圖中的部件係使用相同的標號並省略其說明。 Furthermore, please refer to FIG. 5, which shows a cross-sectional view of a component-embedded circuit board structure 400 according to an embodiment of the present invention, wherein the same components as those in FIG. 1E are denoted by the same reference numerals and the description thereof is omitted. .

第5圖中的元件埋入式電路板結構400類似於第1E圖中的元件埋入式電路板結構100,差異處在於第5圖之元件埋入式電路板結構400更包含第一散熱框401和第二散熱框402,第一散熱框401和第二散熱框402分別設置於第一線路增層結構105的外側和第二線路增層結構108的外側。第一散熱框401和第二散熱框402分別為圍繞第一增層結構105和第二增層結構108的框架結構。 The component buried circuit board structure 400 in FIG. 5 is similar to the component buried circuit board structure 100 in FIG. 1E, except that the component buried circuit board structure 400 of FIG. 5 further includes a first heat dissipation frame. 401 and the second heat dissipation frame 402, the first heat dissipation frame 401 and the second heat dissipation frame 402 are respectively disposed outside the first line build-up structure 105 and outside the second line build-up structure 108. The first heat dissipation frame 401 and the second heat dissipation frame 402 are frame structures surrounding the first build-up structure 105 and the second build-up structure 108, respectively.

透過上述配置,半導體元件102產生的熱能可依序透過導熱膠104、第一核心板101、第一散熱框401和第二散熱框402傳導至元件埋入式電路板結構400的外部,半導體元件102產生的熱能可從更多個方向傳導出去,且可有效增加散熱面積。 Through the above configuration, the thermal energy generated by the semiconductor component 102 can be sequentially transmitted to the outside of the component buried circuit board structure 400 through the thermal conductive adhesive 104, the first core board 101, the first heat dissipation frame 401, and the second heat dissipation frame 402, and the semiconductor component The thermal energy generated by 102 can be conducted out in more directions and can effectively increase the heat dissipation area.

再者,透過第一散熱框401和第二散熱框402分別設置於第一線路增層結構105的外側和第二線路增層結構108的外側,可強化元件埋入式電路板結構400的整體結構強度,故可有效改善元件埋入式電路板結構400變形的情況。 Furthermore, the first heat dissipation frame 401 and the second heat dissipation frame 402 are respectively disposed on the outer side of the first line build-up structure 105 and the outer side of the second line build-up structure 108, thereby reinforcing the entirety of the component-embedded circuit board structure 400. The structural strength can effectively improve the deformation of the component-embedded circuit board structure 400.

關於第一散熱框401和第二散熱框402的製造方 法,在本實施例中,在第一線路增層結構105中形成第一盲孔105a和第二盲孔105b與在第二線路增層結構108中形成第三盲孔108a和第四盲孔108b的期間,同時透過雷射鑽孔或影像轉移等開孔製程,去除第一增層結構105和第二增層結構108的外圍邊緣部分。接著,在形成第一散熱導線106、電性連接結構107、第二散熱導線109和第三散熱導線110的期間,同時透過電鍍製程分別形成第一散熱框401和第二散熱框402於第一線路增層結構105的外側和第二線路增層結構108的外側。 Regarding the manufacturing method of the first heat dissipation frame 401 and the second heat dissipation frame 402, in the present embodiment, the first blind hole 105a and the second blind hole 105b are formed in the first line build-up structure 105 and the second line is added to the second line. During the formation of the third blind hole 108a and the fourth blind hole 108b in the structure 108, the peripheral edge portions of the first build-up structure 105 and the second build-up structure 108 are removed by an opening process such as laser drilling or image transfer. . Then, during the formation of the first heat dissipation wire 106, the electrical connection structure 107, the second heat dissipation wire 109, and the third heat dissipation wire 110, the first heat dissipation frame 401 and the second heat dissipation frame 402 are respectively formed through the plating process. The outside of the line build-up structure 105 and the outside of the second line build-up structure 108.

再者,請參照第6圖,其顯示出依據本發明的一些實施例之元件埋入式電路板結構500的剖面示意圖,其中相同於第3F圖中的部件係使用相同的標號並省略其說明。 Furthermore, please refer to FIG. 6 , which shows a cross-sectional view of a component-embedded circuit board structure 500 according to some embodiments of the present invention, wherein components in the same manner as in FIG. 3F are given the same reference numerals and their description is omitted. .

第6圖中的元件埋入式電路板結構500類似於第3F圖中的元件埋入式電路板結構200,差異處在於第6圖的元件埋入式電路板結構500更包含散熱框501,散熱框501設置於第一線路增層結構105、第二核心板201和第二線路增層結構108的外側。散熱框501為圍繞第一線路增層結構105、第二核心板201和第二線路增層結構108的框架結構。在本實施例中,散熱框501透過第一線路增層結構105的線路層502連接至第一核心板101和第一散熱導線106,且散熱框501也透過第二線路增層結構108的線路層503連接至第一核心板101和第二散熱導線109。 The component-embedded circuit board structure 500 in FIG. 6 is similar to the component-embedded circuit board structure 200 in FIG. 3F. The difference is that the component-embedded circuit board structure 500 of FIG. 6 further includes a heat dissipation frame 501. The heat dissipation frame 501 is disposed outside the first line build-up structure 105, the second core plate 201, and the second line build-up structure 108. The heat dissipation frame 501 is a frame structure surrounding the first line build-up structure 105, the second core plate 201, and the second line build-up structure 108. In this embodiment, the heat dissipation frame 501 is connected to the first core board 101 and the first heat dissipation line 106 through the circuit layer 502 of the first line build-up structure 105, and the heat dissipation frame 501 also passes through the line of the second line build-up structure 108. The layer 503 is connected to the first core board 101 and the second heat dissipation line 109.

透過上述配置,半導體元件102產生的熱能可依序透過導熱膠104、第一核心板101、第一線路增層結構105的線路層502(或第二線路增層結構108的線路層503)、散熱框501傳導至元件埋入式電路板結構500的外部,半導體元件102產生的 熱能可從更多個方向傳導出去,且可有效增加散熱面積。 Through the above configuration, the thermal energy generated by the semiconductor device 102 can sequentially pass through the thermal conductive adhesive 104, the first core board 101, the circuit layer 502 of the first line build-up structure 105 (or the circuit layer 503 of the second line build-up structure 108), The heat dissipation frame 501 is conducted to the outside of the component buried circuit board structure 500, and the thermal energy generated by the semiconductor component 102 can be conducted out from more directions, and the heat dissipation area can be effectively increased.

再者,透過散熱框501設置於第一線路增層結構105、第二核心板201和第二線路增層結構108的外側,可強化元件埋入式電路板結構500的整體結構強度,故可有效改善元件埋入式電路板結構500中之第二核心板201變形的情況。 Furthermore, the heat dissipation frame 501 is disposed outside the first line build-up structure 105, the second core plate 201, and the second line build-up structure 108, so that the overall structural strength of the component-embedded circuit board structure 500 can be strengthened. The case where the second core board 201 in the component buried circuit board structure 500 is deformed is effectively improved.

關於散熱框501的製造方法,在本實施例中,先透過機器鑽孔或影像轉移等開孔製程,去除第二核心板201的外圍邊緣部分。接著,在第一線路增層結構105中形成第一盲孔105a和第二盲孔105b以及在第二線路增層結構108中形成第三盲孔108a和第四盲孔108b的期間,透過雷射鑽孔或影像轉移等開孔製程,去除第一線路增層結構105和第二線路增層結構108的外圍邊緣部分。接著,在形成第一散熱導線106、電性連接結構107、第二散熱導線109和第三散熱導線110的期間,透過電鍍製程形成散熱框501於第一線路增層結構105、第二核心板201和第二線路增層結構108的外側。 Regarding the manufacturing method of the heat dissipation frame 501, in the present embodiment, the peripheral edge portion of the second core plate 201 is removed by an opening process such as machine drilling or image transfer. Next, a first blind via 105a and a second blind via 105b are formed in the first line build-up structure 105, and a third blind via 108a and a fourth blind via 108b are formed in the second trace build-up structure 108. An opening process such as drilling or image transfer is performed to remove the peripheral edge portions of the first line build-up structure 105 and the second line build-up structure 108. Then, during the formation of the first heat dissipation wire 106, the electrical connection structure 107, the second heat dissipation wire 109, and the third heat dissipation wire 110, the heat dissipation frame 501 is formed through the plating process to the first line build-up structure 105 and the second core board. 201 and the outer side of the second line buildup structure 108.

再者,請參照第7圖,其顯示出依據本發明的一實施例之元件埋入式電路板結構600的剖面示意圖,其中相同於第4F圖中的部件係使用相同的標號並省略其說明。 Furthermore, please refer to FIG. 7, which shows a cross-sectional view of a component-embedded circuit board structure 600 according to an embodiment of the present invention, wherein components in the same manner as in FIG. 4F are given the same reference numerals and their description is omitted. .

第7圖中的元件埋入式電路板結構600類似於第4F圖中的元件埋入式電路板結構300,差異處在於第7圖的元件埋入式電路板結構600更包含散熱框601,散熱框601設置於無核心板301、第一線路增層結構105及第二線路增層結構108的外側。散熱框601為圍繞無核心板301、第一線路增層結構105及第二線路增層結構108的框架結構。在本實施例中,散熱框601 透過無核心板301的線路層303和第一線路增層結構105的第一散熱導線106、第二散熱導線309以及第二線路增層結構108的第三散熱導線304、第四散熱導線306連接第一核心板101。 The component-embedded circuit board structure 600 in FIG. 7 is similar to the component-embedded circuit board structure 300 in FIG. 4F. The difference is that the component-embedded circuit board structure 600 of FIG. 7 further includes a heat dissipation frame 601. The heat dissipation frame 601 is disposed outside the coreless board 301, the first line build-up structure 105, and the second line build-up structure 108. The heat dissipation frame 601 is a frame structure surrounding the coreless board 301, the first line build-up structure 105, and the second line build-up structure 108. In this embodiment, the heat dissipation frame 601 is transmitted through the circuit layer 303 of the coreless board 301 and the first heat dissipation wire 106, the second heat dissipation wire 309 of the first line buildup structure 105, and the third heat dissipation of the second line buildup structure 108. The wire 304 and the fourth heat dissipation wire 306 are connected to the first core plate 101.

透過上述配置,半導體元件102產生的熱能可依序透過導熱膠104、第一核心板101、第一線路增層結構105的第一散熱導線106、第二散熱導線309、無核心板301的線路層303、散熱框601或導熱膠104、第一核心板101、第二線路增層結構108的第三散熱導線304、第四散熱導線306、無核心板301的線路層303、散熱框601傳導至元件埋入式電路板結構600的外部,半導體元件102產生的熱能可從更多個方向傳導出去,且可有效增加散熱面積。 Through the above configuration, the thermal energy generated by the semiconductor component 102 can sequentially pass through the thermal conductive adhesive 104, the first core board 101, the first heat dissipation lead 106 of the first line build-up structure 105, the second heat dissipation lead 309, and the line without the core board 301. The layer 303, the heat dissipation frame 601 or the thermal conductive adhesive 104, the first core board 101, the third heat dissipation wire 304 of the second line build-up structure 108, the fourth heat dissipation wire 306, the circuit layer 303 of the coreless board 301, and the heat dissipation frame 601 are conducted. To the outside of the component buried circuit board structure 600, the thermal energy generated by the semiconductor component 102 can be conducted out from more directions, and the heat dissipation area can be effectively increased.

再者,透過散熱框601設置於第一線路增層結構105、無核心板301、第二線路增層結構108的外側,可強化元件埋入式電路板結構600的整體結構強度,故可有效改善埋入式元件的元件埋入式電路板結構600中之無核心板301變形的情況。 Furthermore, the heat dissipation frame 601 is disposed outside the first line build-up structure 105, the coreless board 301, and the second line build-up structure 108, thereby enhancing the overall structural strength of the component-embedded circuit board structure 600, thereby being effective. The case where the core-free board 301 in the component-embedded circuit board structure 600 of the embedded component is deformed is improved.

關於散熱框601的製造方法,在本實施例中,在形成至少一開口301a於無核心板301之前,先透過影像轉移等開孔製程,去除無核心板301的外圍邊緣部分。接著,在第一線路增層結構105中形成第一盲孔105a、第二盲孔105b和第三盲孔105c以及在第二線路增層結構108中形成第四盲孔108a’、第五盲孔108b’和第六盲孔108c’的期間,透過雷射鑽孔或影像轉移等開孔製程,去除第一線路增層結構105和第二線路增層結構108的外圍邊緣部份。接著,在形成第一散熱導線106、電性 連接結構107、第二散熱導線309、第三散熱導線304、第四散熱導線306和第五散熱導線307的期間,透過電鍍製程形成散熱框601於第一線路增層結構105、無核心板301和第二線路增層結構108的外側。 Regarding the manufacturing method of the heat dissipation frame 601, in the present embodiment, before the at least one opening 301a is formed in the coreless board 301, the peripheral edge portion of the coreless board 301 is removed by an opening process such as image transfer. Next, a first blind via 105a, a second blind via 105b and a third blind via 105c are formed in the first line build-up structure 105, and a fourth blind via 108a' is formed in the second trace build-up structure 108. During the hole 108b' and the sixth blind hole 108c', the peripheral edge portions of the first line build-up structure 105 and the second line build-up structure 108 are removed by an opening process such as laser drilling or image transfer. Then, during the formation of the first heat dissipation wire 106, the electrical connection structure 107, the second heat dissipation wire 309, the third heat dissipation wire 304, the fourth heat dissipation wire 306, and the fifth heat dissipation wire 307, the heat dissipation frame 601 is formed through the plating process. The outer side of the first line build-up structure 105, the coreless board 301, and the second line build-up structure 108.

根據本發明的一些實施例,透過採用剛性較佳且導熱的金屬材料作為第一核心板,第一核心板較能夠承受元件埋入式電路板結構在製造過程中的應力變化,因此可改善元件埋入式電路板結構變形的情況且具有快速散熱的功效。 According to some embodiments of the present invention, by using a metal material with better rigidity and heat conduction as the first core board, the first core board can withstand the stress change of the component embedded circuit board structure during the manufacturing process, thereby improving the component. The embedded circuit board structure is deformed and has the effect of rapid heat dissipation.

再者,由於第一散熱導線、第二散熱導線、第三散熱導線、第四散熱導線、第五散熱導線分別設置於不同位置的盲孔中,半導體元件產生的熱能可從多個方向傳導出去,且可有效增加半導體元件的散熱導線的佈線位置和面積。此外,由於散熱導線可設置於第一核心板和無核心板上而並非設置於半導體元件上,因此散熱導線的配置可不受限於且不佔用半導體元件上的線路佈局。 Furthermore, since the first heat dissipation wire, the second heat dissipation wire, the third heat dissipation wire, the fourth heat dissipation wire, and the fifth heat dissipation wire are respectively disposed in the blind holes at different positions, the heat energy generated by the semiconductor component can be conducted from multiple directions. And the wiring position and area of the heat dissipating wire of the semiconductor element can be effectively increased. In addition, since the heat dissipation wires can be disposed on the first core board and the coreless board instead of being disposed on the semiconductor element, the configuration of the heat dissipation wires can be unrestricted and does not occupy the line layout on the semiconductor elements.

再者,由於半導體元件產生的熱能可透過元件埋入式電路板結構外圍的散熱框傳導至元件埋入式電路板結構的外部,半導體元件產生的熱能可從更多個方向傳導出去,且可有效增加散熱面積。 Furthermore, since the thermal energy generated by the semiconductor component can be transmitted to the outside of the component buried circuit board structure through the heat dissipation frame around the component embedded circuit board structure, the thermal energy generated by the semiconductor component can be conducted from more directions, and Effectively increase the heat dissipation area.

另外,透過散熱框位於元件埋入式電路板結構的外側,可強化封裝結構的整體結構強度,故可有效改善元件埋入式電路板結構變形的情況。 In addition, the heat dissipation frame is located outside the component-embedded circuit board structure, and the overall structural strength of the package structure can be strengthened, so that the structural deformation of the component-embedded circuit board can be effectively improved.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不 脫離本發明之精神和範圍內,當可更動與組合上述各種實施例。 While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

Claims (22)

一種元件埋入式電路板結構,包括:一第一核心板,具有一第一側和相對於該第一側的一第二側,且具有一開口;一半導體元件,設置於該第一核心板的該開口中,且該半導體元件與該第一核心板之間具有一第一間隙;一導熱膠,填滿該第一間隙;以及一第一線路增層結構,設置於該第一側上並覆蓋該第一核心板、該半導體元件和該導熱膠,具有一第一盲孔位於該第一核心板上,且具有一第一散熱導線設置於該第一盲孔中。  An element embedded circuit board structure includes: a first core board having a first side and a second side opposite to the first side, and having an opening; a semiconductor component disposed on the first core In the opening of the board, and having a first gap between the semiconductor component and the first core board; a thermal conductive adhesive filling the first gap; and a first line build-up structure disposed on the first side The first core board, the semiconductor component and the thermal paste are disposed on the first core board, and a first heat dissipation lead is disposed in the first blind hole.   如申請專利範圍第1項所述之元件埋入式電路板結構,其中該第一核心板為金屬材料。  The component embedded circuit board structure of claim 1, wherein the first core board is a metal material.   如申請專利範圍第1項所述之元件埋入式電路板結構,其中該第一線路增層結構具有一第二盲孔位於該半導體元件上,且具有一電性連接結構設置於該第二盲孔中以電性連接至該半導體元件。  The component-embedded circuit board structure of claim 1, wherein the first line build-up structure has a second blind hole on the semiconductor component, and an electrical connection structure is disposed on the second The blind via is electrically connected to the semiconductor component.   如申請專利範圍第3項所述之元件埋入式電路板結構,更包括:一第二線路增層結構,設置於該第二側上並位於該第一核心板、該半導體元件和該導熱膠下方,且具有一第三盲孔位於該第一核心板下方和一第四盲孔位於該半導體元件 下方,該第二線路增層結構具有一第二散熱導線設置於該第三盲孔中和一第三散熱導線設置於該第四盲孔中。  The component-embedded circuit board structure of claim 3, further comprising: a second line build-up structure disposed on the second side and located on the first core board, the semiconductor component, and the heat conduction Under the glue, and having a third blind hole under the first core plate and a fourth blind hole under the semiconductor component, the second circuit build-up structure has a second heat dissipation wire disposed in the third blind hole And a third heat dissipation wire is disposed in the fourth blind hole.   如申請專利範圍第4項所述之元件埋入式電路板結構,更包括:一第一抗焊絕緣層和一第二抗焊絕緣層,分別設置於該第一線路增層結構上和該第二線路增層結構下方,該第一抗焊絕緣層具有一第一開孔暴露出該第一散熱導線和一第二開孔暴露出該電性連接結構,該第二抗焊絕緣層具有一第三開孔暴露出該第二散熱導線和一第四開孔暴露出該第三散熱導線。  The component embedded circuit board structure of claim 4, further comprising: a first solder resist insulating layer and a second solder resist insulating layer respectively disposed on the first line buildup structure and Under the second line build-up structure, the first solder resist insulating layer has a first opening exposing the first heat dissipating wire and a second opening exposing the electrical connection structure, the second solder resist insulating layer has A third opening exposes the second heat dissipation wire and a fourth opening exposes the third heat dissipation wire.   如申請專利範圍第4項所述之元件埋入式電路板結構,更包括一第一散熱框和一第二散熱框,分別設置於該第一線路增層結構的外側和該第二線路增層結構的外側。  The component-embedded circuit board structure of claim 4, further comprising a first heat dissipation frame and a second heat dissipation frame respectively disposed on an outer side of the first line build-up structure and the second line increase The outside of the layer structure.   如申請專利範圍第3項所述之元件埋入式電路板結構,更包括一第二核心板,其中該第一核心板、該半導體元件和該導熱膠組成一單元設置於該第二核心板的一開口中,且該單元與該第二核心板之間具有一第二間隙。  The component-embedded circuit board structure of claim 3, further comprising a second core board, wherein the first core board, the semiconductor component and the heat conductive adhesive comprise a unit disposed on the second core board In an opening, and a second gap between the unit and the second core plate.   如申請專利範圍第7項所述之元件埋入式電路板結構,其中該第二核心板為樹脂材料。  The component-embedded circuit board structure of claim 7, wherein the second core board is a resin material.   如申請專利範圍第7項所述之元件埋入式電路板結構,其中該第一線路增層結構更覆蓋該第二核心板並填滿該第二間隙。  The component-embedded circuit board structure of claim 7, wherein the first line build-up structure covers the second core board and fills the second gap.   如申請專利範圍第7項所述之元件埋入式電路板結構,更包括:一第二線路增層結構,設置於該單元和該第二核心板下方,且具有一第三盲孔位於該第一核心板下方和一第四盲孔位於該半導體元件下方,且該第二線路增層結構具有一第二散熱導線設置於該第三盲孔中和一第三散熱導線設置於該第四盲孔中。  The component-embedded circuit board structure of claim 7, further comprising: a second line build-up structure disposed under the unit and the second core board, and having a third blind hole located therein The first core plate and a fourth blind hole are located under the semiconductor component, and the second circuit build-up structure has a second heat dissipation wire disposed in the third blind hole and a third heat dissipation wire disposed on the fourth In the blind hole.   如申請專利範圍第10項所述之元件埋入式電路板結構,更包括:一第一抗焊絕緣層和一第二抗焊絕緣層,分別設置於該第一線路增層結構上和該第二線路增層結構下方,該第一抗焊絕緣層具有一第一開孔暴露出該第一散熱導線和一第二開孔暴露出該電性連接結構,該第二抗焊絕緣層具有一第三開孔暴露出該第二散熱導線和一第四開孔暴露出該第三散熱導線。  The component embedded circuit board structure of claim 10, further comprising: a first solder resist insulating layer and a second solder resist insulating layer respectively disposed on the first line buildup structure and Under the second line build-up structure, the first solder resist insulating layer has a first opening exposing the first heat dissipating wire and a second opening exposing the electrical connection structure, the second solder resist insulating layer has A third opening exposes the second heat dissipation wire and a fourth opening exposes the third heat dissipation wire.   如申請專利範圍第10項所述之元件埋入式電路板結構,更包括一散熱框,設置於該第一線路增層結構、該第二核心板和該第二線路增層結構的外側。  The component-embedded circuit board structure of claim 10, further comprising a heat dissipation frame disposed outside the first line build-up structure, the second core board, and the second line build-up structure.   如申請專利範圍第12項所述之元件埋入式電路板結構,其中該散熱框透過該第一線路增層結構的一線路層連接該第一核心板。  The component-embedded circuit board structure of claim 12, wherein the heat dissipation frame is connected to the first core board through a circuit layer of the first line build-up structure.   如申請專利範圍第3項所述之元件埋入式電路板結構,更包括一無核心板,該無核心板包括一介電層及一線路層設置於該介電層中,其中該第一核心板、該半導體元件和該導熱膠組成一單元設置於該無核心板的一開口中,且該單元與該無核心板之間具有一第三間隙。  The component-embedded circuit board structure of claim 3, further comprising a coreless board, wherein the coreless board comprises a dielectric layer and a circuit layer disposed in the dielectric layer, wherein the first layer The core board, the semiconductor component and the heat conductive adhesive comprise a unit disposed in an opening of the coreless board, and a third gap is formed between the unit and the coreless board.   如申請專利範圍第14項所述之元件埋入式電路板結構,其中該第一線路增層結構更覆蓋該無核心板並填滿該第三間隙,且具有一第三盲孔暴露出該無核心板的該線路層。  The component-embedded circuit board structure of claim 14, wherein the first line build-up structure covers the coreless board and fills the third gap, and has a third blind hole exposing the This circuit layer without a core board.   如申請專利範圍第15項所述之元件埋入式電路板結構,其中該第一線路增層結構具有一第二散熱導線設置於該第三盲孔中,且該第一散熱導線和該第二散熱導線相互連接。  The component-embedded circuit board structure of claim 15, wherein the first line build-up structure has a second heat-dissipating wire disposed in the third blind hole, and the first heat-dissipating wire and the first The two heat dissipation wires are connected to each other.   如申請專利範圍第15項所述之元件埋入式電路板結構,其中該無核心板的該線路層透過該第一線路增層結構的該第一散熱導線和該第二散熱導線連接該第一核心板。  The component-embedded circuit board structure of claim 15, wherein the circuit layer of the coreless board is connected to the first heat dissipation wire and the second heat dissipation wire of the first line build-up structure. A core board.   如申請專利範圍第16項或第17項所述之元件埋入式電路板結構,更包括:一第二線路增層結構,設置於該單元和該無核心板下方,且具有一第四盲孔位於該第一核心板下方、一第五盲孔位於該無核心板下方和一第六盲孔位於該半導體元件下方,且該第二線路增層結構具有一第三散熱導線設置於該 第四盲孔中、一第四散熱導線設置於該第五盲孔中和一第五散熱導線設置於該第六盲孔中,其中該第三散熱導線和該第四散熱導線相互連接。  The component-embedded circuit board structure of claim 16 or 17, further comprising: a second line build-up structure disposed under the unit and the coreless board and having a fourth blind a hole is located below the first core plate, a fifth blind hole is located under the coreless plate, and a sixth blind hole is located under the semiconductor component, and the second line build-up structure has a third heat dissipation wire disposed on the first A fourth heat-dissipating wire is disposed in the fifth blind hole, and a fifth heat-dissipating wire is disposed in the sixth blind hole, wherein the third heat-dissipating wire and the fourth heat-dissipating wire are connected to each other.   如申請專利範圍第18項所述之元件埋入式電路板結構,更包括:一第一抗焊絕緣層和一第二抗焊絕緣層,分別設置於該第一線路增層結構上和該第二線路增層結構下方,該第一抗焊絕緣層具有一第一開孔暴露出該第一散熱導線、一第二開孔暴露出該電性連接結構和一第三開孔暴露出該第二散熱導線,該第二抗焊絕緣層具有一第四開孔暴露出該第三散熱導線、一第五開孔暴露出該第四散熱導線和一第六開孔暴露出該第五散熱導線。  The component embedded circuit board structure of claim 18, further comprising: a first solder resist insulating layer and a second solder resist insulating layer respectively disposed on the first line buildup structure and Under the second line build-up structure, the first solder resist insulating layer has a first opening exposing the first heat dissipating wire, a second opening exposing the electrical connecting structure and a third opening exposing the a second heat dissipating wire, the second solder resist layer has a fourth opening exposing the third heat dissipating wire, a fifth opening exposing the fourth heat dissipating wire and a sixth opening exposing the fifth heat dissipating wire.   如申請專利範圍第16項所述之元件埋入式電路板結構,更包括一散熱框,設置於該無核心板的外側。  The component-embedded circuit board structure of claim 16 further includes a heat dissipation frame disposed outside the coreless board.   如申請專利範圍第19項所述之元件埋入式電路板結構,其中該散熱框透過該無核心板的該線路層和該第一線路增層結構的該第一散熱導線和該第二散熱導線連接該第一核心板。  The component-embedded circuit board structure of claim 19, wherein the heat dissipation frame passes through the circuit layer of the coreless board and the first heat dissipation wire and the second heat dissipation of the first line build-up structure A wire is connected to the first core board.   一種元件埋入式電路板結構的製造方法,包括:提供一載板;形成一核心板於該載板上,該核心板具有一第一側和相對於該第一側的一第二側,且具有一開口; 將一半導體元件埋置於該開口中,其中該半導體元件與該核心板之間具有一間隙;將一導熱膠填滿該間隙;移除該載板;形成一線路增層結構於該第一側上,覆蓋該核心板、該半導體元件和該導熱膠,並在該線路增層結構中形成一盲孔於該核心板上,其中該線路增層結構具有一散熱導線形成於該盲孔中。  A method of manufacturing a component-embedded circuit board structure includes: providing a carrier board; forming a core board on the carrier board, the core board having a first side and a second side opposite to the first side, And having an opening; embedding a semiconductor component in the opening, wherein the semiconductor component and the core plate have a gap; filling a gap with a thermal conductive adhesive; removing the carrier; forming a line buildup layer Forming on the first side, covering the core board, the semiconductor component and the thermal conductive adhesive, and forming a blind hole in the core layer in the line build-up structure, wherein the line build-up structure has a heat-dissipating wire formed In the blind hole.  
TW105132511A 2016-10-07 2016-10-07 Element-embedded circuit board structures and methods for forming the same TW201815240A (en)

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