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TW201801279A - 積體扇出型封裝體 - Google Patents

積體扇出型封裝體 Download PDF

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Publication number
TW201801279A
TW201801279A TW105136805A TW105136805A TW201801279A TW 201801279 A TW201801279 A TW 201801279A TW 105136805 A TW105136805 A TW 105136805A TW 105136805 A TW105136805 A TW 105136805A TW 201801279 A TW201801279 A TW 201801279A
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TW
Taiwan
Prior art keywords
conductive
memory element
integrated circuit
package
integrated
Prior art date
Application number
TW105136805A
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English (en)
Inventor
余振華
余國寵
Original Assignee
台灣積體電路製造股份有限公司
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Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201801279A publication Critical patent/TW201801279A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

一種積體扇出型封裝體，其包括積體電路、多個記憶體元件、絕緣封裝體以及重佈線路結構。記憶體元件與積體電路電性連接。積體電路與記憶體元件相互堆疊，且記憶體元件嵌於絕緣封裝體中。重佈線路結構配置於絕緣封裝體上，且重佈線路結構與積體電路以及記憶體元件電性連接。此外，上述積體扇出型封裝體的製造方法亦被提出。

Description

積體扇出型封裝體
本發明的實施例是有關於一種積體扇出型封裝體。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積集度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件能夠被整合到一預定區域內。較小的電子元件會需要比以往體積更小的封裝。較小型的半導體元件封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
近來，由於積體扇出型封裝體的高積集度(compactness)，積體扇出型封裝體提供了低功率消耗、高效能、較小的封裝體積以及較具競爭性的製造成本，因此積體扇出型封裝體已逐漸成為主流。如何增進積體扇出型封裝體的效能，且特別是在高密度、高功率方面的應用上，是相當重要的焦點。
依據本發明的一些實施例，積體扇出型封裝體包括積體電路、多個記憶體元件、絕緣封裝體以及重佈線路結構。記憶體元件與積體電路電性連接。積體電路與記憶體元件相互堆疊，且記憶體元件嵌於絕緣封裝體中。重佈線路結構配置於絕緣封裝體上，且重佈線路結構與積體電路以及記憶體元件電性連接。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地做出解釋。
圖1至圖8為依照一些實施例所繪示的一種積體扇出型封裝體的製造流程剖視圖。請參照圖1，提供一晶圓W，其包括陣列排列的多個積體電路110。在一些實施例中，積體電路110可為系統級晶片(System on Chip, SOC)積體電路。在對晶圓W進行晶圓切割製程之前，晶圓Ｗ中的積體電路110是相互連接的，如圖1所繪示。在一些實施例中，晶圓W包括半導體基板SUB以及多個形成在半導體基板SUB上的導電接墊PAD。舉例而言，半導體基板SUB可為包括有主動元件(例如電晶體或其他類似元件)以及(例如電阻器、電容器、電感或其他類似元件)形成於其上的矽基板；並且，導電接墊PAD可為鋁接墊、銅接墊或其他合適的金屬接墊。
在一些實施例中，晶圓W可選擇性地包括至少一形成在半導體基板SUB上的鈍化層（未繪示）。鈍化層可包括多個接觸開口，且導電接墊PAD被鈍化層的接觸開口所暴露。在一些實施例中，鈍化層的材質例如為聚醯亞胺(polyimide，PI)、聚苯噁唑(polybenzoxazole，PBO)或其他適合的聚合物或有機材料。
請參照圖2，於晶圓W上形成多個導電柱體120，以使導電柱體120與積體電路110接觸並且熱耦接至積體電路110。各個積體電路110可包括主動表面110a以及與主動表面110a相對的背面110b。部分的導電柱體120與積體電路110的主動表面110a接觸並且熱耦接至積體電路110的主動表面110a，而其餘的導電柱體120則與積體電路110的導電接墊PAD電性連接。換句話說，部分的導電柱體120為熱傳導柱體，用以傳導由積體電路110所產生的熱，而其餘的導電柱體120與積體電路110的導電接墊PAD電性連接，用以傳輸及接收信號。在一些其他實施例中，所有的導電柱體120皆與積體電路110的導電接墊PAD電性連接，用以傳輸及接收信號。
在一些實施例中，導電柱體120是電鍍在積體電路110上。用以製造導電柱體120的電鍍製程將於後進行詳細的描述。首先，通過濺鍍在晶圓W上形成種子層(seed layer)。接著，通過光刻製程在種子層上形成圖案化光阻層(未繪示)，其中對應於導電柱體120所在位置的種子層會被圖案化光阻層所暴露。包括有圖案化光阻層形成在其上的晶圓W會被浸入電鍍槽(plating bath)內的電鍍溶液，以使得導電柱體120被電鍍在種子層被暴露的部分上。在電鍍形成導電柱體120之後，將圖案化光阻層剝除。之後，以導電柱體120為罩幕，通過蝕刻將未被導電柱體120所覆蓋的部分種子層移除，直到積體電路110的主動表面110a被暴露為止。上述用以製造導電柱體120的電鍍製程僅是示例說明。然而，本發明不限於此。
請參照圖3，在晶圓W上形成多個記憶體元件體130，以使記憶體元件130與積體電路110接觸並且電性連接。記憶體元件130例如是通過覆晶接合(flip-chip bonding)製程以及底填(under-fill)製程而設置在晶圓W上。在一些實施例中，各個記憶體元件130包括多個相互堆疊的記憶體晶片132以及至少一個控制器134。各個記憶體晶片132包括多個微凸塊132a，且部分的記憶體晶片132包括多個導通孔132b(例如貫穿矽基材的導電通孔，TSV)。控制器134包括多個微凸塊134a以及多個與微凸塊134a電性連接的導通孔134b(例如貫穿矽基材的導電通孔，TSV)。通過微凸塊132a、導通孔132b以及導通孔134b，記憶體晶片132可與控制器134電性連接。通過控制器134的微凸塊134a，記憶體元件130能夠與晶圓W中的積體電路110電性連接。如圖3所示，位在最上方的記憶體晶片132中不需製作導電通孔。
如圖3所示，記憶體元件130例如為多個高頻寬記憶體堆疊結構(high bandwidth memory cubes)。然而，前述高頻寬記憶體堆疊結構僅為示例之用，然本發明不以此為限。
在一些實施例中，導電柱體120的高度可與記憶體元件130的厚度實質上相同。在一些其他實施例中，導電柱體120的高度可大於記憶體元件130的厚度。
如圖2與圖3所示，導電柱體120是在將記憶體元件130設置在晶圓W上之前形成。然而，本發明不限於此。在一些其他實施例中，導電柱體120可在將記憶體元件130設置在晶圓W上之後形成。
請參照圖4，在晶圓W形成絕緣封裝體140以包覆記憶體元件130以及導電柱體120，進而使得積體電路110、導電柱體120以及記憶體元件130可被嵌於絕緣封裝體140中。在一些實施例中，絕緣封裝體140可為模製製程所形成的封裝膠體。絕緣封裝體140的材料包括環氧化合物(epoxy)或其他合適的介電材料。
絕緣封裝體140可通過包覆型模製製程(over mold)以及研磨製程(grinding)形成。在一些實施例中，可通過包覆型模製製程在晶圓W上形成絕緣材料以全面性覆蓋導電柱體120以及記憶體元件130，接著，絕緣材料可通過機械研磨製程及/或化學機械研磨製程進行研磨，直到全部導電柱體120的頂表面以及記憶體元件130的頂表面被暴露為止。在一些實施例中，導電柱體120的頂表面以及記憶體元件130的頂表面同平面(在同一水平高度上)。
請參照圖5，在絕緣封裝體140形成之後，在絕緣封裝體140的頂表面、導電柱體120的頂表面以及記憶體元件130的頂表面上形成重佈線路結構150。在一些實施例中，重佈線路結構150熱耦接至跟積體電路110的主動表面110a熱耦接的部分導電柱體120，且重佈線路結構150電性連接至跟積體電路110的導電接墊PAD電性連接的其餘導電柱體120。當部分導電柱體120用以作為熱傳導柱體時，重佈線路結構150可包括多個與熱傳導柱體120熱耦接的導熱通孔。通過重佈線路結構150中的熱傳導柱體120以及導熱通孔，積體電路110所產生的熱可被有效率地傳導與逸散。
在一些實施例中，重佈線路結構150與全部的導電柱體120電性連接。雖然全部的導電柱體120皆是用以傳送及接收信號，導電柱體120仍能夠傳導積體電路110產生的熱。當全部的導電柱體120皆用以作為信號傳導柱體時，重佈線路結構150亦可包括多個與信號傳導柱體120熱耦接的導熱通孔。通過重佈線路結構150中的導電柱體120以及導熱通孔，積體電路110所產生的熱可被有效率地傳導與逸散。
如圖5所示，重佈線路結構150通過導電柱體120而與積體電路110以及記憶體元件130電性連接。在一些實施例中，重佈線路結構150通過導電柱體120以及積體電路110的線路層而與記憶體元件130電性連接。
請參照圖6，在重佈線路結構150形成之後，接著形成多個與重佈線路結構150電性連接的導電端子160。重佈線路結構150位在導電端子160以及記憶體元件130之間。換言之，導電端子160分佈在重佈線路結構150的一側，而積體電路110、導電柱體120以及記憶體元件130分佈在重佈線路結構150的另一側。在一些實施例中，導電端子160可為導電凸塊(conductive bumps)或導電球(conductive balls)。
請參照圖6與圖7，沿著切割線SL進行晶圓切割製程以將圖6中所繪示的結構單體化，進而形成多個單體化的封裝體100。在晶圓切割製程進行的期間，重佈線路結構150、絕緣封裝體140以及晶圓W會被切割以形成多個單體化的積體扇出型封裝體100。
如圖7所示，單體化的積體扇出型封裝體100包括積體電路110、記憶體元件130、絕緣封裝體140以及重佈線路結構150。記憶體元件130與積體電路110電性連接。積體電路110與記憶體元件130相互堆疊，且記憶體元件130嵌於絕緣封裝體140中。重佈線路結構150配置在絕緣封裝體140上，且重佈線路結構150與積體電路110以及記憶體元件130電性連接。在一些實施例中，可選擇性地形成導電端子160。
如圖7所示，積體扇出型封裝體100中的積體電路110未嵌於絕緣封裝體140中，且記憶體元件130配置在重佈線路結構150以及積體電路110之間。
請參照圖8，在單體化的積體扇出型封裝體100形成之後，可將其中一個單體化的積體扇出型封裝體100拾取並設置在封裝線路基板170上。單體化的積體扇出型封裝體100中的重佈線路結構150通過導電端子160與封裝線路基板170電性連接。在一些實施例中，封裝線路基板170可包括多個分佈在其底表面上的導電球172。舉例而言，導電球172可為焊料球或其他金屬球。值得注意的是，導電端子160的排列間距例如小於導電球172的排列間距。換句話說，具有導電球172排列於其上的封裝線路基板170可為球格陣列線路板，且球格陣列封裝體100a包括單體化的積體扇出型封裝體100以及封裝線路基板170。
如圖8所示，為了增進導電端子160的接合可靠度，可在重佈線路結構150與封裝線路基板170之間填入底填層180。底填層180包覆導電端子160以確保導電端子160的結構完整度，且由於重佈線路結構150與封裝線路基板170之間的熱膨脹係數差異，底填層180可確保其與重佈線路結構150與封裝線路基板170之間的接合介面。換句話說，熱膨脹係數差異所導致的剪應力可被底填層180所吸收，且導電端子160可被底填層180保護。
在一些實施例中，為了進一步增進散熱能力，可將散熱器190黏貼在積體電路100的背面100b上。舉例而言，散熱器190的材料包括鋁或其他適合的金屬材料。
圖9為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。請參照圖9，本實施例未使用高頻寬記憶體堆疊結構(HBM cubes)，而是使用與記憶體元件130(繪示於圖3中)不同架構的記憶體元件130a。值得注意的是，本發明的實施例不限定記憶體元件130a的數量。
圖10至圖17為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程剖視圖。
請參照圖10，提供具有剝離層DB形成於其上的載板C。在一些實施例中，載板C例如是玻璃基板，而剝離層DB例如是形成於玻璃基板上的光熱轉換釋放層(LTHC release layer)。然而，本發明的實施例不限定載板C與剝離層DB的材質。
在提供具有剝離層DB的載板C之後，可通過黏著層AD將多個記憶體元件130設置在剝離層DB以及載板C上。舉例而言，晶粒貼附製程中所使用的晶粒貼附薄膜(Die Attachment Film，DAF)可用以作為黏著層AD。在一些實施例中，各個記憶體元件130包括多個相互堆疊的記憶體晶片132以及至少一個控制器134。各個記憶體晶片132包括多個微凸塊132a，且部分的記憶體晶片132包括多個導通孔132b(例如貫穿矽基材的導電通孔，TSV)。控制器134包括多個與記憶體晶片132的微凸塊132a電性連接的導電通孔134b。通過微凸塊132a、導通孔132b以及導通孔134b，記憶體晶片132可與控制器134電性連接。如圖10所示，位在最下方的記憶體晶片132中不需製作導電通孔，且控制器134堆疊在記憶體晶片132下方。
如圖10所示，記憶體元件130例如為多個高頻寬記憶體堆疊結構(high bandwidth memory cubes)。然而，前述高頻寬記憶體堆疊結構僅為示例之用，然本發明不以此為限。
請參照圖11，將第一絕緣部分140a形成在剝離層DB以及載板C上以包覆記憶體元件130的側壁，進而使得記憶體元件130嵌於第一絕緣部分140a中。在一些實施例中，第一絕緣部分140a可為模製製程所形成的封裝膠體。第一絕緣部分140a的材料包括環氧化合物(epoxy)或其他合適的介電材料。
第一絕緣部分140a可通過包覆型模製製程(over mold)以及研磨製程(grinding)形成。在一些實施例中，可通過包覆型模製製程在剝離層DB以及載板C上形成絕緣材料以全面性覆蓋記憶體元件130，接著，絕緣材料可通過機械研磨製程及/或化學機械研磨製程進行研磨，直到記憶體元件130的頂表面被暴露為止。
請參照圖12，在記憶體元件130及/或第一絕緣部分140a上形成多個導電柱體120。在一些實施例中，在形成導電柱體120之前，可在記憶體元件130的頂表面及/或第一絕緣部分140a的頂表面上形成重佈線層RDL。導電柱體120例如是通過重佈線層RDL而與記憶體元件130電性連接。
在一些實施例中，導電柱體120是通過電鍍製程所形成。導電柱體120的電鍍製程將於後進行詳細的描述。首先，通過濺鍍在記憶體元件130的頂表面上以及第一絕緣部分140a的頂表面上形成種子層。接著，通過光刻製程在種子層上形成圖案化光阻層(未繪示)，其中對應於導電柱體120所在位置的種子層被圖案化光阻層所暴露。接著，進行電鍍製程以在種子層被暴露出的部分上形成導電柱體120。在電鍍形成導電柱體120之後，將圖案化光阻層剝除。之後，以導電柱體120為罩幕，通過蝕刻將未被導電柱體120所覆蓋的部分種子層移除，直到記憶體元件130的頂表面以及第一絕緣部分140a的頂表面被暴露為止。上述用以製造導電柱體120的電鍍製程僅是示例說明。然而，本發明不限於此。
請參照圖13，在形成導電柱體120之後，將積體電路110拾取並設置在記憶體元件130以及第一絕緣部分140a上。積體電路110例如是通過覆晶接合(flip-chip bonding)製程以及底填(under-fill)製程而設置在記憶體元件130上。積體電路110包括主動表面110a、與主動表面110a相對的背面110b，積體電路110的主動表面110a朝向記憶體元件130設置，且積體電路110通過多個位在主動表面110a與記憶體元件130之間的凸塊112與記憶體元件130電性連接。在一些實施例中，積體電路110通過位在積體電路110與記憶體元件130之間的重佈線層RDL與記憶體元件130電性連接。在一些其他實施例中，積體電路110可與記憶體元件130直接電性連接，且積體電路110可透過重佈線層RDL與導電柱體120直接電性連接。積體電路110、導電柱體120以及記憶體元件130之間的電性連接方式可依據不同設計需求更動，然本發明的實施例不限於此。
請參照圖14，在第一絕緣部分140a上形成第二絕緣部分140b以包覆積體電路110以及導電柱體120。在一些實施例中，第二絕緣部分140b可為模製製程所形成的封裝膠體。第二絕緣部分140b的材料包括環氧化合物(epoxy)或其他合適的介電材料。舉例而言，第一絕緣部分140a的材質可與第二絕緣部分140b的材質相同。
第二絕緣部分140b可通過包覆型模製製程(over mold)以及研磨製程(grinding)形成。在一些實施例中，可通過包覆型模製製程形成絕緣材料以包覆積體電路110以及導電柱體120，接著，絕緣材料可通過機械研磨製程及/或化學機械研磨製程進行研磨，直到積體電路110的背面110b以及全部導電柱體120的頂表面被暴露為止。在第二絕緣部分140b被研磨的期間，積體電路110以及導電柱體120會被研磨至相同水平高度。
第一絕緣部分140a以及第二絕緣部分140b構成絕緣封裝體140。如圖14所示，積體電路110、導電柱體120以及記憶體元件130嵌於絕緣封裝體140中。
在一些實施例中，導電柱體120的高度可與積體電路110的厚度以及第二絕緣部分140b的厚度實質上相同。
請參照圖15，在絕緣封裝體140形成之後，在絕緣封裝體140的頂表面、導電柱體120的頂表面以及積體電路110的背面110b上形成重佈線路結構150。在一些實施例中，導電柱體120與記憶體元件130以及重佈線路結構150電性連接。換句話說，重佈線路結構150通過導電柱體120以及重佈線層RDL而與積體電路110以及記憶體元件130電性連接。
在一些實施例中，重佈線路結構150包括多個與積體電路110的背面110b熱耦接的導熱通孔。通過重佈線路結構150中的導熱通孔以及導熱通孔，積體電路110所產生的熱可被有效率地傳導與逸散。
請參照圖16，在重佈線路結構150形成之後，接著形成多個與重佈線路結構150電性連接的導電端子160。積體電路110配置在重佈線路結構150以及記憶體元件130之間。換言之，導電端子160分佈在重佈線路結構150的一側，而積體電路110、導電柱體120以及記憶體元件130分佈在重佈線路結構150的另一側。在一些實施例中，導電端子160可為導電凸塊(conductive bumps)或導電球(conductive balls)。
如圖16所示，積體扇出型封裝體200包括積體電路110、記憶體元件130、絕緣封裝體140以及重佈線路結構150。記憶體元件130與積體電路110電性連接。重佈線路結構150配置在絕緣封裝體140上，且重佈線路結構150與積體電路110以及記憶體元件130電性連接。在一些實施例中，可選擇性地形成導電端子160。如圖16所示，在積體扇出型封裝體200中，積體電路110以及記憶體元件130嵌於絕緣封裝體140中。
請參照圖17，令積體扇出型封裝體200從剝離層DB以及載板C上剝離。在一些實施例中，剝離層DB(例如，光熱轉換釋放層)可被紫外光雷射照射以使得積體扇出型封裝體200能夠與剝離層DB以及載板C分離。積體扇出型封裝體200可被拾取並且設置在封裝線路基板170上。積體扇出型封裝體200中的重佈線路結構150通過導電端子160與封裝線路基板170電性連接。在一些實施例中，封裝線路基板170可包括多個分佈在其底表面上的導電球172。舉例而言，導電球172可為焊料球或其他金屬球。值得注意的是，導電端子160的排列間距例如小於導電球172的排列間距。換句話說，具有導電球172排列於其上的封裝線路基板170可為球格陣列線路板，且球格陣列封裝體200a包括積體扇出型封裝體200以及封裝線路基板170。
如圖17所示，為了增進導電端子160的接合可靠度，可在重佈線路結構150與封裝線路基板170之間填入底填層180。底填層180包覆導電端子160以確保導電端子160的結構完整度，且由於重佈線路結構150與封裝線路基板170之間的熱膨脹係數差異，底填層180可確保其與重佈線路結構150與封裝線路基板170之間的接合介面。換句話說，熱膨脹係數差異所導致的剪應力可被底填層180所吸收，且導電端子160可被底填層180保護。
在一些實施例中，為了進一步增進散熱能力，可將散熱器190黏貼在記憶體元件130被暴露出的表面上以及絕緣封裝體140的頂表面上。舉例而言，散熱器190的材料包括鋁或其他適合的金屬材料。
圖18以及圖19為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。請參照圖18與圖19，本實施例未使用高頻寬記憶體堆疊結構(HBM cubes)，而是使用與記憶體元件130(繪示於圖17中)不同架構的記憶體元件130a。值得注意的是，本發明的實施例不限定記憶體元件130a的數量。此外，如圖18所示，圖19中的封裝線路基板170在積體扇出型封裝體中是選擇性構件。
圖20至圖27為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程剖視圖。請參照圖20至圖22，圖20至圖22中的製程與圖10至圖12中的製程類似，故省略其詳細描述。
請參照圖23，在形成導電柱體120之後，將積體電路110拾取並設置在記憶體元件130以及第一絕緣部分140a上。舉例而言，積體電路110通過晶粒接合製程中所使用的晶粒貼附薄膜(DAF)而設置在記憶體元件130以及第一絕緣部分140a上。積體電路110包括主動表面110a以及與主動表面110a相對的背面110b，且積體電路110的背面110b朝向記憶體元件130。
請參照圖24，在第一絕緣部分140a上形成第二絕緣部分140b以包覆積體電路110以及導電柱體120。在一些實施例中，第二絕緣部分140b可為模製製程所形成的封裝膠體。第二絕緣部分140b的材料包括環氧化合物(epoxy)或其他合適的介電材料。舉例而言，第一絕緣部分140a的材質可與第二絕緣部分140b的材質相同。
第二絕緣部分140b可通過轉移模製製程(transfer mold)製程形成。在一些實施例中，通過轉移模製製程形成絕緣材料以包覆積體電路110以及導電柱體120，並且使積體電路110的主動表面110a以及導電柱體120的頂表面暴露。在一些實施例中，可通過包覆型模製製程形成絕緣材料以包覆積體電路110以及導電柱體120，接著，絕緣材料可通過機械研磨製程及/或化學機械研磨製程進行研磨，直到積體電路110的金屬柱體(未繪示)以及全部導電柱體120的頂表面被暴露為止。
第一絕緣部分140a以及第二絕緣部分140b構成絕緣封裝體140。如圖24所示，積體電路110、導電柱體120以及記憶體元件130嵌於絕緣封裝體140中。
請參照圖25，在絕緣封裝體140形成之後，在絕緣封裝體140的頂表面、導電柱體120的頂表面以及積體電路110的主動表面110a上形成重佈線路結構150。在一些實施例中，重佈線路結構150與積體電路110以及導電柱體120電性連接，且重佈線路結構150通過導電柱體120以及重佈線層RDL而與記憶體元件130電性連接。換句話說，積體電路110通過重佈線路結構150、導電柱體120以及重佈線層RDL與記憶體元件130電性連接。
在一些實施例中，重佈線路結構150包括多個與積體電路110的主動表面110a熱耦接的導熱通孔。通過重佈線路結構150中的導熱通孔以及導熱通孔，積體電路110所產生的熱可被有效率地傳導與逸散。
請參照圖26，在重佈線路結構150形成之後，接著形成多個與重佈線路結構150電性連接的導電端子160。請參照圖26，積體電路110配置在重佈線路結構150以及記憶體元件130之間。換言之，導電端子160分佈在重佈線路結構150的一側，而積體電路110、導電柱體120以及記憶體元件130分佈在重佈線路結構150的另一側。在一些實施例中，導電端子160可為導電凸塊(conductive bumps)或導電球(conductive balls)。
如圖26所示，積體扇出型封裝體300包括積體電路110、記憶體元件130、絕緣封裝體140以及重佈線路結構150。換句話說，記憶體元件130例如是通過重佈線路結構150、導電柱體120以及重佈線層RDL與積體電路110電性連接。積體電路110與記憶體元件130相互堆疊。在一些實施例中，可選擇性地形成導電端子160。
請參照圖27，令積體扇出型封裝體300從剝離層DB以及載板C上剝離。在一些實施例中，剝離層DB(例如，光熱轉換釋放層)可被紫外光雷射照射以使得積體扇出型封裝體300能夠與剝離層DB以及載板C分離。積體扇出型封裝體300可被拾取並且設置在封裝線路基板170上。積體扇出型封裝體300中的重佈線路結構150通過導電端子160與封裝線路基板170電性連接。在一些實施例中，封裝線路基板170可包括多個分佈在其底表面上的導電球172。舉例而言，導電球172可為焊料球或其他金屬球。值得注意的是，導電端子160的排列間距例如小於導電球172的排列間距。換句話說，具有導電球172排列於其上的封裝線路基板170可為球格陣列線路板，且球格陣列封裝體300a包括積體扇出型封裝體300以及封裝線路基板170。
如圖27所示，為了增進導電端子160的接合可靠度，可在重佈線路結構150與封裝線路基板170之間填入底填層180。底填層180包覆導電端子160以確保導電端子160的結構完整度，且由於重佈線路結構150與封裝線路基板170之間的熱膨脹係數差異，底填層180可確保其與重佈線路結構150與封裝線路基板170之間的接合介面。換句話說，熱膨脹係數差異所導致的剪應力可被底填層180所吸收，且導電端子160可被底填層180保護。
在一些實施例中，為了進一步增進散熱能力，可將散熱器190黏貼在記憶體元件130被暴露出的表面上以及絕緣封裝體140的表面上。舉例而言，散熱器190的材料包括鋁或其他適合的金屬材料。
圖28為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。請參照圖28，本實施例未使用高頻寬記憶體堆疊結構(HBM cubes)，而是使用與記憶體元件130(繪示於圖27中)不同架構的記憶體元件130a。值得注意的是，本發明的實施例不限定記憶體元件130a的數量。此外，圖28中的封裝線路基板170在積體扇出型封裝體中是選擇性構件。
在上述實施例中，積體電路110以及記憶體元件130的堆疊架構可以減小積體電路110的輸入/輸出介面與記憶體元件130之間的距離。據此，積體扇出型封裝體的效能(例如積體電路與記憶體元件之間的短信號傳輸路徑)可獲得增進。此外，基於積體電路110與記憶體元件130堆疊架構，積體扇出型封裝體的積集度可獲得增進。
依據本發明的一些實施例，積體扇出型封裝體包括積體電路、多個記憶體元件、絕緣封裝體以及重佈線路結構。記憶體元件與積體電路電性連接。積體電路與記憶體元件相互堆疊，且記憶體元件嵌於絕緣封裝體中。重佈線路結構配置於絕緣封裝體上，且重佈線路結構與積體電路以及記憶體元件電性連接。
在所述的積體扇出型封裝體中，積體電路與記憶體元件嵌於絕緣封裝體中。
在所述的積體扇出型封裝體中，各個記憶體元件包括：多個堆疊的記憶體晶片，各個記憶體晶片包括多個凸塊；以及控制器，其中記憶體晶片與控制器相互堆疊並且通過凸塊相互電性連接。
在所述的積體扇出型封裝體中，積體電路包括主動表面以及與主動表面相對的背面，積體電路的主動表面朝向記憶體元件，且積體電路通過位在主動表面與記憶體元件之間的凸塊與記憶體元件電性連接。
在所述的積體扇出型封裝體中，記憶體元件位在重佈線路結構與積體電路之間。此外，所述的積體扇出型封裝體進一步包括多個嵌於絕緣封裝體中的導電柱體，其中導電柱體與積體電路以及重佈線路結構電性連接。
在所述的積體扇出型封裝體中，積體電路位在重佈線路結構與記憶體元件之間。此外，所述的積體扇出型封裝體進一步包括多個嵌於絕緣封裝體中的導電柱體，其中導電柱體與積體電路以及重佈線路結構電性連接。
所述的積體扇出型封裝體進一步包括位於積體電路與記憶體元件之間的重佈線層，其中重佈線層位在記憶體元件的表面上，且記憶體元件通過重佈線層與積體電路電性連接。
在所述的積體扇出型封裝體中，積體電路包括主動表面以及與主動表面相對的背面，積體電路的背面朝向記憶體元件，積體電路的主動表面朝向重佈線路結構，且積體電路與重佈線路結構電性連接。
所述的積體扇出型封裝體進一步包括：多個嵌於絕緣封裝體中的導電柱體，導電柱體與記憶體元件以及重佈線路結構電性連接；以及位於記憶體元件的表面上的重佈線層，積體電路通過重佈線路結構、導電柱體以及重佈線層而與記憶體元件電性連接。
所述的積體扇出型封裝體進一步包括：多個與重佈線路結構電性連接的導電端子，其中重佈線路結構位在導電端子與記憶體元件之間。
所述的積體扇出型封裝體進一步包括封裝線路基板，其中重佈線路結構通過導電端子與封裝線路基板電性連接。
依據本揭露的另一些實施例，一種積體扇出型封裝體的製造方法被提出。將多個記憶體元件設置在一晶圓上，其中晶圓包括多個排列成陣列的積體電路，且記憶體元件與積體電路電性連接。在晶圓上形成絕緣封裝體以包覆記憶體元件。在絕緣封裝體以及記憶體元件上形成重佈線路結構配置，其中重佈線路結構與積體電路以及記憶體元件電性連接。切割重佈線路結構、絕緣封裝體以及晶圓，以形成多個單體化的封裝體。
所述的積體扇出型封裝體的製造方法進一步包括：在絕緣封裝體形成之前，在晶圓上形成多個導電柱體，其中導電柱體與積體電路電性連接，而在絕緣封裝體與重佈線路結構形成之後，導電柱體嵌於絕緣封裝體中並且與重佈線路結構電性連接。
所述的積體扇出型封裝體的製造方法進一步包括：形成多個與重佈線路結構電性連接的導電端子，其中重佈線路結構位在導電端子與記憶體元件之間。
所述的積體扇出型封裝體的製造方法進一步包括：將至少一個單體化的封裝體設置在封裝線路基板上，其中所述至少一個單體化的封裝體中的重佈線路結構通過導電端子與封裝線路基板電性連接。
依據本揭露的另一些實施例，一種積體扇出型封裝體的製造方法被提出。將多個記憶體元件設置在載板上。在載板上形成絕緣封裝體的第一絕緣部分，以包覆記憶體元件。將積體電路設置在記憶體元件上，其中積體電路與記憶體元件電性連接。在第一絕緣部分上形成絕緣封裝體的第二絕緣部分，以包覆積體電路。在絕緣封裝體以及積體電路上形成重佈線路結構配置，其中重佈線路結構與積體電路以及記憶體元件電性連接。
所述的積體扇出型封裝體的製造方法進一步包括：在絕緣封裝體的第二絕緣部分形成之前，在記憶體元件上形成多個導電柱體，其中導電柱體與積體電路以及記憶體元件電性連接，而在絕緣封裝體的第二絕緣部分與重佈線路結構形成之後，導電柱體嵌於導電柱體嵌於絕緣封裝體的第二絕緣部分中並且與重佈線路結構電性連接。
在所述的積體扇出型封裝體的製造方法中，積體電路包括主動表面以及與主動表面相對的背面，且在積體電路被設置在記憶體元件上之後，積體電路的主動表面或背面會朝向記憶體元件。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100、200、300‧‧‧積體扇出型封裝體
100a、200a、300a‧‧‧球格陣列封裝體
110‧‧‧積體電路
110a‧‧‧主動表面
110b‧‧‧背面
120‧‧‧導電柱體
130‧‧‧記憶體元件
132‧‧‧記憶體晶片
132a‧‧‧微凸塊
132b‧‧‧導通孔
134‧‧‧控制器
134a‧‧‧微凸塊
134b‧‧‧導通孔
140‧‧‧絕緣封裝體
150‧‧‧重佈線路結構
160‧‧‧導電端子
170‧‧‧封裝線路基板
172‧‧‧導電球
180‧‧‧底填層
190‧‧‧散熱器
AD‧‧‧黏著層
C‧‧‧載板
DB‧‧‧剝離層
PAD‧‧‧導電接墊
RDL‧‧‧重佈線層
SUB‧‧‧半導體基板
SL‧‧‧切割線
W‧‧‧晶圓
圖1至圖8為依照一些實施例所繪示的一種積體扇出型封裝體的製造流程剖視圖。 圖9為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。 圖10至圖17為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程剖視圖。 圖18以及圖19為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。 圖20至圖27為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程剖視圖。 圖28為依照一些其他實施例所繪示的積體扇出型封裝體的剖視圖。
100‧‧‧積體扇出型封裝體
100a‧‧‧球格陣列封裝體
110‧‧‧積體電路
110a‧‧‧主動表面
110b‧‧‧背面
120‧‧‧導電柱體
130‧‧‧記憶體元件
132‧‧‧記憶體晶片
132a‧‧‧微凸塊
132b‧‧‧導通孔
134‧‧‧控制器
134a‧‧‧微凸塊
134b‧‧‧導通孔
140‧‧‧絕緣封裝體
150‧‧‧重佈線路結構
160‧‧‧導電端子
170‧‧‧封裝線路基板
172‧‧‧導電球
180‧‧‧底填層
190‧‧‧散熱器
PAD‧‧‧導電接墊
SUB‧‧‧半導體基板
W‧‧‧晶圓

Claims (1)

  1. 一種積體扇出型封裝體，包括: 積體電路； 多個記憶體元件，與所述積體電路電性連接； 絕緣封裝體，所述積體電路與所述記憶體元件相互堆疊，且所述記憶體元件嵌於所述絕緣封裝體中；以及 重佈線路結構，配置於所述絕緣封裝體上，且所述重佈線路結構與所述積體電路以及所述記憶體元件電性連接。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662677B (zh) * 2018-01-10 2019-06-11 力成科技股份有限公司 堆疊式封裝結構及其製造方法
US11024603B2 (en) 2018-01-10 2021-06-01 Powertech Technology Inc. Manufacturing method and a related stackable chip package
TWI758151B (zh) * 2020-04-07 2022-03-11 聯發科技股份有限公司 半導體封裝結構
US11670596B2 (en) 2020-04-07 2023-06-06 Mediatek Inc. Semiconductor package structure
TWI841894B (zh) * 2020-12-25 2024-05-11 國立大學法人東京工業大學 半導體裝置及其製造方法
US12021031B2 (en) 2019-11-27 2024-06-25 Mediatek Inc. Semiconductor package structure
TWI852208B (zh) * 2022-01-31 2024-08-11 台灣積體電路製造股份有限公司 裝置封裝、積體電路封裝及方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10431738B2 (en) * 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US9865570B1 (en) * 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
TWI684260B (zh) * 2017-05-11 2020-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
KR102397902B1 (ko) 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
KR102587976B1 (ko) * 2018-02-06 2023-10-12 삼성전자주식회사 반도체 패키지
US11282776B2 (en) 2018-02-22 2022-03-22 Xilinx, Inc. High density routing for heterogeneous package integration
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10510629B2 (en) * 2018-05-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10867947B2 (en) * 2018-11-29 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US11107791B2 (en) * 2019-03-14 2021-08-31 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11282791B2 (en) * 2019-06-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a heat dissipation structure connected chip package
US11244906B2 (en) * 2020-05-22 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
US11562963B2 (en) * 2020-06-05 2023-01-24 Intel Corporation Stacked semiconductor package and method of forming the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
KR20220054118A (ko) * 2020-10-23 2022-05-02 삼성전자주식회사 적층 칩 패키지
US20240038702A1 (en) * 2022-07-27 2024-02-01 Adeia Semiconductor Bonding Technologies Inc. High-performance hybrid bonded interconnect systems

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US431738A (en) * 1890-07-08 blackman
US6004839A (en) * 1996-01-17 1999-12-21 Nec Corporation Semiconductor device with conductive plugs
KR100476694B1 (ko) * 2002-11-07 2005-03-17 삼성전자주식회사 반도체 장치의 퓨즈 구조물 및 그 제조 방법
WO2006123825A1 (en) * 2005-05-20 2006-11-23 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9449986B1 (en) * 2015-10-13 2016-09-20 Samsung Electronics Co., Ltd. 3-dimensional memory device having peripheral circuit devices having source/drain contacts with different spacings
US10431738B2 (en) * 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662677B (zh) * 2018-01-10 2019-06-11 力成科技股份有限公司 堆疊式封裝結構及其製造方法
US10354978B1 (en) 2018-01-10 2019-07-16 Powertech Technology Inc. Stacked package including exterior conductive element and a manufacturing method of the same
US11024603B2 (en) 2018-01-10 2021-06-01 Powertech Technology Inc. Manufacturing method and a related stackable chip package
US12021031B2 (en) 2019-11-27 2024-06-25 Mediatek Inc. Semiconductor package structure
TWI758151B (zh) * 2020-04-07 2022-03-11 聯發科技股份有限公司 半導體封裝結構
US11670596B2 (en) 2020-04-07 2023-06-06 Mediatek Inc. Semiconductor package structure
TWI841894B (zh) * 2020-12-25 2024-05-11 國立大學法人東京工業大學 半導體裝置及其製造方法
US12002781B2 (en) 2020-12-25 2024-06-04 Tokyo Institute Of Technology Semiconductor device and method for manufacturing same
TWI852208B (zh) * 2022-01-31 2024-08-11 台灣積體電路製造股份有限公司 裝置封裝、積體電路封裝及方法

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US11177434B2 (en) 2021-11-16
US20170373037A1 (en) 2017-12-28
US10431738B2 (en) 2019-10-01
CN107546193A (zh) 2018-01-05
US20190372000A1 (en) 2019-12-05
US10770655B2 (en) 2020-09-08

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